From patchwork Wed Feb 2 01:11:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kasireddy, Vivek" X-Patchwork-Id: 12732496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F41DFC433EF for ; Wed, 2 Feb 2022 01:28:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1EBB110E3F8; Wed, 2 Feb 2022 01:28:33 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3168210E3F8 for ; Wed, 2 Feb 2022 01:28:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643765312; x=1675301312; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=vTM3+QJBPbh1cN6MENgsShWKhIiFIhHPXrYpl8rILPI=; b=WU+U0n0OZxaTONECjnXjz7tuiBVjxS8GQovLNHzUO6Q7MZE+g8oNx68K Ac5OaRuRt20JHVEk9GJzRiZWveOPiY2S4zXEJykGhY4FtzLXn1VaZd8ym 7M2dU9XUoZNEbMTEwLXP4AoJDvgyTwS7SlRf6t++DASuUt2U3NiwA+NXW yijNkzmeXD6WHT72xwJ+RFXTLgEfUC3ARokTmv8kK9Z9MkVCVkNGn0b5P QqQUIQawUZ0fik0bzWMCsI9gzvN/MVazyU3qE973hh9+RXslavLzYvvmZ 11a1muaxWycbMdZf65qfy7E7YBZf7TRyK8aRa1FLCt54Qm1XU0DvVkes1 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10245"; a="247781737" X-IronPort-AV: E=Sophos;i="5.88,335,1635231600"; d="scan'208";a="247781737" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2022 17:28:31 -0800 X-IronPort-AV: E=Sophos;i="5.88,335,1635231600"; d="scan'208";a="497582404" Received: from vkasired-desk2.fm.intel.com ([10.105.128.127]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2022 17:28:31 -0800 From: Vivek Kasireddy To: intel-gfx@lists.freedesktop.org Date: Tue, 1 Feb 2022 17:11:35 -0800 Message-Id: <20220202011136.1387951-1-vivek.kasireddy@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/mm: Add an iterator to optimally walk over holes for an allocation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This iterator relies on drm_mm_first_hole() and drm_mm_next_hole() functions to identify suitable holes for an allocation of a given size by efficently traversing the rbtree associated with the given allocator. It replaces the for loop in drm_mm_insert_node_in_range() and can also be used by drm drivers to quickly identify holes of a certain size within a given range. Suggested-by: Tvrtko Ursulin Signed-off-by: Vivek Kasireddy --- drivers/gpu/drm/drm_mm.c | 28 ++++++++++++---------------- include/drm/drm_mm.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 8257f9d4f619..416c849c10e5 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -352,10 +352,10 @@ static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64 size) return node; } -static struct drm_mm_node * -first_hole(struct drm_mm *mm, - u64 start, u64 end, u64 size, - enum drm_mm_insert_mode mode) +struct drm_mm_node * +drm_mm_first_hole(struct drm_mm *mm, + u64 start, u64 end, u64 size, + enum drm_mm_insert_mode mode) { switch (mode) { default: @@ -374,6 +374,7 @@ first_hole(struct drm_mm *mm, hole_stack); } } +EXPORT_SYMBOL(drm_mm_first_hole); /** * DECLARE_NEXT_HOLE_ADDR - macro to declare next hole functions @@ -410,11 +411,11 @@ static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ DECLARE_NEXT_HOLE_ADDR(next_hole_high_addr, rb_left, rb_right) DECLARE_NEXT_HOLE_ADDR(next_hole_low_addr, rb_right, rb_left) -static struct drm_mm_node * -next_hole(struct drm_mm *mm, - struct drm_mm_node *node, - u64 size, - enum drm_mm_insert_mode mode) +struct drm_mm_node * +drm_mm_next_hole(struct drm_mm *mm, + struct drm_mm_node *node, + u64 size, + enum drm_mm_insert_mode mode) { switch (mode) { default: @@ -432,6 +433,7 @@ next_hole(struct drm_mm *mm, return &node->hole_stack == &mm->hole_stack ? NULL : node; } } +EXPORT_SYMBOL(drm_mm_next_hole); /** * drm_mm_reserve_node - insert an pre-initialized node @@ -520,7 +522,6 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm, { struct drm_mm_node *hole; u64 remainder_mask; - bool once; DRM_MM_BUG_ON(range_start > range_end); @@ -533,13 +534,8 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm, if (alignment <= 1) alignment = 0; - once = mode & DRM_MM_INSERT_ONCE; - mode &= ~DRM_MM_INSERT_ONCE; - remainder_mask = is_power_of_2(alignment) ? alignment - 1 : 0; - for (hole = first_hole(mm, range_start, range_end, size, mode); - hole; - hole = once ? NULL : next_hole(mm, hole, size, mode)) { + drm_mm_for_each_best_hole(hole, mm, range_start, range_end, size, mode) { u64 hole_start = __drm_mm_hole_node_start(hole); u64 hole_end = hole_start + hole->hole_size; u64 adj_start, adj_end; diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h index ac33ba1b18bc..5055447697fa 100644 --- a/include/drm/drm_mm.h +++ b/include/drm/drm_mm.h @@ -322,6 +322,17 @@ static inline u64 __drm_mm_hole_node_end(const struct drm_mm_node *hole_node) return list_next_entry(hole_node, node_list)->start; } +struct drm_mm_node * +drm_mm_first_hole(struct drm_mm *mm, + u64 start, u64 end, u64 size, + enum drm_mm_insert_mode mode); + +struct drm_mm_node * +drm_mm_next_hole(struct drm_mm *mm, + struct drm_mm_node *node, + u64 size, + enum drm_mm_insert_mode mode); + /** * drm_mm_hole_node_end - computes the end of the hole following @node * @hole_node: drm_mm_node which implicitly tracks the following hole @@ -400,6 +411,27 @@ static inline u64 drm_mm_hole_node_end(const struct drm_mm_node *hole_node) 1 : 0; \ pos = list_next_entry(pos, hole_stack)) +/** + * drm_mm_for_each_best_hole - iterator to optimally walk over all holes >= @size + * @pos: &drm_mm_node used internally to track progress + * @mm: &drm_mm allocator to walk + * @range_start: start of the allowed range for the allocation + * @range_end: end of the allowed range for the allocation + * @size: size of the allocation + * @mode: fine-tune the allocation search + * + * This iterator walks over all holes suitable for the allocation of given + * @size in a very efficient manner. It is implemented by calling + * drm_mm_first_hole() and drm_mm_next_hole() which identify the + * appropriate holes within the given range by efficently traversing the + * rbtree associated with @mm. + */ +#define drm_mm_for_each_best_hole(pos, mm, range_start, range_end, size, mode) \ + for (pos = drm_mm_first_hole(mm, range_start, range_end, size, mode); \ + pos; \ + pos = mode & DRM_MM_INSERT_ONCE ? \ + NULL : drm_mm_next_hole(mm, hole, size, mode)) + /* * Basic range manager support (drm_mm.c) */ From patchwork Wed Feb 2 01:11:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Kasireddy, Vivek" X-Patchwork-Id: 12732497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28B44C433F5 for ; Wed, 2 Feb 2022 01:28:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 454EE10E406; Wed, 2 Feb 2022 01:28:44 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 080A210E406 for ; Wed, 2 Feb 2022 01:28:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643765323; x=1675301323; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nTf+MD5e/VOww+utmGCWcE+iMKeQZzVTioDnJetCasQ=; b=NKMQMOczuxzaFjCDS84cAVvl8hWt0TxFhSCN0HKuWg3WNTLAnRSBI/Q9 Ml3Y+tBCBl+OVB+j1jKUi/aWmL+HOEOEe1KH5nEZF0f49yGvwKB81u2D3 /BqOw7tKgAHqDomoC8AzwOUuzmU7bCwqs7FnqOgwjTue5volsSijnsw+e ENrVgD8zwkngD+W8w7iTrihVPW4wdyVxHbVvAaYdXr3xtNuQwgjWn5WVI 0fjUY/7lipmnboEuABy/XDJSwsgNH7XH2LkCDKL90cdsVMArVRPea1uiQ gcXtJoIaFRccwnZ1xduHooEMOuauC/8P0hvjlvvzvTJ2pxjgTrRsYrLFU Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10245"; a="228488074" X-IronPort-AV: E=Sophos;i="5.88,335,1635231600"; d="scan'208";a="228488074" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2022 17:28:42 -0800 X-IronPort-AV: E=Sophos;i="5.88,335,1635231600"; d="scan'208";a="497582433" Received: from vkasired-desk2.fm.intel.com ([10.105.128.127]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2022 17:28:41 -0800 From: Vivek Kasireddy To: intel-gfx@lists.freedesktop.org Date: Tue, 1 Feb 2022 17:11:36 -0800 Message-Id: <20220202011136.1387951-2-vivek.kasireddy@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220202011136.1387951-1-vivek.kasireddy@intel.com> References: <20220202011136.1387951-1-vivek.kasireddy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Don't try to map and fence large scanout buffers (v5) X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or more framebuffers/scanout buffers results in only one that is mappable/ fenceable. Therefore, pageflipping between these 2 FBs where only one is mappable/fenceable creates latencies large enough to miss alternate vblanks thereby producing less optimal framerate. This mainly happens because when i915_gem_object_pin_to_display_plane() is called to pin one of the FB objs, the associated vma is identified as misplaced and therefore i915_vma_unbind() is called which unbinds and evicts it. This misplaced vma gets subseqently pinned only when i915_gem_object_ggtt_pin_ww() is called without PIN_MAPPABLE. This results in a latency of ~10ms and happens every other vblank/repaint cycle. Therefore, to fix this issue, we try to see if there is space to map at-least two objects of a given size and return early if there isn't. This would ensure that we do not try with PIN_MAPPABLE for any objects that are too big to map thereby preventing unncessary unbind. Testcase: Running Weston and weston-simple-egl on an Alderlake_S (ADLS) platform with a 8K@60 mode results in only ~40 FPS. Since upstream Weston submits a frame ~7ms before the next vblank, the latencies seen between atomic commit and flip event are 7, 24 (7 + 16.66), 7, 24..... suggesting that it misses the vblank every other frame. Here is the ftrace snippet that shows the source of the ~10ms latency: i915_gem_object_pin_to_display_plane() { 0.102 us | i915_gem_object_set_cache_level(); i915_gem_object_ggtt_pin_ww() { 0.390 us | i915_vma_instance(); 0.178 us | i915_vma_misplaced(); i915_vma_unbind() { __i915_active_wait() { 0.082 us | i915_active_acquire_if_busy(); 0.475 us | } intel_runtime_pm_get() { 0.087 us | intel_runtime_pm_acquire(); 0.259 us | } __i915_active_wait() { 0.085 us | i915_active_acquire_if_busy(); 0.240 us | } __i915_vma_evict() { ggtt_unbind_vma() { gen8_ggtt_clear_range() { 10507.255 us | } 10507.689 us | } 10508.516 us | } v2: Instead of using bigjoiner checks, determine whether a scanout buffer is too big by checking to see if it is possible to map two of them into the ggtt. v3 (Ville): - Count how many fb objects can be fit into the available holes instead of checking for a hole twice the object size. - Take alignment constraints into account. - Limit this large scanout buffer check to >= Gen 11 platforms. v4: - Remove existing heuristic that checks just for size. (Ville) - Return early if we find space to map at-least two objects. (Tvrtko) - Slightly update the commit message. v5: (Tvrtko) - Rename the function to indicate that the object may be too big to map into the aperture. - Account for guard pages while calculating the total size required for the object. - Do not subject all objects to the heuristic check and instead consider objects only of a certain size. - Do the hole walk using the rbtree. - Preserve the existing PIN_NONBLOCK logic. - Drop the PIN_MAPPABLE check while pinning the VMA. Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Tvrtko Ursulin Cc: Manasi Navare Signed-off-by: Vivek Kasireddy --- drivers/gpu/drm/i915/i915_gem.c | 117 ++++++++++++++++++++++++-------- 1 file changed, 88 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e3a2c2a0e156..752fec2b4c60 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -46,6 +46,7 @@ #include "gem/i915_gem_mman.h" #include "gem/i915_gem_region.h" #include "gem/i915_gem_userptr.h" +#include "gem/i915_gem_tiling.h" #include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" @@ -876,6 +877,92 @@ static void discard_ggtt_vma(struct i915_vma *vma) spin_unlock(&obj->vma.lock); } +static bool +i915_gem_object_fits_in_aperture(struct drm_i915_gem_object *obj, + u64 alignment, u64 flags) +{ + struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_ggtt *ggtt = to_gt(i915)->ggtt; + struct drm_mm_node *hole; + u64 hole_start, hole_end, start, end; + u64 fence_size, fence_alignment; + unsigned int count = 0; + + /* + * If the required space is larger than the available + * aperture, we will not able to find a slot for the + * object and unbinding the object now will be in + * vain. Worse, doing so may cause us to ping-pong + * the object in and out of the Global GTT and + * waste a lot of cycles under the mutex. + */ + if (obj->base.size > ggtt->mappable_end) + return true; + + /* + * If NONBLOCK is set the caller is optimistically + * trying to cache the full object within the mappable + * aperture, and *must* have a fallback in place for + * situations where we cannot bind the object. We + * can be a little more lax here and use the fallback + * more often to avoid costly migrations of ourselves + * and other objects within the aperture. + */ + if (!(flags & PIN_NONBLOCK)) + return false; + + /* + * We only consider objects whose size is at-least a quarter of + * the aperture to be too big and subject them to the new + * heuristic below. + */ + if (obj->base.size < ggtt->mappable_end / 4) + return false; + + if (HAS_GMCH(i915) || DISPLAY_VER(i915) < 11 || + !i915_gem_object_is_framebuffer(obj)) + return false; + + fence_size = i915_gem_fence_size(i915, obj->base.size, + i915_gem_object_get_tiling(obj), + i915_gem_object_get_stride(obj)); + + if (i915_vm_has_cache_coloring(&ggtt->vm)) + fence_size += 2 * I915_GTT_PAGE_SIZE; + + fence_alignment = i915_gem_fence_alignment(i915, obj->base.size, + i915_gem_object_get_tiling(obj), + i915_gem_object_get_stride(obj)); + alignment = max_t(u64, alignment, fence_alignment); + + /* + * Assuming this object is a large scanout buffer, we try to find + * out if there is room to map at-least two of them. There could + * be space available to map one but to be consistent, we try to + * avoid mapping/fencing any of them. + */ + drm_mm_for_each_best_hole(hole, &ggtt->vm.mm, 0, ggtt->mappable_end, + fence_size, DRM_MM_INSERT_LOW) { + hole_start = drm_mm_hole_node_start(hole); + hole_end = hole_start + hole->hole_size; + + do { + start = round_up(hole_start, alignment); + end = min_t(u64, hole_end, ggtt->mappable_end); + + if (range_overflows(start, fence_size, end)) + break; + + if (++count >= 2) + return false; + + hole_start = start + fence_size; + } while (1); + } + + return true; +} + struct i915_vma * i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, struct i915_gem_ww_ctx *ww, @@ -891,36 +978,8 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, if (flags & PIN_MAPPABLE && (!view || view->type == I915_GGTT_VIEW_NORMAL)) { - /* - * If the required space is larger than the available - * aperture, we will not able to find a slot for the - * object and unbinding the object now will be in - * vain. Worse, doing so may cause us to ping-pong - * the object in and out of the Global GTT and - * waste a lot of cycles under the mutex. - */ - if (obj->base.size > ggtt->mappable_end) + if (i915_gem_object_fits_in_aperture(obj, alignment, flags)) return ERR_PTR(-E2BIG); - - /* - * If NONBLOCK is set the caller is optimistically - * trying to cache the full object within the mappable - * aperture, and *must* have a fallback in place for - * situations where we cannot bind the object. We - * can be a little more lax here and use the fallback - * more often to avoid costly migrations of ourselves - * and other objects within the aperture. - * - * Half-the-aperture is used as a simple heuristic. - * More interesting would to do search for a free - * block prior to making the commitment to unbind. - * That caters for the self-harm case, and with a - * little more heuristics (e.g. NOFAULT, NOEVICT) - * we could try to minimise harm to others. - */ - if (flags & PIN_NONBLOCK && - obj->base.size > ggtt->mappable_end / 2) - return ERR_PTR(-ENOSPC); } new_vma: