From patchwork Thu Feb 3 08:26:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12733900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85509C433FE for ; Thu, 3 Feb 2022 08:26:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349504AbiBCI0d (ORCPT ); Thu, 3 Feb 2022 03:26:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349574AbiBCI0a (ORCPT ); Thu, 3 Feb 2022 03:26:30 -0500 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDD3EC061753 for ; Thu, 3 Feb 2022 00:26:15 -0800 (PST) Received: by mail-lj1-x235.google.com with SMTP id t7so2749029ljc.10 for ; Thu, 03 Feb 2022 00:26:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sfwEed+GJAr0KDwg+GYGg8QDt2lqdwbQp3DHVhIOZQQ=; b=XWqsNZ+t9i/U4p0KeuaSH72S02HQnwRce+TrI4VLyzbPGmSz+xtnMCgvt7GWHlx849 jzuBkm2V9/KqHaSslcs/kXqxP6337cc6sxkNhvlG/7zfWxDCRs+P472qPS3vqwpcZjx9 Fg1MZhCtPUEYhnMSk8ECZHfxJRce3RAGlVJsjIpsJu1ESC+Ub8h3hYjEdYpXDpDAL8Gv 3uJOiQl5p+MQTcVOhHCQZKnGYThT1GtkDqkIA5ORNcaXcuPPlkMNX7OZdsY22Y5mLoSa HN6oGINDBCQVEL2S/Q0oj9l5kabL97lb0NDM+p0EgymBC2lAJBAYLZKEo4jvwe2eSEPz Zaxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sfwEed+GJAr0KDwg+GYGg8QDt2lqdwbQp3DHVhIOZQQ=; b=P9nssilzv0umhebHvYz+9ytUlUjGVPPjjy1YVYziFZFpW5dJZ9/ZGz9HcukdcVk/bZ gKJtTWEk344Te37+Ck3VKsLENwtRLhSZZ+0JhITCA7598sNxG36+/DHrnZoFdPowVPCp cXz9fz27IqhRzgtl2FrxGKDK0jtxuU5PDHXEnbyqGu2uGp0sYNlNrEFE0hyY5BQJ2TIK BExiD4ee60KmdKrdCwY6/l8Uw4zjZnZkrA5oc/pVzXL01fp2+vbD8aUm1PqT18g08tAE kJL0H/wAA87L/zC77XYgHPmrcnq2FXxl/ADhj4Pz32rAqrLdoP968IvQyUfbIp+av4Sp UeHw== X-Gm-Message-State: AOAM531AdU370/fY1z0OhpStjVdWAycd6RErhK5TQTB3i1WOyapqC1kz zeLZToCjX4hQIUtB2SWfHFVrIA== X-Google-Smtp-Source: ABdhPJxEq6wuXH5vMzJOC9olrIInIc4kHo6hkQvuv0qu+/QCoUqnbJmB98hC6S+aHtH3I/z/CUtg1A== X-Received: by 2002:a2e:988d:: with SMTP id b13mr18964703ljj.170.1643876774158; Thu, 03 Feb 2022 00:26:14 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm4083440ljh.36.2022.02.03.00.26.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 00:26:13 -0800 (PST) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 1/7] drm/msm: move struct msm_display_info to dpu driver Date: Thu, 3 Feb 2022 11:26:05 +0300 Message-Id: <20220203082611.2654810-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> References: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The msm_display_info structure is not used by the rest of msm driver, so move it into the dpu1 (dpu_encoder.h to be precise). Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 18 ++++++++++++++++++ drivers/gpu/drm/msm/msm_drv.h | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index e241914a9677..ebe3944355bb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -34,6 +34,24 @@ struct dpu_encoder_hw_resources { void dpu_encoder_get_hw_resources(struct drm_encoder *encoder, struct dpu_encoder_hw_resources *hw_res); +/** + * struct msm_display_info - defines display properties + * @intf_type: DRM_MODE_ENCODER_ type + * @capabilities: Bitmask of display flags + * @num_of_h_tiles: Number of horizontal tiles in case of split interface + * @h_tile_instance: Controller instance used per tile. Number of elements is + * based on num_of_h_tiles + * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is + * used instead of panel TE in cmd mode panels + */ +struct msm_display_info { + int intf_type; + uint32_t capabilities; + uint32_t num_of_h_tiles; + uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; + bool is_te_using_watchdog_timer; +}; + /** * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to * @encoder: encoder pointer diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index d7574e6bd4e4..16f9e25ee19e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -109,24 +109,6 @@ struct msm_display_topology { u32 num_dspp; }; -/** - * struct msm_display_info - defines display properties - * @intf_type: DRM_MODE_ENCODER_ type - * @capabilities: Bitmask of display flags - * @num_of_h_tiles: Number of horizontal tiles in case of split interface - * @h_tile_instance: Controller instance used per tile. Number of elements is - * based on num_of_h_tiles - * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is - * used instead of panel TE in cmd mode panels - */ -struct msm_display_info { - int intf_type; - uint32_t capabilities; - uint32_t num_of_h_tiles; - uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; - bool is_te_using_watchdog_timer; -}; - /* Commit/Event thread specific structure */ struct msm_drm_thread { struct drm_device *dev; From patchwork Thu Feb 3 08:26:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12733901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9C9BC433F5 for ; Thu, 3 Feb 2022 08:26:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349513AbiBCI0e (ORCPT ); Thu, 3 Feb 2022 03:26:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349577AbiBCI0a (ORCPT ); Thu, 3 Feb 2022 03:26:30 -0500 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9245FC061755 for ; Thu, 3 Feb 2022 00:26:16 -0800 (PST) Received: by mail-lj1-x232.google.com with SMTP id t9so2730297lji.12 for ; Thu, 03 Feb 2022 00:26:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+wSU34yraQ2ZRR8Er/D8D7vbjQgPnuIKReJWue9YfHY=; b=CQ0U8lKxjH+YkU6Gnm+dNpAkAshCvyFDbKS4lBSveqTyjfUKsfZLnoW7smfSFdS91I uSWTVCAJsIbLOqJKThsrJrU1Sid+FsD9sjZ4ELg/BfHBBR6OFr1PdagdhgLXGOGJEXh7 ZBjRTovS6CICayZ4TzLwUeBAiblg2zzL2PQ30/yZvgu3vZCrB8lw29G25TD+a7EIVIaz CWo5kQBG+p2NwmU8R3yQZdDHtERpcQSz5mxmYaL93Jw96cDGGOZ9HpTVJWmS8zUyN5FK oZn0b7tSak7olXckVTeLIJH8pA5tLNWlIBt7Ib4gK7dn+KUbCKRSFUVYdy9dUy3nHhSX IjPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+wSU34yraQ2ZRR8Er/D8D7vbjQgPnuIKReJWue9YfHY=; b=2iDN7jITZrKk8bJrKwZU1+FLxXSsDoUEPiQDHgrWJCNmhHhz8qRdEwDdQKeRMZuWbC sIT/2QJCnQNN7g5ivFsqXpjqhP8nwMuqLy/ifmJAL1dN+lEFis+X/5iCLxy0Sob9NMcc UDACKBrsdi2Y5si3zrOhvRNUGuFfqsQnw2OViylRwqrqu/1HqZCg0OqdLuLn4ly8Q90x 7t0OXDwyD2qDv+JivKe2UIj1wAm+C9nGllvpeWtgUQ06kaJfdEf0EkOmjOfUuzNbkQ7e B8aiIAJV1HezO7ZRUuFSLC041hvNb9yUydx8rJiHo8kptT9Tvg9KSGBCtTF4lH5i5Va+ yvCQ== X-Gm-Message-State: AOAM532nSeKV2blD6wNPb5gxSv8wstsICAbazOJPKcTcvjAkpA44MLd4 Eud8rJQCwjoPixqytmsymYDM3Q== X-Google-Smtp-Source: ABdhPJxWjc1zb0X42/026nPtgv8Dmtm0ngQ5dn+MKclju1BNzlCraV00zcnpv+wKLhZ4G501HAY8/Q== X-Received: by 2002:a2e:b8d6:: with SMTP id s22mr22758251ljp.218.1643876774942; Thu, 03 Feb 2022 00:26:14 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm4083440ljh.36.2022.02.03.00.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 00:26:14 -0800 (PST) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 2/7] drm/msm/dpu: simplify intf allocation code Date: Thu, 3 Feb 2022 11:26:06 +0300 Message-Id: <20220203082611.2654810-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> References: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess, which intf type we mean, pass INTF_DSI/INTF_DP directly. While we are at it, fix the DP audio enablement code which was comparing intf_type, DRM_MODE_ENCODER_TMDS (= 2) with DRM_MODE_CONNECTOR_DisplayPort (= 10). Which would never succeed. Fixes: d13e36d7d222 ("drm/msm/dp: add audio support for Display Port on MSM") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 28 +++++++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-- 3 files changed, 13 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1e648db439f9..e8fc029ad607 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -493,7 +493,7 @@ void dpu_encoder_helper_split_config( hw_mdptop = phys_enc->hw_mdptop; disp_info = &dpu_enc->disp_info; - if (disp_info->intf_type != DRM_MODE_ENCODER_DSI) + if (disp_info->intf_type != INTF_DSI) return; /** @@ -555,7 +555,7 @@ static struct msm_display_topology dpu_encoder_get_topology( else topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { + if (dpu_enc->disp_info.intf_type == INTF_DSI) { if (dpu_kms->catalog->dspp && (dpu_kms->catalog->dspp_count >= topology.num_lm)) topology.num_dspp = topology.num_lm; @@ -1099,7 +1099,7 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) } - if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort && + if (dpu_enc->disp_info.intf_type == INTF_DP && dpu_enc->cur_master->hw_mdptop && dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( @@ -1107,7 +1107,7 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && + if (dpu_enc->disp_info.intf_type == INTF_DSI && !WARN_ON(dpu_enc->num_phys_encs == 0)) { unsigned bpc = dpu_enc->phys_encs[0]->connector->display_info.bpc; for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { @@ -1981,7 +1981,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, { int ret = 0; int i = 0; - enum dpu_intf_type intf_type = INTF_NONE; struct dpu_enc_phys_init_params phys_params; if (!dpu_enc) { @@ -1997,15 +1996,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, phys_params.parent_ops = &dpu_encoder_parent_ops; phys_params.enc_spinlock = &dpu_enc->enc_spinlock; - switch (disp_info->intf_type) { - case DRM_MODE_ENCODER_DSI: - intf_type = INTF_DSI; - break; - case DRM_MODE_ENCODER_TMDS: - intf_type = INTF_DP; - break; - } - WARN_ON(disp_info->num_of_h_tiles < 1); DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); @@ -2037,11 +2027,11 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, i, controller_id, phys_params.split_role); phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog, - intf_type, - controller_id); + disp_info->intf_type, + controller_id); if (phys_params.intf_idx == INTF_MAX) { DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", - intf_type, controller_id); + disp_info->intf_type, controller_id); ret = -EINVAL; } @@ -2124,11 +2114,11 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, timer_setup(&dpu_enc->frame_done_timer, dpu_encoder_frame_done_timeout, 0); - if (disp_info->intf_type == DRM_MODE_ENCODER_DSI) + if (disp_info->intf_type == INTF_DSI) timer_setup(&dpu_enc->vsync_event_timer, dpu_encoder_vsync_event_handler, 0); - else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS) + else if (disp_info->intf_type == INTF_DP || disp_info->intf_type == INTF_EDP) dpu_enc->dp = priv->dp[disp_info->h_tile_instance[0]]; INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index ebe3944355bb..3891bcbbe5a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -36,7 +36,7 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *encoder, /** * struct msm_display_info - defines display properties - * @intf_type: DRM_MODE_ENCODER_ type + * @intf_type: INTF_ type * @capabilities: Bitmask of display flags * @num_of_h_tiles: Number of horizontal tiles in case of split interface * @h_tile_instance: Controller instance used per tile. Number of elements is @@ -45,7 +45,7 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *encoder, * used instead of panel TE in cmd mode panels */ struct msm_display_info { - int intf_type; + enum dpu_intf_type intf_type; uint32_t capabilities; uint32_t num_of_h_tiles; uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 47fe11a84a77..f4028be9e2e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -564,7 +564,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, priv->encoders[priv->num_encoders++] = encoder; memset(&info, 0, sizeof(info)); - info.intf_type = encoder->encoder_type; + info.intf_type = INTF_DSI; rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); if (rc) { @@ -630,7 +630,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, info.num_of_h_tiles = 1; info.h_tile_instance[0] = i; info.capabilities = MSM_DISPLAY_CAP_VID_MODE; - info.intf_type = encoder->encoder_type; + info.intf_type = INTF_DP; /* FIXME: support eDP too */ rc = dpu_encoder_setup(dev, encoder, &info); if (rc) { DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n", From patchwork Thu Feb 3 08:26:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12733902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F1EDC433EF for ; Thu, 3 Feb 2022 08:26:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349499AbiBCI0e (ORCPT ); Thu, 3 Feb 2022 03:26:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349579AbiBCI0a (ORCPT ); Thu, 3 Feb 2022 03:26:30 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 412FEC061757 for ; Thu, 3 Feb 2022 00:26:17 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id u14so4302588lfo.11 for ; Thu, 03 Feb 2022 00:26:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nyqAWn+MLtydxGLUl27Vc6FqSrdQWPLLY5cb0Wp4tL0=; b=E40myW0Dt62WsHZYp64vJbBGaUyByvUm0+AbpUUH+1FNbwrKE+JPrwmJSEAHrRNxSi v24iUSxQOSxR1cWAM8nNtgrjVcbIFxlrkPDSVAxmgALwRjRJkvLgCa+Bzsy3RgHQp4HZ aZtr+KM4OtBYZ/u2uA34l1JGVWV3C1aNQnA+zElc5wTLWvxWdjoBZhd59lPNhMrI6wrb 1IkAJtJSUC/hRXqEoGx4ZK+U2F0UdamSRNBSlXLl2vlTxf63Iwuxrf3XLusmX/XZgz8T RE9n3Q8mHAMlSOFuTQhWcSpBNF6p5/KE6nMEBE8XhUYIxBt4x9n7Vk+NRQn8p1XzZ5HE m0xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nyqAWn+MLtydxGLUl27Vc6FqSrdQWPLLY5cb0Wp4tL0=; b=uV7Eq3cG+xLqHL+raZOT8fAJkmfNo5pfP22oMmcwnpPfx0QrW4cZLlLUJE/737TklP mLfjVfl62vbCUnz9kZHMyyDnbGNMOe+mu5lSxo3KyZrKnUaylCan/m5A2eoS9+8iZ0cy xpddyUWL8KzzCvysBKA8Zbopfk6+1UsWaS83d1/d0uWSKaS/fdJAIWsCsACzSQmABwSz RRCiQvsrZ8a8HgVgKV7ATqAfmq6uBiMlBoremzu3nv1hv0SP0OqQil5WhOLk9QOzXXRC 9M6VFqPv64pqtUUMHbSiNj+V4uX2n7bt2XEuJlnIVobAOTebyImF81hajSbyJf7UJh9z 80TA== X-Gm-Message-State: AOAM533u7pGMu12r5/UCiOw8bSz+3fRyIL0AeAD99PxTZo2qWOAEZx3R IlZuUwvSwRVMVn7I2IXWSaIJpFLrDMNUMg== X-Google-Smtp-Source: ABdhPJxt9wyAADoi6sO3Q9B2fKIcxZB9Lf2naVuJGw7avxWxVk+8JXcX+EWz6eHxZO0qa/71OjJBew== X-Received: by 2002:ac2:55ad:: with SMTP id y13mr25702114lfg.38.1643876775631; Thu, 03 Feb 2022 00:26:15 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm4083440ljh.36.2022.02.03.00.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 00:26:15 -0800 (PST) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 3/7] drm/msm/dpu: remove msm_dp cached in dpu_encoder_virt Date: Thu, 3 Feb 2022 11:26:07 +0300 Message-Id: <20220203082611.2654810-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> References: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Stop caching msm_dp instance in dpu_encoder_virt since it's not used now. Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable and disable") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index e8fc029ad607..6c1a19ffae38 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -168,7 +168,6 @@ enum dpu_enc_rc_states { * @vsync_event_work: worker to handle vsync event for autorefresh * @topology: topology of the display * @idle_timeout: idle timeout duration in milliseconds - * @dp: msm_dp pointer, for DP encoders */ struct dpu_encoder_virt { struct drm_encoder base; @@ -207,8 +206,6 @@ struct dpu_encoder_virt { struct msm_display_topology topology; u32 idle_timeout; - - struct msm_dp *dp; }; #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) @@ -2118,8 +2115,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, timer_setup(&dpu_enc->vsync_event_timer, dpu_encoder_vsync_event_handler, 0); - else if (disp_info->intf_type == INTF_DP || disp_info->intf_type == INTF_EDP) - dpu_enc->dp = priv->dp[disp_info->h_tile_instance[0]]; INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, dpu_encoder_off_work); From patchwork Thu Feb 3 08:26:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12733903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41013C4332F for ; Thu, 3 Feb 2022 08:26:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349502AbiBCI0g (ORCPT ); Thu, 3 Feb 2022 03:26:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349580AbiBCI0a (ORCPT ); Thu, 3 Feb 2022 03:26:30 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E85FCC061758 for ; Thu, 3 Feb 2022 00:26:17 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id f10so4325866lfu.8 for ; Thu, 03 Feb 2022 00:26:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8jvPULXIIzR0qzqGPTTUmR7uSAA4jIsRkWAFzhKA5wM=; b=tN0CX3/x7KyOve+6YH7O2t+7rzfSwiG1JieGaG3cot3ESYYaTQPzOiBTSJcddDGrGu 6XXmb0J2mgAZP0KUWm0gmibjzp2sQtYdn56B5nzOVLlD0JawY9XHDp3+Tu1NVo7Qiwc7 g1Yt/9LvRaXH6LVUABbpiVhwWy8CVDf8hfYw7RQXmFJrzEQOX9ODxgIEIonVvZJeiZwN jbDXGHwCeyW31ec1X/fr43svDoj4/UweZP4f9ot3pWxNyMAcEnc19LPxC7l3q8h6k926 B20Zb1t4UzxgGFItkm5VtE5tDMvcAYTKHtR9KFrh8Q/Wsj8q3LyTLwXZ2hB7/YptARIK nDCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8jvPULXIIzR0qzqGPTTUmR7uSAA4jIsRkWAFzhKA5wM=; b=jZvMkzUAJ1ZiJrW+CVuvrfYYMMaiLFZciT4ltKpYXv6PrOsZcd1PDC31E9n+57wwDI AWBtnrjvGfCYU+XKioV79TTzxmeCOeaAY9d+oTmlgRL1/xJmfhaN6VJ5W8LFv1VlbT+V uqbTqNov+g2BjzYwBi2814Lx5aKF9kOGCxfQKf0r2ig5nHtroFTARcQCMBGzPrQKzktw dalKZopKVBtQKlonCRhGSDw8OLSgjKLI1T3zqIFJhMTawg0Dm0I0mRKl94+XOVaWrm79 LiAQLvI5VB0ENup2epPa/BQVzSR2Ktc5HVkE8j6dmdsIxDTU1bs0iWy6OyG/+liPod6k cm6A== X-Gm-Message-State: AOAM531+MEma4jsdklpZnAp2x4AlXFTiihyJQQxdJvwQNXmuLfm83bUO DVcfGHJC0RMVyG19c9nMImrRRQ== X-Google-Smtp-Source: ABdhPJwuwmzDXKRStTl6JDYpRGB0zgxUC0uB1/DK/DFZh/CLhIJD8ZlQjWrCzxvWGGVl3nx+hjosVA== X-Received: by 2002:a05:6512:1292:: with SMTP id u18mr25527911lfs.360.1643876776338; Thu, 03 Feb 2022 00:26:16 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm4083440ljh.36.2022.02.03.00.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 00:26:15 -0800 (PST) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 4/7] drm/msm/dpu: drop bus_scaling_client field Date: Thu, 3 Feb 2022 11:26:08 +0300 Message-Id: <20220203082611.2654810-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> References: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We do not use MSM bus client, so drop bus_scaling_client field from dpu_encoder_virt. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 6c1a19ffae38..4530549850f0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -127,7 +127,6 @@ enum dpu_enc_rc_states { * Virtual encoder registers itself with the DRM Framework as the encoder. * @base: drm_encoder base class for registration with DRM * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes - * @bus_scaling_client: Client handle to the bus scaling interface * @enabled: True if the encoder is active, protected by enc_lock * @num_phys_encs: Actual number of physical encoders contained. * @phys_encs: Container of physical encoders managed. @@ -172,7 +171,6 @@ enum dpu_enc_rc_states { struct dpu_encoder_virt { struct drm_encoder base; spinlock_t enc_spinlock; - uint32_t bus_scaling_client; bool enabled; From patchwork Thu Feb 3 08:26:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12733904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF578C433F5 for ; Thu, 3 Feb 2022 08:26:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349507AbiBCI0h (ORCPT ); Thu, 3 Feb 2022 03:26:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349512AbiBCI0a (ORCPT ); Thu, 3 Feb 2022 03:26:30 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3134C06175A for ; Thu, 3 Feb 2022 00:26:18 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id a25so2755514lji.9 for ; Thu, 03 Feb 2022 00:26:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=01vAlF56txli9i+1P79Ks55klOiBe1vcVce2eYfWMVQ=; b=Wwc/jzjgCn8dBk34LwuCEYK7m8y/9uNjBKjS95Z8q5v6Y21BZUn6KR0FhGQoG/PKXc EsIwTQLDOQcobQw2eQt95hM4x1kEht2VWMCk2YoCebgreM9CBdiR4kvKTJgI4IoVqW9G yBEKL2LXHKmqu/KxzaGllFSPDZQk6RZVWHvW88XCI0chqDTxEwOYrmfnO/HXrJHyO456 p3oN5pgq41HdxkP2ITwqqwNHvHxyzxc4kZNBUhUsAQ2NBocpZzHvhlCgAeIuKuja6qDg hkz5N0LZG9XTP7yQP53PDM0KBB/CHPKiCCbbgEJuTjxZGBYApGVo4uYqPZAOlYrGCsVo uaVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=01vAlF56txli9i+1P79Ks55klOiBe1vcVce2eYfWMVQ=; b=ZC8gM8bE9Sah1y5Ey9ZQUACVzTTFPUnaZMYG6JCwWG+s1YnwjNqyXdhHnTlrHTPBTc q3EajValqteYTZGyLq1+I7LOqEaoDAqr5nnnd+tb/CmYEuOgQPAYj4a4VvGscH3irGpY VhUieQfz956AS9n65bjKqrNNdUS0r39zzBe1J7xdPoTJD6fHmz+0zDdXA/ZHJww0wRMy 9VP1ZOqPrr7HX8iNHSNpUq09HBv17zYwMFM5mJcNX3F4q1vRQ2QMSf0Zo22aDF+0Y8x2 tXsCsjm0ynr1v9fb/eHxAeYsmDeIs/BMXtUTAlPv/LP/ZBPGZfr3jMccsYDM8N1l5GSm ggGg== X-Gm-Message-State: AOAM533eKX+XlS3lR/MDXcRimppKkTdNS30q8vDr5+FGSByP+rpkyZ3Q AWYI8/f6ySjdnQeKzM3nt/nIpA== X-Google-Smtp-Source: ABdhPJyH274nfTSpuj2FBKolFllZJM/qsDNBJ4zyPoyCUHpzwjQifqg9Nan8aMRgBd8gmAINP8vPVw== X-Received: by 2002:a2e:96c6:: with SMTP id d6mr22096258ljj.215.1643876777023; Thu, 03 Feb 2022 00:26:17 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm4083440ljh.36.2022.02.03.00.26.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 00:26:16 -0800 (PST) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 5/7] drm/msm/dpu: encoder: drop unused callbacks Date: Thu, 3 Feb 2022 11:26:09 +0300 Message-Id: <20220203082611.2654810-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> References: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Both cmd and vid backends provide no atomic_check() callbacks and useless mode_fixup() callbacks. Drop support for both of them. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 39 +++++-------------- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ---- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 10 ----- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 ------- 4 files changed, 9 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 4530549850f0..e1c43a0c0643 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -573,7 +573,6 @@ static int dpu_encoder_virt_atomic_check( struct drm_display_mode *adj_mode; struct msm_display_topology topology; struct dpu_global_state *global_state; - int i = 0; int ret = 0; if (!drm_enc || !crtc_state || !conn_state) { @@ -595,39 +594,19 @@ static int dpu_encoder_virt_atomic_check( trace_dpu_enc_atomic_check(DRMID(drm_enc)); - /* perform atomic check on the first physical encoder (master) */ - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - - if (phys->ops.atomic_check) - ret = phys->ops.atomic_check(phys, crtc_state, - conn_state); - else if (phys->ops.mode_fixup) - if (!phys->ops.mode_fixup(phys, mode, adj_mode)) - ret = -EINVAL; - - if (ret) { - DPU_ERROR_ENC(dpu_enc, - "mode unsupported, phys idx %d\n", i); - break; - } - } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); /* Reserve dynamic resources now. */ - if (!ret) { - /* - * Release and Allocate resources on every modeset - * Dont allocate when active is false. - */ - if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + /* + * Release and Allocate resources on every modeset + * Dont allocate when active is false. + */ + if (drm_atomic_crtc_needs_modeset(crtc_state)) { + dpu_rm_release(global_state, drm_enc); - if (!crtc_state->active_changed || crtc_state->active) - ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); - } + if (!crtc_state->active_changed || crtc_state->active) + ret = dpu_rm_reserve(&dpu_kms->rm, global_state, + drm_enc, crtc_state, topology); } trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index e7270eb6b84b..159deb8ed7fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -84,12 +84,10 @@ struct dpu_encoder_virt_ops { * @is_master: Whether this phys_enc is the current master * encoder. Can be switched at enable time. Based * on split_role and current mode (CMD/VID). - * @mode_fixup: DRM Call. Fixup a DRM mode. * @mode_set: DRM Call. Set a DRM mode. * This likely caches the mode, for use at enable. * @enable: DRM Call. Enable a DRM mode. * @disable: DRM Call. Disable mode. - * @atomic_check: DRM Call. Atomic check new DRM state. * @destroy: DRM Call. Destroy and release resources. * @get_hw_resources: Populate the structure with the hardware * resources that this phys_enc is using. @@ -117,17 +115,11 @@ struct dpu_encoder_phys_ops { struct dentry *debugfs_root); void (*prepare_commit)(struct dpu_encoder_phys *encoder); bool (*is_master)(struct dpu_encoder_phys *encoder); - bool (*mode_fixup)(struct dpu_encoder_phys *encoder, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode); void (*mode_set)(struct dpu_encoder_phys *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); void (*enable)(struct dpu_encoder_phys *encoder); void (*disable)(struct dpu_encoder_phys *encoder); - int (*atomic_check)(struct dpu_encoder_phys *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state); void (*destroy)(struct dpu_encoder_phys *encoder); void (*get_hw_resources)(struct dpu_encoder_phys *encoder, struct dpu_encoder_hw_resources *hw_res); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 34a6940d12c5..45fe97fb612d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -45,15 +45,6 @@ static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) return (phys_enc->split_role != ENC_ROLE_SLAVE); } -static bool dpu_encoder_phys_cmd_mode_fixup( - struct dpu_encoder_phys *phys_enc, - const struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n"); - return true; -} - static void _dpu_encoder_phys_cmd_update_intf_cfg( struct dpu_encoder_phys *phys_enc) { @@ -732,7 +723,6 @@ static void dpu_encoder_phys_cmd_init_ops( ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit; ops->is_master = dpu_encoder_phys_cmd_is_master; ops->mode_set = dpu_encoder_phys_cmd_mode_set; - ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup; ops->enable = dpu_encoder_phys_cmd_enable; ops->disable = dpu_encoder_phys_cmd_disable; ops->destroy = dpu_encoder_phys_cmd_destroy; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ddd9d89cd456..1831fe37c88c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -225,19 +225,6 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); } -static bool dpu_encoder_phys_vid_mode_fixup( - struct dpu_encoder_phys *phys_enc, - const struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - DPU_DEBUG_VIDENC(phys_enc, "\n"); - - /* - * Modifying mode has consequences when the mode comes back to us - */ - return true; -} - static void dpu_encoder_phys_vid_setup_timing_engine( struct dpu_encoder_phys *phys_enc) { @@ -676,7 +663,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_vid_is_master; ops->mode_set = dpu_encoder_phys_vid_mode_set; - ops->mode_fixup = dpu_encoder_phys_vid_mode_fixup; ops->enable = dpu_encoder_phys_vid_enable; ops->disable = dpu_encoder_phys_vid_disable; ops->destroy = dpu_encoder_phys_vid_destroy; From patchwork Thu Feb 3 08:26:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12733905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26C9BC433FE for ; Thu, 3 Feb 2022 08:26:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345346AbiBCI0i (ORCPT ); Thu, 3 Feb 2022 03:26:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349583AbiBCI0a (ORCPT ); Thu, 3 Feb 2022 03:26:30 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FEEEC061759 for ; Thu, 3 Feb 2022 00:26:19 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id b9so4360517lfq.6 for ; Thu, 03 Feb 2022 00:26:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kxx+KIsoHDhwboQa53vIY1pbo+Mq+g9OnoduNhwfSIo=; b=xYYyUP7csIEsiSPKFNcA1VEGne27p5LLKWa6gWf18Co1jtWThk7R1WLbVYLZZK6PHk o5EYCDDf5rmBDRbk+ISwmaPIWZUAZWeqlDsmXDXiFWcUBn/EeN+3pubgaTodzAyIKSEu 8PNC+ghgflkmaLBmoQrBlN+WEtf2SQ+8Fzztm1lp5xk0Z4o0fHbzc23aJ+Pb7rxs8htJ Rt5IVSDIZSCGArLGH/0me3d4xD8CNmCJHsM5FynYKv/mwrxB08Lu5f9sXm6hm/W5NvQH TncZGwnAvNd7n6jmhc0u8GdVVphoeoPY8r7RS5G5xCvhU3Emy0GrrpTx/k+6IIQKIi4I psQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kxx+KIsoHDhwboQa53vIY1pbo+Mq+g9OnoduNhwfSIo=; b=aHWWCPWRgkAF5OmzH6MNXiT25UvfDNHA7ff0dobg0exQAhCJA4/veOAZgMWv3RGkSz OR1+3rVFaNH279w9bh3vww8xTiJ712KaWSRG3VMr7OzxYlG1A9+RWAaSv2mjuC4SzQJz zmkc7QjDxYizZRb47+C9SDIRZZmtA8yNmLZZQN4wBE32Ml3ZNETXGfx4NIrsWZc09ZYh FxNbOGVDvZ5twEH9pS6uk7sOtlXbqnkBhJlcPDeauf1M7zilDR809n6o5lvsJc3C0xyA xzI++k8i3BXEZYhqAImGkMFcRXG7heOm+9eOiJ86LfCf9BLVy7cy7MseXBgMoM8AFK1r tZdw== X-Gm-Message-State: AOAM5338hkW4vb+MrVmlFHL6wmrZvPvKgnLqnOx0CEv+OtiKJQRTieRU uqGJkl4qPbfLEeF/TYTtrwwXVw== X-Google-Smtp-Source: ABdhPJxVBknx0e2O0VOPFZ5x9Z9ypx3moLc2DO8GsIt+Aspqc19qZ4hFLhqhXkSQnfDp9r/xa+p2Eg== X-Received: by 2002:a05:6512:2316:: with SMTP id o22mr22064856lfu.244.1643876777798; Thu, 03 Feb 2022 00:26:17 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm4083440ljh.36.2022.02.03.00.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 00:26:17 -0800 (PST) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 6/7] drm/msm/dpu: switch dpu_encoder to use atomic_mode_set Date: Thu, 3 Feb 2022 11:26:10 +0300 Message-Id: <20220203082611.2654810-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> References: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Make dpu_encoder use atomic_mode_set to receive connector and CRTC states as arguments rather than finding connector and CRTC by manually looping through the respective lists. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 37 +++++-------------- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++-- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 18 ++------- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 ++----- 4 files changed, 21 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index e1c43a0c0643..1462c426c14c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -930,16 +930,13 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, return 0; } -static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) +static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { struct dpu_encoder_virt *dpu_enc; struct msm_drm_private *priv; struct dpu_kms *dpu_kms; - struct list_head *connector_list; - struct drm_connector *conn = NULL, *conn_iter; - struct drm_crtc *drm_crtc; struct dpu_crtc_state *cstate; struct dpu_global_state *global_state; struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; @@ -959,7 +956,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, priv = drm_enc->dev->dev_private; dpu_kms = to_dpu_kms(priv->kms); - connector_list = &dpu_kms->dev->mode_config.connector_list; global_state = dpu_kms_get_existing_global_state(dpu_kms); if (IS_ERR_OR_NULL(global_state)) { @@ -969,22 +965,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, trace_dpu_enc_mode_set(DRMID(drm_enc)); - list_for_each_entry(conn_iter, connector_list, head) - if (conn_iter->encoder == drm_enc) - conn = conn_iter; - - if (!conn) { - DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n"); - return; - } else if (!conn->state) { - DPU_ERROR_ENC(dpu_enc, "invalid connector state\n"); - return; - } - - drm_for_each_crtc(drm_crtc, drm_enc->dev) - if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc)) - break; - /* Query resource that have been reserved in atomic check step. */ num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, @@ -1001,7 +981,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) : NULL; - cstate = to_dpu_crtc_state(drm_crtc->state); + cstate = to_dpu_crtc_state(crtc_state); for (i = 0; i < num_lm; i++) { int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); @@ -1050,9 +1030,10 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, return; } - phys->connector = conn->state->connector; - if (phys->ops.mode_set) - phys->ops.mode_set(phys, mode, adj_mode); + phys->connector = conn_state->connector; + phys->cached_mode = crtc_state->adjusted_mode; + if (phys->ops.atomic_mode_set) + phys->ops.atomic_mode_set(phys, crtc_state, conn_state); } } @@ -2057,7 +2038,7 @@ static void dpu_encoder_frame_done_timeout(struct timer_list *t) } static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { - .mode_set = dpu_encoder_virt_mode_set, + .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, .disable = dpu_encoder_virt_disable, .enable = dpu_encoder_virt_enable, .atomic_check = dpu_encoder_virt_atomic_check, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 159deb8ed7fb..6e80321b13c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -84,7 +84,7 @@ struct dpu_encoder_virt_ops { * @is_master: Whether this phys_enc is the current master * encoder. Can be switched at enable time. Based * on split_role and current mode (CMD/VID). - * @mode_set: DRM Call. Set a DRM mode. + * @atomic_mode_set: DRM Call. Set a DRM mode. * This likely caches the mode, for use at enable. * @enable: DRM Call. Enable a DRM mode. * @disable: DRM Call. Disable mode. @@ -115,9 +115,9 @@ struct dpu_encoder_phys_ops { struct dentry *debugfs_root); void (*prepare_commit)(struct dpu_encoder_phys *encoder); bool (*is_master)(struct dpu_encoder_phys *encoder); - void (*mode_set)(struct dpu_encoder_phys *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode); + void (*atomic_mode_set)(struct dpu_encoder_phys *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state); void (*enable)(struct dpu_encoder_phys *encoder); void (*disable)(struct dpu_encoder_phys *encoder); void (*destroy)(struct dpu_encoder_phys *encoder); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 45fe97fb612d..6de298d521ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -135,23 +135,13 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) phys_enc); } -static void dpu_encoder_phys_cmd_mode_set( +static void dpu_encoder_phys_cmd_atomic_mode_set( struct dpu_encoder_phys *phys_enc, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); struct dpu_encoder_irq *irq; - if (!mode || !adj_mode) { - DPU_ERROR("invalid args\n"); - return; - } - phys_enc->cached_mode = *adj_mode; - DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n"); - drm_mode_debug_printmodeline(adj_mode); - irq = &phys_enc->irq[INTR_IDX_CTL_START]; irq->irq_idx = phys_enc->hw_ctl->caps->intr_start; @@ -722,7 +712,7 @@ static void dpu_encoder_phys_cmd_init_ops( { ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit; ops->is_master = dpu_encoder_phys_cmd_is_master; - ops->mode_set = dpu_encoder_phys_cmd_mode_set; + ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; ops->enable = dpu_encoder_phys_cmd_enable; ops->disable = dpu_encoder_phys_cmd_disable; ops->destroy = dpu_encoder_phys_cmd_destroy; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 1831fe37c88c..0c07db5021eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -348,19 +348,13 @@ static bool dpu_encoder_phys_vid_needs_single_flush( return phys_enc->split_role != ENC_ROLE_SOLO; } -static void dpu_encoder_phys_vid_mode_set( +static void dpu_encoder_phys_vid_atomic_mode_set( struct dpu_encoder_phys *phys_enc, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { struct dpu_encoder_irq *irq; - if (adj_mode) { - phys_enc->cached_mode = *adj_mode; - drm_mode_debug_printmodeline(adj_mode); - DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n"); - } - irq = &phys_enc->irq[INTR_IDX_VSYNC]; irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync; @@ -662,7 +656,7 @@ static int dpu_encoder_phys_vid_get_frame_count( static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_vid_is_master; - ops->mode_set = dpu_encoder_phys_vid_mode_set; + ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; ops->enable = dpu_encoder_phys_vid_enable; ops->disable = dpu_encoder_phys_vid_disable; ops->destroy = dpu_encoder_phys_vid_destroy; From patchwork Thu Feb 3 08:26:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12733906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDA8DC433EF for ; Thu, 3 Feb 2022 08:26:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349053AbiBCI0i (ORCPT ); Thu, 3 Feb 2022 03:26:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349516AbiBCI0a (ORCPT ); Thu, 3 Feb 2022 03:26:30 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CF92C06175B for ; Thu, 3 Feb 2022 00:26:20 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id bx31so2858528ljb.0 for ; Thu, 03 Feb 2022 00:26:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HdSi3nMWEr1dk9VcTiRx+6Kl9ilPXNam2bjJyEs5WlA=; b=nMOrvXInD9QfJLdb/fan79KuA0cxJYB6CDwub/cuX1SUSIeZ+jIpwZahuXcvPktQwu Z0mAaho/2/1bci/Xm75jRn2cEky6fuaNHfAOGXZdClCX4darf6w9bHhB/naAOele0tcW b8uXzNCi0mD+iRnSKS5zN5ymyUbIohC8Og8ZVG0QTVvInuNJVBAxhJDFv/DOcHaPiYy+ a0dhNYtEaOJKBpdyIC5RBtaT2zD+IKRuWGN0QA/LujXjVPQBXDVbcrwbLsc7ySVQE3+u nLCaoELd4H56aGuHnRcR9/BUOswSiYtfdn/AVyP96qMgQsovvldxT2C1uOzjC4QSe17B y8yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HdSi3nMWEr1dk9VcTiRx+6Kl9ilPXNam2bjJyEs5WlA=; b=VVCkzs13A0SitDf1YDU+wog85VTZB4a4ioUyjSYPmJ4swreT5UXa03PC7cwDInvJNq W6p2WFFXh8qfhcyb06V721fYFbkbYOLI8ORbUhworKF5V9V9y8jlNJUmZjxDfffOhGUS g8wtDKLdlenXJrZRtNagyb1EQI7/JnneUYvRMCd9ztw5y+jcOxwjKhnKNEKpgdGpXa+V ovunSSO8LoIqPiZMG1DuJFtBxr8xzowVbAn9s5zoXql/JgTT2Hc/F9SmKPcpBjspFJgS b6hHOTbLYpJ/NvHyGCv7C/zbcHwNY/u5TQ6BQZHJvqSV0gaD58lmCOFVf7I6RR8EydST JTBw== X-Gm-Message-State: AOAM530gLgsc7iAfjBK4YXaQI90bCqQFU4ybhY4EiLyZlQjSNIXjLQg7 KfG1J4onh3qD9pqHHcuiXCJShQ== X-Google-Smtp-Source: ABdhPJzJcKaoSRnA+SCXMUX/6l5BWhp7iUNyYhdEWRGhXgy4rGgcRuKmwU0Df+HMNSoxlOiwey9EQw== X-Received: by 2002:a2e:b703:: with SMTP id j3mr22061476ljo.228.1643876778587; Thu, 03 Feb 2022 00:26:18 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id n15sm4083440ljh.36.2022.02.03.00.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 00:26:18 -0800 (PST) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 7/7] drm/msm/dpu: pull connector from dpu_encoder_phys to dpu_encoder_virt Date: Thu, 3 Feb 2022 11:26:11 +0300 Message-Id: <20220203082611.2654810-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> References: <20220203082611.2654810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All physical encoders used by virtual encoder share the same connector, so pull the connector field from dpu_encoder_phys into dpu_encoder_virt structure. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 -- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1462c426c14c..afafdaf48aea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -143,6 +143,7 @@ enum dpu_enc_rc_states { * link between encoder/crtc. However in this case we need * to track crtc in the disable() hook which is called * _after_ encoder_mask is cleared. + * @connector: If a mode is set, cached pointer to the active connector * @crtc_kickoff_cb: Callback into CRTC that will flush & start * all CTL paths * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb @@ -183,6 +184,7 @@ struct dpu_encoder_virt { bool intfs_swapped; struct drm_crtc *crtc; + struct drm_connector *connector; struct dentry *debugfs_root; struct mutex enc_lock; @@ -993,6 +995,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, cstate->num_mixers = num_lm; + dpu_enc->connector = conn_state->connector; + for (i = 0; i < dpu_enc->num_phys_encs; i++) { int num_blk; struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC]; @@ -1030,7 +1034,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, return; } - phys->connector = conn_state->connector; phys->cached_mode = crtc_state->adjusted_mode; if (phys->ops.atomic_mode_set) phys->ops.atomic_mode_set(phys, crtc_state, conn_state); @@ -1064,7 +1067,7 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) if (dpu_enc->disp_info.intf_type == INTF_DSI && !WARN_ON(dpu_enc->num_phys_encs == 0)) { - unsigned bpc = dpu_enc->phys_encs[0]->connector->display_info.bpc; + unsigned bpc = dpu_enc->connector->display_info.bpc; for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { if (!dpu_enc->hw_pp[i]) continue; @@ -1168,9 +1171,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - dpu_enc->phys_encs[i]->connector = NULL; - } + dpu_enc->connector = NULL; DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 6e80321b13c5..5093810f6663 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -174,7 +174,6 @@ struct dpu_encoder_irq { * tied to a specific panel / sub-panel. Abstract type, sub-classed by * phys_vid or phys_cmd for video mode or command mode encs respectively. * @parent: Pointer to the containing virtual encoder - * @connector: If a mode is set, cached pointer to the active connector * @ops: Operations exposed to the virtual encoder * @parent_ops: Callbacks exposed by the parent to the phys_enc * @hw_mdptop: Hardware interface to the top registers @@ -203,7 +202,6 @@ struct dpu_encoder_irq { */ struct dpu_encoder_phys { struct drm_encoder *parent; - struct drm_connector *connector; struct dpu_encoder_phys_ops ops; const struct dpu_encoder_virt_ops *parent_ops; struct dpu_hw_mdp *hw_mdptop;