From patchwork Fri Feb 4 18:33:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 12735444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2E30C433F5 for ; Fri, 4 Feb 2022 18:33:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237456AbiBDSdZ (ORCPT ); Fri, 4 Feb 2022 13:33:25 -0500 Received: from imap3.hz.codethink.co.uk ([176.9.8.87]:33904 "EHLO imap3.hz.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377518AbiBDSdY (ORCPT ); Fri, 4 Feb 2022 13:33:24 -0500 Received: from [167.98.27.226] (helo=rainbowdash) by imap3.hz.codethink.co.uk with esmtpsa (Exim 4.92 #3 (Debian)) id 1nG3OY-0001k0-I1; Fri, 04 Feb 2022 18:33:18 +0000 Received: from ben by rainbowdash with local (Exim 4.95) (envelope-from ) id 1nG3OY-001NZg-7R; Fri, 04 Feb 2022 18:33:18 +0000 From: Ben Dooks To: paul.walmsley@sifive.com, greentime.hu@sifive.com Cc: lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Ben Dooks Subject: [PATCH] PCI: fu740: RFC: force gen1 and get devices probing Date: Fri, 4 Feb 2022 18:33:16 +0000 Message-Id: <20220204183316.328937-1-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The dw pcie core does not probe devices unless this fix from u-boot is applied. The link must be changed to gen1 and then the system will see all the other pcie devices behind the unmatched board's bridge. This is a quick PoC to try and get our test farm working when a system does not have the pcie initialised by a u-boot script. I will look at a proper patch when I am back in the office --- drivers/pci/controller/dwc/pcie-fu740.c | 37 +++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c index 960e58ead5f2..44f792764e45 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -181,11 +181,48 @@ static void fu740_pcie_init_phy(struct fu740_pcie *afp) fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); } +/* u-boot forces system to gen1 otherwise nothing probes... */ +static void pcie_sifive_force_gen1(struct dw_pcie *dw, struct fu740_pcie *afp ) +{ + unsigned val; + +#if 0 + /* u-boot code */ + /* ctrl_ro_wr_enable */ + val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1); + val |= DBI_RO_WR_EN; + writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); + + /* configure link cap */ + linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); + linkcap |= PCIE_LINK_CAP_MAX_SPEED_MASK; + writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); + + /* ctrl_ro_wr_disable */ + val &= ~DBI_RO_WR_EN; + writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); +#endif + + val = readl_relaxed(dw->dbi_base + PCIE_MISC_CONTROL_1_OFF); + val |= PCIE_DBI_RO_WR_EN; + writel_relaxed(val, dw->dbi_base + PCIE_MISC_CONTROL_1_OFF); + + val = readl(dw->dbi_base + 0x70 + 0x0c); + val |= 0xf; + writel(val, dw->dbi_base + 0x70 + 0x0c); + + val = readl_relaxed(dw->dbi_base + PCIE_MISC_CONTROL_1_OFF); + val &= ~PCIE_DBI_RO_WR_EN; + writel_relaxed(val, dw->dbi_base + PCIE_MISC_CONTROL_1_OFF); +} + static int fu740_pcie_start_link(struct dw_pcie *pci) { struct device *dev = pci->dev; struct fu740_pcie *afp = dev_get_drvdata(dev); + pcie_sifive_force_gen1(pci, afp); + /* Enable LTSSM */ writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); return 0;