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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id c22sm1148888oao.43.2022.02.04.16.36.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 16:36:52 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v2 1/6] target/riscv: Define simpler privileged spec version numbering Date: Fri, 4 Feb 2022 16:36:00 -0800 Message-Id: <20220205003605.1150143-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220205003605.1150143-1-atishp@rivosinc.com> References: <20220205003605.1150143-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c29 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Atish Patra , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9d24d678e98a..e5ff4c134c86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,8 +82,11 @@ enum { RISCV_FEATURE_AIA }; -#define PRIV_VERSION_1_10_0 0x00011000 -#define PRIV_VERSION_1_11_0 0x00011100 +/* Privileged specification version */ +enum { + PRIV_VERSION_1_10_0 = 0, + PRIV_VERSION_1_11_0, +}; #define VEXT_VERSION_1_00_0 0x00010000 From patchwork Sat Feb 5 00:36:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12735888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8C41C433F5 for ; Sat, 5 Feb 2022 00:51:23 +0000 (UTC) Received: from localhost ([::1]:37478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG9IQ-000587-Hs for qemu-devel@archiver.kernel.org; Fri, 04 Feb 2022 19:51:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG94T-00021n-V9 for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:36:58 -0500 Received: from [2607:f8b0:4864:20::229] (port=33608 helo=mail-oi1-x229.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG94R-0001mI-Cr for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:36:57 -0500 Received: by mail-oi1-x229.google.com with SMTP id x193so10584695oix.0 for ; Fri, 04 Feb 2022 16:36:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EyU4+THqr3Y8pJWma7DCKWkG8X88FhKyF8Z3F935mXk=; b=UGCeGcxXtXrmlrdCUG7Sl6m2cxxhrzzxTNkW50mpaueHrLLbIPa76eYHpQRL4rwbPC WvavkOJdC4TBpBXYIgqHyOWyEo565pdhYr/u37yYts4jN2T0d8tnZWF751u/WfxQKvBX 6vs27bsYrxfrOFBqoVfwy/HGxnpj5X5r+KlwOQ7DOW6Uri37mwTx5uMdmZ515mzp+EHV T5oKU03Plwlrh0DqbnENixDdxNnaLf1DS78l9OP1X3CPGZnFZvnyMmVT5YWN77JEzkRb L+4uV+tmahT6uLRKBzxbxeJhL92UOd7k/e8EgfZai7Rb1srXFItIJ/i67nq2t7Xs4oxm fP8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EyU4+THqr3Y8pJWma7DCKWkG8X88FhKyF8Z3F935mXk=; b=IPNYsvGbMWduGIVkIjQvX6b8Pd5Au2tlG8zVN+NCIOMIlNONkG2m/ZmAY/RQrsftMo E3V9Irh0ApVPUX/CFzZ0q3Ta1Lv7vSTe127GhhykdD29H1MG3EtgH5Jctpytin6waYtZ T3MG97yIi30EZaD5csTam0hr2loat6cMS8uSmOc1vuiNk8gnTNqMRg2P6uJY4PzTFMwz iAoxhBu8PD81x02zNEc8gvtnFflkMRujflrr8nsl26jrgJ8/kSavgrX+s/cHTH4XripO artb3n2dPMChF6nokZAEQqRkkfA3pssYr1ia17w9xXMoe7JyWcH1lubEXneHCSTYd6cV LPow== X-Gm-Message-State: AOAM532j57IWEf6j0HjJTlX2VVS+kJc6884rgtDY/4AlLi3/YoyZKewa 0NEwn5al6PQXPSqQ6jK1VOD2223gTOoh2sZN X-Google-Smtp-Source: ABdhPJwTxYCnpx3iOYhsArZVHvbjddAVL0IrzlcpiUi05NgH8OqXJTtkKlT7wAgel5l418D2437YhA== X-Received: by 2002:aca:5e55:: with SMTP id s82mr2507034oib.109.1644021414207; Fri, 04 Feb 2022 16:36:54 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id c22sm1148888oao.43.2022.02.04.16.36.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 16:36:53 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v2 2/6] target/riscv: Add the privileged spec version 1.12.0 Date: Fri, 4 Feb 2022 16:36:01 -0800 Message-Id: <20220205003605.1150143-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220205003605.1150143-1-atishp@rivosinc.com> References: <20220205003605.1150143-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::229 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,6 +86,7 @@ enum { enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, + PRIV_VERSION_1_12_0, }; #define VEXT_VERSION_1_00_0 0x00010000 From patchwork Sat Feb 5 00:36:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12735900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58933C433F5 for ; Sat, 5 Feb 2022 00:57:21 +0000 (UTC) Received: from localhost ([::1]:40426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG9OB-0007Kl-Sf for qemu-devel@archiver.kernel.org; Fri, 04 Feb 2022 19:57:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG99t-0003pW-Bb for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:42:33 -0500 Received: from [2607:f8b0:4864:20::235] (port=34739 helo=mail-oi1-x235.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG99q-0002co-Uo for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:42:32 -0500 Received: by mail-oi1-x235.google.com with SMTP id i5so10519239oih.1 for ; Fri, 04 Feb 2022 16:42:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O6PObwqwUIyUdHO/OYUSJ8TGMiaYgn/szHFribdqUcc=; b=cOVnl9CT8NKpSCuBAxYkQsfoOPdaa0gm6K8SzA/J26tm0cTLr2CLAusN6Rss3v3xsf sweftwQ93s1r5ZfvSn21EPViljWI/k6v9OtMHGB9tX6zgRO9X8YG4cpPx1OZHdpnuUIy OJsZ6DPAQsjkGAzbmAGg5IGfSBulqhUTgINIXODVglOFQiGJ5VOLIhMyIcWtEvk1nmpe +Y2WLE6atQnOlkaewAJMib0OplzW4b/Nqie+Q4CDfPmMHHJ40S3ymDq+mpeTmz0/pDIy 0uX/AiIA3zKQbPICe+aiaYNYcQ46tPbTm3CreiyjC+P+6yByIJnEG5k8tGU35Qr2i8DG mzmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O6PObwqwUIyUdHO/OYUSJ8TGMiaYgn/szHFribdqUcc=; b=dpUw+O2fcrMk9hm3ma0m7qlp4wm78DspfCnnKQzQ0ErW1cpaBgpClxYfZH0b70hon9 N9vP4Tgq56dMPWYNy9ha2owQQqyrRoJTjhDkZHOCDeOQsPx0C2/8eSeNLAnZERdRg/s1 JWZnZnxULrioKMzMNzJbmLvhe2JiiQW5nSK6zVX6hQNE67RZbwfUjCrifN2Gb86ipvvE /wE9kxs2grTVDpU47ZgesfOCM9OnRD+mymJC34ktti+Z0E9ZDWhZ13Uv6noV0cSGdOba QsE+bPw+28ejVmYPG6bNSTKJ8Zd5NYeu9zFe8DJ37g8AyCusq1c8SH5f+03usTsK7r8g BxuA== X-Gm-Message-State: AOAM531YvEREf+l3nCbiYJkGRyWbI3ZLSB8QI2Iv0P0OkgILhx5Qcv/N ECk9tcodiFV1ZRzkoYVGPMV5dRazZp0N+LTf X-Google-Smtp-Source: ABdhPJwDtDvViBx68TcnEF7CDux9XUNJ+pBtMLPwoLWSQ9uUR7dcmt30RFp6NpWMb9Vh5aKqHsJKTQ== X-Received: by 2002:a05:6870:d413:: with SMTP id i19mr435049oag.54.1644021415431; Fri, 04 Feb 2022 16:36:55 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id c22sm1148888oao.43.2022.02.04.16.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 16:36:54 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v2 3/6] target/riscv: Introduce privilege version field in the CSR ops. Date: Fri, 4 Feb 2022 16:36:02 -0800 Message-Id: <20220205003605.1150143-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220205003605.1150143-1-atishp@rivosinc.com> References: <20220205003605.1150143-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::235 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60b847141db2..0741f9822cf0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -593,6 +593,8 @@ typedef struct { riscv_csr_op_fn op; riscv_csr_read128_fn read128; riscv_csr_write128_fn write128; + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ + uint32_t min_priv_ver; } riscv_csr_operations; /* CSR function table constants */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8c63caa39245..25a0df498669 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_FRM] = { "frm", fs, read_frm, write_frm }, [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, - [CSR_VL] = { "vl", vs, read_vl }, - [CSR_VTYPE] = { "vtype", vs, read_vtype }, - [CSR_VLENB] = { "vlenb", vs, read_vlenb }, + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VL] = { "vl", vs, read_vl, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VTYPE] = { "vtype", vs, read_vtype, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VLENB] = { "vlenb", vs, read_vlenb, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_instret }, [CSR_INSTRET] = { "instret", ctr, read_instret }, @@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, - [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg }, - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie }, - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, - [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL }, - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, - - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie }, - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, - - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, @@ -3154,7 +3186,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, /* Physical Memory Protection */ - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, + [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, From patchwork Sat Feb 5 00:36:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12735911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13CD6C433F5 for ; Sat, 5 Feb 2022 01:09:03 +0000 (UTC) Received: from localhost ([::1]:51952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG9ZV-0007Z2-Rt for qemu-devel@archiver.kernel.org; Fri, 04 Feb 2022 20:09:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG9Cl-0004X1-TD for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:45:31 -0500 Received: from [2607:f8b0:4864:20::c33] (port=45843 helo=mail-oo1-xc33.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG9CE-0002nK-Si for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:45:00 -0500 Received: by mail-oo1-xc33.google.com with SMTP id u25-20020a4ad0d9000000b002e8d4370689so6532380oor.12 for ; Fri, 04 Feb 2022 16:44:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O+UQgPTWo4oSI1lXL4qP4CNWV5vH/WcWtAOvp8yVUj8=; b=w17XdDKF1j0rYLuNdsuG075oPsqjU+JFepUG7YE84E2cbd4gBINzGq1SgKnrcClIzs 3HH3aUa0T2F+IHo0y5FDAuxidr0b+/V0YleKm8Ukgc/zzxgUjzpm1gyQSEkyTw9quBdk eiHBeCmt4Ww8EDzrjiwPmJa4BF6onBCIJEdv+KSA3cj0ba1Onr8h0aQxJ6F087AKvgqj VeNfdGRtxNwmgs2Dry/F454sZHam8CD5EtGkypP550Y5rBjxK3t/BKUSDHjeLi5fdqjF FnAADby3AyEBf3WXXVyL4pFldgVaWqR0wqfVyzGDhUdGSZG3IOz9jdrSgp3XAR8A5H3t WmEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O+UQgPTWo4oSI1lXL4qP4CNWV5vH/WcWtAOvp8yVUj8=; b=aCXjCLgqTezaXdhJ+yyCNSLZQq/+ULgVoHbxDZT0+CRuUEODHuVkDAsaZDVTj0lncn wbIhI2TbPe6/IFOS6w6whrGz20f1i99gidDuF58WWxegaFadp9ROJHQexzAlukU+j7rh 5E65OPcdsrnmfqj7E9Ep9GuywHm5+z2FZBpV6i/9DJh3l+ppHQQ39qHwk7BZJhFwqXsc OdQ5Qd2biOCQn10Zm7YoeALUVNMjHtsIi2jyt0w2iT7Gc6QN1XPDLkYzGkeVQ5p+cHT6 GOwWs/Z70K2YGH1aZ429EBkBGqGqyu7Q+qi0UuKkIJytudphcl1lcxS7f8NzmNRKel+G Ix/w== X-Gm-Message-State: AOAM532ag3tatNypCS7gJgCXk5Df5nH3MNIsMW3Zv40sEmGSXvFM0mIz x7WRcbxw4RXLbAi5vvAlviT0bIf1zO+0C6iv X-Google-Smtp-Source: ABdhPJxYtxPUmxf0rxfmsjQLVAFLHcgpKjtCDI0MUDmH+L5V5p3+Ct0bjIeEE8q4MvkP2Sczeo2gaA== X-Received: by 2002:a05:6870:3845:: with SMTP id z5mr1380989oal.77.1644021416679; Fri, 04 Feb 2022 16:36:56 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id c22sm1148888oao.43.2022.02.04.16.36.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 16:36:56 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v2 4/6] target/riscv: Add support for mconfigptr Date: Fri, 4 Feb 2022 16:36:03 -0800 Message-Id: <20220205003605.1150143-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220205003605.1150143-1-atishp@rivosinc.com> References: <20220205003605.1150143-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c33 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc33.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f96d26399607..89440241632a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -148,6 +148,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 /* Machine Trap Setup */ #define CSR_MSTATUS 0x300 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 25a0df498669..4366e5e95ce8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3020,6 +3020,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MARCHID] = { "marchid", any, read_zero }, [CSR_MIMPID] = { "mimpid", any, read_zero }, [CSR_MHARTID] = { "mhartid", any, read_mhartid }, + [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Machine Trap Setup */ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, From patchwork Sat Feb 5 00:36:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12735907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D06A1C433EF for ; Sat, 5 Feb 2022 01:03:00 +0000 (UTC) Received: from localhost ([::1]:46692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG9Tc-0003pa-2q for qemu-devel@archiver.kernel.org; Fri, 04 Feb 2022 20:02:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG94k-0002ET-FH for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:37:14 -0500 Received: from [2607:f8b0:4864:20::32c] (port=42648 helo=mail-ot1-x32c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG94V-0001nH-6E for qemu-devel@nongnu.org; Fri, 04 Feb 2022 19:37:14 -0500 Received: by mail-ot1-x32c.google.com with SMTP id p3-20020a0568301d4300b005a7a702f921so6288489oth.9 for ; Fri, 04 Feb 2022 16:36:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tXHbWM3JuJ6npBKT11wxJghQ5QtuufX+d8uTeUApNww=; b=ISMXLee2g7vdk6j57gDvekZqlB039HjHLcQj+5juLHqVhmn+c+Hlayeo4hFdKf3PJU +xAA44/04Tv4qKzF71q2zuWxkdDzfzm2kNOkTgJJaiD6Ap7+pttSFwHB8foNKJwJGyCb RcJMcQr9wGVxx6FvIY7EshOtL579kZGjXKXblmbm7J3+u5OCIEw5V3H10YiZyo6ICZZu jsSXaCCVCiH9GEiJlZ6dceRMTCd0WM5BUUgd0JKOWSqFehXGnzPfORo5DgNJTe1tp96r reQ0YfxziNEK2o0Ab3QWn0L+VeJ4INK5R9yAIor+CnBlnIWfoGz9KYjFj4eKpfT+eKPb Zw+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tXHbWM3JuJ6npBKT11wxJghQ5QtuufX+d8uTeUApNww=; b=3ZkmLyNeDEfKTpt5NNQxrIkUzXXxWST3xWjUzjjGc28bWSWnkNTRS8Fifytt68rO5N /9cQZ6yDNFakSBhIIObZFL/wPDE0NI4uNWkzIK5PexiRQJtwlT9utW+xrvMONZ7y1bTN ZWGEP28xpT6fHvtYSolztBwGa0ywaATj9xDwX67zgPemt8NCkd2ravuasBcsQBnCBLbr x0DGvxV6adqlJU5eHee4P3Zhz75YBt6f8IX8JUsq2AK3rpEOq7hC766QSrAUYBMtb7Uf NeMybPBdrac+bIuiLY8tdb041tj7YktVYrkdVi93BItpm39kjFVoM6HfCutTzTXODOgf B0kg== X-Gm-Message-State: AOAM533vHQGL/Hl//ji1zssHFIVxfAlhIgmUOS+/CNjDrhERWESEv6rU 3O+LblmjUviVawIShhyvrIXdwfat/ioO/r6C X-Google-Smtp-Source: ABdhPJz2X5wlhOrhuIQrl/hSZPdP9tl2YXzhy+XMJYDyZLx15enPDqmzeIe/qfi9hnzjkrjrG3Shqg== X-Received: by 2002:a9d:12d6:: with SMTP id g80mr551637otg.169.1644021417930; Fri, 04 Feb 2022 16:36:57 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id c22sm1148888oao.43.2022.02.04.16.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 16:36:57 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v2 5/6] target/riscv: Add *envcfg* CSRs support Date: Fri, 4 Feb 2022 16:36:04 -0800 Message-Id: <20220205003605.1150143-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220205003605.1150143-1-atishp@rivosinc.com> References: <20220205003605.1150143-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::32c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=atishp@rivosinc.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 +++ target/riscv/cpu_bits.h | 39 ++++++++++++++++++ target/riscv/csr.c | 87 +++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 24 ++++++++++++ 4 files changed, 156 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0741f9822cf0..675f8716b239 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -303,6 +303,12 @@ struct CPURISCVState { target_ulong spmbase; target_ulong upmmask; target_ulong upmbase; + + /* CSRs for execution enviornment configuration */ + + uint64_t menvcfg; + target_ulong senvcfg; + uint64_t henvcfg; #endif float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 89440241632a..58a0a8d69f72 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -202,6 +202,9 @@ #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +/* Supervisor Configuration CSRs */ +#define CSR_SENVCFG 0x10A + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -247,6 +250,10 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 +/* Hypervisor Configuration CSRs */ +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -290,6 +297,10 @@ #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 +/* Machine Configuration CSRs */ +#define CSR_MENVCFG 0x30A +#define CSR_MENVCFGH 0x31A + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -654,6 +665,34 @@ typedef enum RISCVException { #define PM_EXT_CLEAN 0x00000002ULL #define PM_EXT_DIRTY 0x00000003ULL +/* Execution enviornment configuration bits */ +#define MENVCFG_FIOM BIT(0) +#define MENVCFG_CBIE (3UL << 4) +#define MENVCFG_CBCFE BIT(6) +#define MENVCFG_CBZE BIT(7) +#define MENVCFG_PBMTE BIT(62) +#define MENVCFG_STCE BIT(63) + +/* For RV32 */ +#define MENVCFGH_PBMTE BIT(30) +#define MENVCFGH_STCE BIT(31) + +#define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_CBIE MENVCFG_CBIE +#define SENVCFG_CBCFE MENVCFG_CBCFE +#define SENVCFG_CBZE MENVCFG_CBZE + +#define HENVCFG_FIOM MENVCFG_FIOM +#define HENVCFG_CBIE MENVCFG_CBIE +#define HENVCFG_CBCFE MENVCFG_CBCFE +#define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PBMTE MENVCFG_PBMTE +#define HENVCFG_STCE MENVCFG_STCE + +/* For RV32 */ +#define HENVCFGH_PBMTE MENVCFGH_PBMTE +#define HENVCFGH_STCE MENVCFGH_STCE + /* Offsets for every pair of control bits per each priv level */ #define XS_OFFSET 0ULL #define U_OFFSET 2ULL diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4366e5e95ce8..88c839a5ffaa 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1366,6 +1366,81 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +/* Execution environment configuration setup */ +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->menvcfg = val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t valh = (uint64_t)val << 32; + env->menvcfg |= valh; + + return RISCV_EXCP_NONE; +} + +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->senvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->senvcfg = val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->henvcfg = val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t valh = (uint64_t)val << 32; + env->henvcfg |= valh; + + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3069,6 +3144,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, + /* Execution environment configuration */ + [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 9895930b2976..4a50a05937fa 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -220,6 +220,29 @@ static const VMStateDescription vmstate_kvmtimer = { } }; +/* TODO: henvcfg need both hyper_needed & envcfg_needed */ +static bool envcfg_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0); +} + +static const VMStateDescription vmstate_envcfg = { + .name = "cpu/envcfg", + .version_id = 1, + .minimum_version_id = 1, + .needed = envcfg_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.menvcfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINT64(env.henvcfg, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, @@ -280,6 +303,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_pointermasking, &vmstate_rv128, &vmstate_kvmtimer, + &vmstate_envcfg, NULL } }; From patchwork Sat Feb 5 00:36:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12735889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF22DC433F5 for ; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id c22sm1148888oao.43.2022.02.04.16.36.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 16:36:58 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v2 6/6] target/riscv: Enable privileged spec version 1.12 Date: Fri, 4 Feb 2022 16:36:05 -0800 Message-Id: <20220205003605.1150143-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220205003605.1150143-1-atishp@rivosinc.com> References: <20220205003605.1150143-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::335 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=atishp@rivosinc.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +++++--- target/riscv/csr.c | 5 +++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2668f9c358b2..1c72dfffdc61 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } #if defined(TARGET_RISCV64) @@ -474,7 +474,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version = PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { priv_version = PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version = PRIV_VERSION_1_10_0; @@ -489,7 +491,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (priv_version) { set_priv_version(env, priv_version); } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } if (cpu->cfg.mmu) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 88c839a5ffaa..4e381053927d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2866,6 +2866,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ int read_only = get_field(csrno, 0xC00) == 3; + int csr_min_priv = csr_ops[csrno].min_priv_ver; #if !defined(CONFIG_USER_ONLY) int effective_priv = env->priv; @@ -2898,6 +2899,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, return RISCV_EXCP_ILLEGAL_INST; } + if (env->priv_ver < csr_min_priv) { + return RISCV_EXCP_ILLEGAL_INST; + } + return csr_ops[csrno].predicate(env, csrno); }