From patchwork Tue Feb 8 10:49:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jordan Justen X-Patchwork-Id: 12738476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4C1CC433F5 for ; Tue, 8 Feb 2022 10:49:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CDDC10E69D; Tue, 8 Feb 2022 10:49:40 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6568510E65F; Tue, 8 Feb 2022 10:49:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644317377; x=1675853377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iD02jLNk8q2RN4saVzWFu2KhDsF0NYpUYW48D7qpHzw=; b=b+WI0JhvpOa5ru6osfCAmb8eT6VostsSus55Q4dtrqx7mUFjRMH9LagL fNPk7UGGHN3PGb7fYrBUyQCRWsBOILQnlbpmeNelBl7DKBuJy/mVdJgWx /fCMAu4xG4iwk9sknu0ueJU3A5s+Wo32jqhT6arVFfUXj605FfJcXMQrv o47gUISLtUMXp8VIYzilye7MDzSs6UZ0/8S2EM+b2LG9T0s3JvFWgC3n0 wFULEzpqrU6t9D96t7Z1hcenD6Z9czCU5kQbqbKWGQsX6sisrJAPjGb/M I5+sMpWX09ip5dOeG0WzMmy/QHy2OoKU/qCkFATEZYpIj/Ba1SISu6uUv w==; X-IronPort-AV: E=McAfee;i="6200,9189,10251"; a="309667890" X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="309667890" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:36 -0800 X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="484772173" Received: from fpaillet-mobl.amr.corp.intel.com (HELO localhost) ([10.209.65.117]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:35 -0800 From: Jordan Justen To: intel-gfx Subject: [PATCH v2 1/4] drm/i915/guc: Add fetch of hwconfig table Date: Tue, 8 Feb 2022 02:49:30 -0800 Message-Id: <20220208104933.867812-2-jordan.l.justen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208104933.867812-1-jordan.l.justen@intel.com> References: <20220208104933.867812-1-jordan.l.justen@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , Rodrigo Vivi , John Harrison , dri-devel , Michal Wajdeczko Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: John Harrison Implement support for fetching the hardware description table from the GuC. The call is made twice - once without a destination buffer to query the size and then a second time to fill in the buffer. Note that the table is only available on ADL-P and later platforms. Cc: Michal Wajdeczko Signed-off-by: Rodrigo Vivi Signed-off-by: John Harrison Reviewed-by: Matthew Brost --- drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 + .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 4 + drivers/gpu/drm/i915/gt/uc/intel_guc.h | 3 + .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 151 ++++++++++++++++++ .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h | 19 +++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 + 7 files changed, 185 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 6836b020a5be..ba9b6557d59d 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -192,6 +192,7 @@ i915-y += gt/uc/intel_uc.o \ gt/uc/intel_guc_rc.o \ gt/uc/intel_guc_slpc.o \ gt/uc/intel_guc_submission.o \ + gt/uc/intel_guc_hwconfig.o \ gt/uc/intel_huc.o \ gt/uc/intel_huc_debugfs.o \ gt/uc/intel_huc_fw.o diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index fe5d7d261797..4a61c819f32b 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -137,6 +137,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009, INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004, INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, + INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100, INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502, INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503, INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h index 488b6061ee89..f9e2a6aaef4a 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h @@ -8,6 +8,10 @@ enum intel_guc_response_status { INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, + INTEL_GUC_RESPONSE_NOT_SUPPORTED = 0x20, + INTEL_GUC_RESPONSE_NO_ATTRIBUTE_TABLE = 0x201, + INTEL_GUC_RESPONSE_NO_DECRYPTION_KEY = 0x202, + INTEL_GUC_RESPONSE_DECRYPTION_FAILED = 0x204, INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, }; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index f9240d4baa69..ce2ff4bb0fd5 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -13,6 +13,7 @@ #include "intel_guc_fw.h" #include "intel_guc_fwif.h" #include "intel_guc_ct.h" +#include "intel_guc_hwconfig.h" #include "intel_guc_log.h" #include "intel_guc_reg.h" #include "intel_guc_slpc_types.h" @@ -37,6 +38,8 @@ struct intel_guc { struct intel_guc_ct ct; /** @slpc: sub-structure containing SLPC related data and objects */ struct intel_guc_slpc slpc; + /** @hwconfig: hardware configuration KLV table */ + struct intel_guc_hwconfig hwconfig; /** @sched_engine: Global engine used to submit requests to GuC */ struct i915_sched_engine *sched_engine; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c new file mode 100644 index 000000000000..ce6088f112d4 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include "gt/intel_gt.h" +#include "i915_drv.h" +#include "i915_memcpy.h" +#include "intel_guc_hwconfig.h" + +static inline struct intel_guc *hwconfig_to_guc(struct intel_guc_hwconfig *hwconfig) +{ + return container_of(hwconfig, struct intel_guc, hwconfig); +} + +/* + * GuC has a blob containing hardware configuration information (HWConfig). + * This is formatted as a simple and flexible KLV (Key/Length/Value) table. + * + * For example, a minimal version could be: + * enum device_attr { + * ATTR_SOME_VALUE = 0, + * ATTR_SOME_MASK = 1, + * }; + * + * static const u32 hwconfig[] = { + * ATTR_SOME_VALUE, + * 1, // Value Length in DWords + * 8, // Value + * + * ATTR_SOME_MASK, + * 3, + * 0x00FFFFFFFF, 0xFFFFFFFF, 0xFF000000, + * }; + * + * The attribute ids are defined in a hardware spec. + */ + +static int __guc_action_get_hwconfig(struct intel_guc_hwconfig *hwconfig, + u32 ggtt_offset, u32 ggtt_size) +{ + struct intel_guc *guc = hwconfig_to_guc(hwconfig); + u32 action[] = { + INTEL_GUC_ACTION_GET_HWCONFIG, + ggtt_offset, + 0, /* upper 32 bits of address */ + ggtt_size, + }; + int ret; + + ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); + if (ret == -ENXIO) + return -ENOENT; + + if (!ggtt_size && !ret) + ret = -EINVAL; + + return ret; +} + +static int guc_hwconfig_discover_size(struct intel_guc_hwconfig *hwconfig) +{ + int ret; + + /* Sending a query with too small a table will return the size of the table */ + ret = __guc_action_get_hwconfig(hwconfig, 0, 0); + if (ret < 0) + return ret; + + hwconfig->size = ret; + return 0; +} + +static int guc_hwconfig_fill_buffer(struct intel_guc_hwconfig *hwconfig) +{ + struct intel_guc *guc = hwconfig_to_guc(hwconfig); + struct i915_vma *vma; + u32 ggtt_offset; + void *vaddr; + int ret; + + GEM_BUG_ON(!hwconfig->size); + + ret = intel_guc_allocate_and_map_vma(guc, hwconfig->size, &vma, &vaddr); + if (ret) + return ret; + + ggtt_offset = intel_guc_ggtt_offset(guc, vma); + + ret = __guc_action_get_hwconfig(hwconfig, ggtt_offset, hwconfig->size); + if (ret >= 0) + memcpy(hwconfig->ptr, vaddr, hwconfig->size); + + i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); + + return ret; +} + +static bool has_table(struct drm_i915_private *i915) +{ + if (IS_ALDERLAKE_P(i915)) + return true; + + return false; +} + +/** + * intel_guc_hwconfig_fini - Finalize the HWConfig + * + * Free up the memory allocation holding the table. + */ +void intel_guc_hwconfig_fini(struct intel_guc_hwconfig *hwconfig) +{ + kfree(hwconfig->ptr); + hwconfig->size = 0; + hwconfig->ptr = NULL; +} + +/** + * intel_guc_hwconfig_init - Initialize the HWConfig + * + * Retrieve the HWConfig table from the GuC and save it away in a local memory + * allocation. It can then be queried on demand by other users later on. + */ +int intel_guc_hwconfig_init(struct intel_guc_hwconfig *hwconfig) +{ + struct intel_guc *guc = hwconfig_to_guc(hwconfig); + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + int ret; + + if (!has_table(i915)) + return 0; + + ret = guc_hwconfig_discover_size(hwconfig); + if (ret) + return ret; + + hwconfig->ptr = kmalloc(hwconfig->size, GFP_KERNEL); + if (!hwconfig->ptr) { + hwconfig->size = 0; + return -ENOMEM; + } + + ret = guc_hwconfig_fill_buffer(hwconfig); + if (ret < 0) { + intel_guc_hwconfig_fini(hwconfig); + return ret; + } + + return 0; +} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h new file mode 100644 index 000000000000..fdd7f0d6e938 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#ifndef _INTEL_GUC_HWCONFIG_H_ +#define _INTEL_GUC_HWCONFIG_H_ + +#include + +struct intel_guc_hwconfig { + u32 size; + void *ptr; +}; + +int intel_guc_hwconfig_init(struct intel_guc_hwconfig *hwconfig); +void intel_guc_hwconfig_fini(struct intel_guc_hwconfig *hwconfig); + +#endif /* _INTEL_GUC_HWCONFIG_H_ */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 09ed29df67bc..d045ff6d4d63 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -489,6 +489,10 @@ static int __uc_init_hw(struct intel_uc *uc) if (ret) goto err_log_capture; + ret = intel_guc_hwconfig_init(&guc->hwconfig); + if (ret) + drm_err(&i915->drm, "Failed to retrieve hwconfig table: %d\n", ret); + ret = guc_enable_communication(guc); if (ret) goto err_log_capture; @@ -562,6 +566,8 @@ static void __uc_fini_hw(struct intel_uc *uc) if (intel_uc_uses_guc_submission(uc)) intel_guc_submission_disable(guc); + intel_guc_hwconfig_fini(&guc->hwconfig); + __uc_sanitize(uc); } From patchwork Tue Feb 8 10:49:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Justen X-Patchwork-Id: 12738477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5775BC433F5 for ; Tue, 8 Feb 2022 10:49:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C005510E69E; Tue, 8 Feb 2022 10:49:40 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7BC2310E48F; Tue, 8 Feb 2022 10:49:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644317377; x=1675853377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4Zu7Eblxg822KDxynxPZ7A8kRiJYw05Yj3cMvp94maQ=; b=FyDiQvS3hdThtutUUNuZxNItcbTOvoREmC0L5acsULhOAu7BOtzRGnzE dTu62a3Xhdsj+xfYVlhPlD/hvtpoNo86ZrWBtNGalQRiZ404PMYb/7l+U M3l6NV4Z4PZl+LB78pepMtozrJvoTA+y9A+D08yzYnoTrpvHuq4zuW9qi zYxZav8cmXgdoVfGzB7D0eBGcu/TRSVdiYWIPABWlwmURAq7c1a3X5dkP Ldhj0kcJXg+fXw7Y3p7pc/j23MoIJnFE/7NcV1gLO+eFfRwRMPjeobQzl g6p0c964UJ2SFPMOxRBzJ02KTS204oEW7dt/d5oRX1Bauno9vWcz9z7rj A==; X-IronPort-AV: E=McAfee;i="6200,9189,10251"; a="236329520" X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="236329520" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:37 -0800 X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="499529960" Received: from fpaillet-mobl.amr.corp.intel.com (HELO localhost) ([10.209.65.117]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:36 -0800 From: Jordan Justen To: intel-gfx Subject: [PATCH v2 2/4] drm/i915/uapi: Add query for hwconfig blob Date: Tue, 8 Feb 2022 02:49:31 -0800 Message-Id: <20220208104933.867812-3-jordan.l.justen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208104933.867812-1-jordan.l.justen@intel.com> References: <20220208104933.867812-1-jordan.l.justen@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , Tvrtko Ursulin , Kenneth Graunke , Jordan Justen , dri-devel , Slawomir Milczarek , Rodrigo Vivi , John Harrison , Michal Wajdeczko Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rodrigo Vivi The DRM_I915_QUERY_HWCONFIG_BLOB query item returns a blob of data which it receives from the GuC software. This blob provides some useful data about the hardware for drivers. Although the blob is not fully documented at this time, the basic format is an array of u32 values. The array is a simple and flexible KLV (Key/Length/Value) formatted table. For example, it could be just: enum device_attr { ATTR_SOME_VALUE = 0, ATTR_SOME_MASK = 1, }; static const u32 hwconfig[] = { ATTR_SOME_VALUE, 1, // Value Length in DWords 8, // Value ATTR_SOME_MASK, 3, 0x00FFFFFFFF, 0xFFFFFFFF, 0xFF000000, }; The attribute ids and meaning of the values will be documented in the Programmer Reference Manuals when released. Cc: Tvrtko Ursulin Cc: Kenneth Graunke Cc: Michal Wajdeczko Cc: Slawomir Milczarek Cc: Joonas Lahtinen Signed-off-by: Rodrigo Vivi Signed-off-by: John Harrison Reviewed-by: Matthew Brost Acked-by: Jordan Justen Tested-by: Jordan Justen --- drivers/gpu/drm/i915/i915_query.c | 23 +++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 2dfbc22857a3..195524e9a369 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -479,12 +479,35 @@ static int query_memregion_info(struct drm_i915_private *i915, return total_length; } +static int query_hwconfig_blob(struct drm_i915_private *i915, + struct drm_i915_query_item *query_item) +{ + struct intel_gt *gt = to_gt(i915); + struct intel_guc_hwconfig *hwconfig = >->uc.guc.hwconfig; + + if (!hwconfig->size || !hwconfig->ptr) + return -ENODEV; + + if (query_item->length == 0) + return hwconfig->size; + + if (query_item->length < hwconfig->size) + return -EINVAL; + + if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), + hwconfig->ptr, hwconfig->size)) + return -EFAULT; + + return hwconfig->size; +} + static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info, query_engine_info, query_perf_config, query_memregion_info, + query_hwconfig_blob, }; int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 914ebd9290e5..069d2fadfbd9 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2685,6 +2685,7 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_ENGINE_INFO 2 #define DRM_I915_QUERY_PERF_CONFIG 3 #define DRM_I915_QUERY_MEMORY_REGIONS 4 +#define DRM_I915_QUERY_HWCONFIG_BLOB 5 /* Must be kept compact -- no holes and well documented */ /** From patchwork Tue Feb 8 10:49:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Justen X-Patchwork-Id: 12738475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FB37C433FE for ; Tue, 8 Feb 2022 10:49:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CD0910E69C; Tue, 8 Feb 2022 10:49:40 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 16B9810E65F; Tue, 8 Feb 2022 10:49:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644317379; x=1675853379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FckM1zrypGTJoNdtrrMS/dV/Ay2roxwm2jhMhf2GAi0=; b=g8/f2w+saMuFSuBoloqOxYSSLTrqTwOBC7Hx//So5SjT/Vzn7CHCSdr+ cQfmH7SwgJzJuX12TLMmvmyfEbvOAAd7aTEYWHQhBj+Lm8Ikt1VwV22qY OmYGXTypGMNgiOn/bSUu1de2URNSgbAqOSUVn+ALXpVXSuT0TlmlrUqkJ Ciuyu9Utl85CBMvH+h3f/pzt747gwBKqyjdmxHuIPf1HEhPISWhg3t/N5 xNyPZ+/aHyJgYHaVuPdyPHfh2LlErdokukcPiAWt0PgaDiNfVMmknJU/M P0Ept/xLetuzMMwG/GZ2TiBMkdNyxr7Dci99dmarFvfOhAsOY00GEbuZf Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10251"; a="247758993" X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="247758993" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:38 -0800 X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="540547018" Received: from fpaillet-mobl.amr.corp.intel.com (HELO localhost) ([10.209.65.117]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:37 -0800 From: Jordan Justen To: intel-gfx Subject: [PATCH v2 3/4] drm/i915/uapi: Add struct drm_i915_query_hwconfig_blob_item Date: Tue, 8 Feb 2022 02:49:32 -0800 Message-Id: <20220208104933.867812-4-jordan.l.justen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208104933.867812-1-jordan.l.justen@intel.com> References: <20220208104933.867812-1-jordan.l.justen@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , dri-devel , Daniel Vetter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Also, document DRM_I915_QUERY_HWCONFIG_BLOB with this struct. Cc: Daniel Vetter Signed-off-by: Jordan Justen --- include/uapi/drm/i915_drm.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 069d2fadfbd9..280e7e2e04d8 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -3276,6 +3276,36 @@ struct drm_i915_gem_create_ext_protected_content { __u32 flags; }; +/** + * DOC: GuC HWCONFIG blob uAPI + * + * The GuC produces a blob with information about the current device. + * i915 reads this blob from GuC and makes it available via this uAPI. + * + * The returned blob is an sequence of items of variable length + * described by struct drm_i915_query_hwconfig_blob_item. The + * drm_i915_query_hwconfig_blob_item length field gives the length of + * the drm_i915_query_hwconfig_blob_item data[] array for the item and + * thereby determines the length of that item. + * + * The overall blob returned by DRM_I915_QUERY_HWCONFIG_BLOB will end + * at the same location as the end of the final + * drm_i915_query_hwconfig_blob_item. In other words, walking through + * the individual items is guaranteed to eventually arrive at the + * exact end of the entire blob. + * + * The meaning of the key field and the data values are documented in + * the Programmer's Reference Manual. + */ +struct drm_i915_query_hwconfig_blob_item { + /** @key: Enum which defines how to interpret @data values. */ + __u32 key; + /** @length: Length of the @data array. */ + __u32 length; + /** @key: Array of values with meaning defined by @key */ + __u32 data[]; +}; + /* ID of the protected content session managed by i915 when PXP is active */ #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf From patchwork Tue Feb 8 10:49:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Justen X-Patchwork-Id: 12738478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83D2BC433F5 for ; Tue, 8 Feb 2022 10:49:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A003E10E738; Tue, 8 Feb 2022 10:49:50 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5204610E6B8; Tue, 8 Feb 2022 10:49:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644317381; x=1675853381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TSGUJguinxNypQynb8SI7RiU6gpxYvWLy1ybvcBgvu8=; b=V3fMqbTcrpN++DtLIS9WRKg3dFT99w+xqs1Y3ZvrOdrgOz0xWIDAgLcc /f9AYaQfcthLQNJWguskUpks4NUT/0BzE27GFa+BLnUA8kaRuxPt7AM3I x2W2wabW0tnGWoXwAacp0CjwWkAORNuU64Lm+Rfl5hw8PO2Um8uNlcsZn cohvx0nbXIGXNX7KEyEVMvK0OS8E/zddwFJ0JOOHC9kIxEXOnMogo+SKr gSW/27Vt3mTTiINukcCt4fnk6VojflT6Hz6kd2kRlFLllsyRJU8kD0a13 eOHF0izJmZ1vgQ/KybG6omuHbcQAM+Cg0JMrsXz6s5J1Cbx+Sjyojn8wb A==; X-IronPort-AV: E=McAfee;i="6200,9189,10251"; a="309667903" X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="309667903" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:39 -0800 X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="770949457" Received: from fpaillet-mobl.amr.corp.intel.com (HELO localhost) ([10.209.65.117]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 02:49:38 -0800 From: Jordan Justen To: intel-gfx Subject: [PATCH v2 4/4] drm/i915/guc: Verify hwconfig blob matches supported format Date: Tue, 8 Feb 2022 02:49:33 -0800 Message-Id: <20220208104933.867812-5-jordan.l.justen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208104933.867812-1-jordan.l.justen@intel.com> References: <20220208104933.867812-1-jordan.l.justen@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , dri-devel Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" i915_drm.h now defines the format of the returned DRM_I915_QUERY_HWCONFIG_BLOB query item. Since i915 receives this from the black box GuC software, it should verify that the data matches that format before sending it to user-space. The verification makes a single simple pass through the blob contents, so this verification step should not add a significant amount of init time to i915. Signed-off-by: Jordan Justen --- .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c index ce6088f112d4..6208246d4209 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c @@ -71,6 +71,29 @@ static int guc_hwconfig_discover_size(struct intel_guc_hwconfig *hwconfig) return 0; } +static int verify_hwconfig_blob(const struct intel_guc_hwconfig *hwconfig) +{ + struct drm_i915_query_hwconfig_blob_item *pos; + u32 remaining; + + if (hwconfig->size % 4 != 0 || hwconfig->ptr == NULL) + return -EINVAL; + + pos = hwconfig->ptr; + remaining = (hwconfig->size / 4); + while (remaining > 0) { + if (remaining < 2) + return -EINVAL; + if (pos->length > remaining - 2) + return -EINVAL; + remaining -= 2 + pos->length; + pos = (void *)&pos->data[pos->length]; + } + + DRM_INFO("hwconfig blob format appears valid\n"); + return 0; +} + static int guc_hwconfig_fill_buffer(struct intel_guc_hwconfig *hwconfig) { struct intel_guc *guc = hwconfig_to_guc(hwconfig); @@ -91,6 +114,12 @@ static int guc_hwconfig_fill_buffer(struct intel_guc_hwconfig *hwconfig) if (ret >= 0) memcpy(hwconfig->ptr, vaddr, hwconfig->size); + if (verify_hwconfig_blob(hwconfig)) { + DRM_ERROR("Ignoring invalid hwconfig blob received from " + "GuC!\n"); + return -EINVAL; + } + i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); return ret;