From patchwork Tue Feb 8 15:22:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F404FC433F5 for ; Tue, 8 Feb 2022 17:33:57 +0000 (UTC) Received: from localhost ([::1]:42516 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHUNH-0000qN-Mc for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 12:33:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSKb-0007tL-AL for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:01 -0500 Received: from [2607:f8b0:4864:20::42f] (port=38676 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSKZ-0000GI-NQ for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:00 -0500 Received: by mail-pf1-x42f.google.com with SMTP id e28so19424141pfj.5 for ; Tue, 08 Feb 2022 07:22:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qmrpYy0HXOTyQgHJzOuN7VqtGNgJBH5lxPAjxJsNimQ=; b=EmxN3aS0guCZW0FgOAmTimdjmsb2flq6H6s5LqfPZkdZMdFOuGXMZKCrYVT23AREPY jYfZff9M1tbFlfNkmRZN7Tj9Ws8mSlgwEsABDNsjLXb+34bgUc3K3QnPlwIC0/l1Q0Si L0fwWCb4ioZlZUPotJVH270alRsIU45zGOZb4qxBMG4L9WbYk3H0rNHS7xIjPzdtfDUI R4kmFgQ89Pn1CcFZ0XauvawoVNhzY6OraJ66ENmCDzEpqBQrZTYnjeHBGkVX9eOWyTYL Ir6TnIBhUFs3Gb5BERa42Yubv7W+WIxo9qepGy+ii/RxqKhrkTmlD7E23up1eCDPtx/E l8wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qmrpYy0HXOTyQgHJzOuN7VqtGNgJBH5lxPAjxJsNimQ=; b=OuNEaawUMjkJweoUrlROVl8y8EQbkz4QGaZi14/rP8Z67+6UMmNRIaRSyXTQKeLiVj eK7WGF9aZsnaV6yNTRTscFtTEoH1tT9oyUpV1jR6Y0Nt+tkpdsxYcHx+h1Rpi4hsSohC 2/I/pEoTn2On+lKvOV8oA8QEsIjX2LCi/FnVTgDkNGr2XdgV9u+OiobWbVMx0++JD63u jAdzbF0yXesFgllM01wcXIpwZAMJsb3sszouuNuMV6qFnh4FBvRW+LG1CPQz4RZKmUHo gKENUECAu4PZWpIXCNpK5M1iMju0rBxllKrvgBcdrTdsoj7VeDmk0jPdlzHGJzG7/7A+ m7Hg== X-Gm-Message-State: AOAM530HM5RS1ldslUz7hNRCtXOtkCVvVzBz1vTnqJeq2zZDNTtjV6pd RM4/H7ueUyZN+aQf8VLuaH+1iSxzqsU= X-Google-Smtp-Source: ABdhPJyr6bIKCL3cVQkxzQijNw+reA21uBYiCkEXNO9FZHDMkOTgnnoH2Op+PI8unHUx3XM65eWD2g== X-Received: by 2002:a63:b25a:: with SMTP id t26mr3883640pgo.144.1644333778144; Tue, 08 Feb 2022 07:22:58 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id z22sm16319919pfe.42.2022.02.08.07.22.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:22:57 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 01/13] meson: Display libfdt as disabled when system emulation is disabled Date: Tue, 8 Feb 2022 16:22:31 +0100 Message-Id: <20220208152243.16452-2-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= When configuring QEMU with --disable-system, meson keeps showing libfdt as "auto". Mark it as disabled instead. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Paolo Bonzini --- meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 571af34b7d..3c274386bb 100644 --- a/meson.build +++ b/meson.build @@ -2271,8 +2271,8 @@ if get_option('cfi') and slirp_opt == 'system' endif fdt = not_found -fdt_opt = get_option('fdt') if have_system + fdt_opt = get_option('fdt') if fdt_opt in ['enabled', 'auto', 'system'] have_internal = fs.exists(meson.current_source_dir() / 'dtc/libfdt/Makefile.libfdt') fdt = cc.find_library('fdt', kwargs: static_kwargs, @@ -2315,6 +2315,8 @@ if have_system fdt = declare_dependency(link_with: libfdt, include_directories: fdt_inc) endif +else + fdt_opt = 'disabled' endif if not fdt.found() and fdt_required.length() > 0 error('fdt not available but required by targets ' + ', '.join(fdt_required)) From patchwork Tue Feb 8 15:22:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12738983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2366BC433F5 for ; Tue, 8 Feb 2022 16:18:08 +0000 (UTC) Received: from localhost ([::1]:56972 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHTBu-0001H2-Uz for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 11:18:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42864) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSKj-000874-2h for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:09 -0500 Received: from [2607:f8b0:4864:20::434] (port=44964 helo=mail-pf1-x434.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSKh-0000Ie-Kc for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:08 -0500 Received: by mail-pf1-x434.google.com with SMTP id n32so19401146pfv.11 for ; Tue, 08 Feb 2022 07:23:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9EXID/rfj16zUB/LB4uRhHEEJYpJqPDVp6AaGWqd0oM=; b=EayZ/toVohhnYBxSg9ibDCVg1YUvsXmlAfeOLSzpC14y5RBeej55KUIubBirFJif7Q 7rLrqu8O3foGs+YiGAG18miyn0kjOV9A4PrQXdoyE9/gB1GGXGWMX2/3MyVHyS+JLbLb yx3f4fTSGHn83jp02NSh8DT+DzMz+A51wdOecD0A1xmzxfbUi25+lJhO/ubK0yW/nQkx iiMB7LchR2sZM+RpecC5mTzMu06L2/yg6g6I+V7Bg3x1QqfJzCRlWJYsLs5g3nKUEGU3 cEG6Qo9xq5CzOUmOTcSz6Tp0m2eqgw1IML8i6gC/lOSTnTkFVwGPQeGF+0V5hD+FI00G Ke0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9EXID/rfj16zUB/LB4uRhHEEJYpJqPDVp6AaGWqd0oM=; b=rpGHLdsmeWXnQ7vvTAaeRvgbcn5/94rlCW1+iyKYvt2JOfGn2avthT7qN4RHQHtWxC x5yk+Ukoo7XK250IXniHzx1E52uAV68iTgUXRGXp9ug0vI1OykencnZbT2zSfuEAcPyS QbeNTQgl6YQQSBQz0mAaU08sYSKGAkbc/siFEaUjsnOMNORlkmo7CZBIB5zQHN/h1EeH zuXBham1P5CLzSvFGgp/KV5pFTYnedfOlLSoIkfr02GbnglU8+6tzZMc0zwqldbWMbmf l7f9lWZ6DzAgRUufPkg9LKLaVLHOfa6SdAPI0nOAAZm79Cqnov5bSyL7hUen2ARztWUW Oa7g== X-Gm-Message-State: AOAM5305w6k86l+Izu5EDIReyI7l3VmAOo3nzBK86+Z/mJGZPUiqEhWr GGrUrgfVd1eFbvLY49gvx6pNuqh/qdA= X-Google-Smtp-Source: ABdhPJwrODLlJYP3MnfPqLVYLrpw3DG6gozWq4bYBUJY5ZtmyTEvvVl+eOWG0yqBVddfYJ2XesgHEg== X-Received: by 2002:a62:848c:: with SMTP id k134mr2052132pfd.86.1644333785929; Tue, 08 Feb 2022 07:23:05 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id a22sm10122524pfv.185.2022.02.08.07.23.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:23:05 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 02/13] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition Date: Tue, 8 Feb 2022 16:22:32 +0100 Message-Id: <20220208152243.16452-3-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::434 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu_ldst.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a878fd0105..5c999966de 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -64,6 +64,7 @@ #include "exec/memopidx.h" #include "qemu/int128.h" +#include "cpu.h" #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address From patchwork Tue Feb 8 15:22:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42E41C433EF for ; Tue, 8 Feb 2022 17:59:23 +0000 (UTC) Received: from localhost ([::1]:55068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHUlt-0005Yz-SI for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 12:59:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSKr-0008UF-8U for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:17 -0500 Received: from [2607:f8b0:4864:20::42a] (port=43537 helo=mail-pf1-x42a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSKp-0000KJ-Q1 for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:16 -0500 Received: by mail-pf1-x42a.google.com with SMTP id d187so19401177pfa.10 for ; Tue, 08 Feb 2022 07:23:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qQziwPFjJgRf1SMHEEYubQGyoFdOJoEaOKsr6/z4KWY=; b=gFZsnxGjj6rgke7eAHiGDB3OQ1RMIAJvwBuiJy1huFHixdKIWI3NDq0TsyY7wwZpmc SKHlcgYAZmPQb3XGqhuQB+YCiIdMas976mlx0DB+xwfQMjGQUxf30lkEwublxHfZBvv0 uK47uUKTrNj/bfGjOtEceFt7PtR0JX/F9xCT5u9sAhsWYk6f5zEfep6COfkARn+4W2oL mp0jvDAX6Z3ZfmHKEh1ADGmVla2+4YJVX1w+88VF9GlSYGxRvrzfAVUWivwmVqzkZHNR zN1v3cKsA87j5mb0G8hVHiscngR2MUkDlJ86+Exwbu8L2rP9Y6EYjQkZ7HMSujdf38bJ KXBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qQziwPFjJgRf1SMHEEYubQGyoFdOJoEaOKsr6/z4KWY=; b=4Yt/sPL586tTDJv3eXw4AurZ0nScDy+Lp/Erq8EkK6/HBLi8zfFB6nntjMFGHqMJ5D F9/E7Y3hezWTzMPoi8geeSBoZzCrdU8CVDUjnRL7+VdaNRFUdhUTwG32ud0DtVh6w2GP sXy4tzhHYlxB6s0pA/spestnl9RN+H8TOEmvSn8j3urbh9qZFzLCYSDygO3tMB7zxp/o i1gzU55Ei0p08DQ3LyCftbL+IP1mlkXVHeLP5rhvZGApNgT7QoA/9UsMJukmEcwaUqr2 tEY7W6gwIErqjif34nh5aDlAhhJFsO3WIDArwH4429A6qCIq/ugyPKrsWSpftNAY9p4l yokg== X-Gm-Message-State: AOAM531Gah+MmRoHNw1p9ioFv0auub2fJF6f8ID+8Nv/daB7Qj4li8Nf QaYEfNRUVyzBD0TwalStLtipml7TRhg= X-Google-Smtp-Source: ABdhPJz1PrUb4Ek7aiMsrNxkpjZIPUFK1i8axmy+3sXzxzGbdHyZ/USUFNUSwmuq65RBU8PzK7KNlw== X-Received: by 2002:a65:57cf:: with SMTP id q15mr3832802pgr.307.1644333794120; Tue, 08 Feb 2022 07:23:14 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id h6sm17563900pfk.110.2022.02.08.07.23.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:23:13 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 03/13] accel: Elide kvm_update_guest_debug by checking kvm_supports_guest_debug Date: Tue, 8 Feb 2022 16:22:33 +0100 Message-Id: <20220208152243.16452-4-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé --- accel/stubs/kvm-stub.c | 5 ----- cpu.c | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 7e0fb884b9..924ffbde85 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -46,11 +46,6 @@ int kvm_has_many_ioeventfds(void) return 0; } -int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) -{ - return -ENOSYS; -} - int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, target_ulong len, int type) { diff --git a/cpu.c b/cpu.c index 97d42b6b2a..834e2b4cdb 100644 --- a/cpu.c +++ b/cpu.c @@ -350,7 +350,7 @@ void cpu_single_step(CPUState *cpu, int enabled) { if (cpu->singlestep_enabled != enabled) { cpu->singlestep_enabled = enabled; - if (kvm_enabled()) { + if (kvm_enabled() && kvm_supports_guest_debug()) { kvm_update_guest_debug(cpu, 0); } trace_breakpoint_singlestep(cpu->cpu_index, enabled); From patchwork Tue Feb 8 15:22:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12738997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94591C433EF for ; Tue, 8 Feb 2022 16:36:23 +0000 (UTC) Received: from localhost ([::1]:32994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHTTa-000714-PE for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 11:36:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLM-0000x5-88 for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:48 -0500 Received: from [2607:f8b0:4864:20::102b] (port=53961 helo=mail-pj1-x102b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSL6-0000Ky-UT for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:47 -0500 Received: by mail-pj1-x102b.google.com with SMTP id qe15so7122621pjb.3 for ; Tue, 08 Feb 2022 07:23:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mdQ+eAovLxYRPvUl2EjaoonJuaKHKGu/H15gTuYJ1gQ=; b=lWc5eMnX+dY8dVUKrVcFdDh42nBTDiNDaR35VB/NqKt1vD04dO5fSg6QB1abRWzkQ+ HwO+co+BymDCdyVtQgRdG7ydpXrVDGDUgeCagPagsmX50uBO5y1gnHueNAZ+8KGt09ol nt0g9IqOnVeNtKEWUvx+7nXdoM+CpR727zb6ZmTuwXb0URHZzRCX8tFyt24E+XFWD2s/ lAVFK7KWIBjoImzr8ECOOX74ddVQQHvMchdBTgaaMX0wxdB4yfWjI8+me0uw/GzXmZgZ TdDhYpEc552D1grQbtZkTrs0VPNrFGKZFZyjehQF0NG3dsGl7kbTo8OVHcqMfasq6hxE 9zlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mdQ+eAovLxYRPvUl2EjaoonJuaKHKGu/H15gTuYJ1gQ=; b=SsjcdkZq/pZ2WSVpNN4Pg12/63VAZer1K2wkhVkZ5rmqNWkHV9Gxo4gkWpbK5E3oZm jNo1jfxqbV6z9FjAtOBifZmUyQ+vVUGZq/q+n02DXg3nwbFnHrhv3jkc6DV5kzdzH4Yn mr/SB02atnuq1iXVG7XpZnxOf3FNGqnvDAgEbMC7wEk2l8IwEzhlyHyuMUW4YSJLTlOw ciDX7EJv1WPE2Y9Cz7xYiNe/9Ki35ogoKO3UESi+JTqBcfeXwjhVOQD7ZgFAqyQEjQs6 5UG0jFtytjWBOb1euF0dc/H89QpuMJB0U1vxa3to5QesNBTU5IYJvyAGZPPeIuxBbPBV dakw== X-Gm-Message-State: AOAM531VjF/BxhjCs1s8LX4G+HmHH2OhviRJT/EjuQnV/LvnG7tzr246 1oT6eCTQk45uBaygYHyrXlyAK9GsNgY= X-Google-Smtp-Source: ABdhPJzpDegwghltUe07uEbVzk146eR152FN8DWzIMRu1sPPUSo5B+EiFK/RR7hgQEM+luoE8vhU9A== X-Received: by 2002:a17:902:bf0a:: with SMTP id bi10mr4841444plb.164.1644333802080; Tue, 08 Feb 2022 07:23:22 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id i3sm2127112pgq.65.2022.02.08.07.23.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:23:21 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 04/13] target/i386/cpu: Ensure accelerators set CPU addressble physical bits Date: Tue, 8 Feb 2022 16:22:34 +0100 Message-Id: <20220208152243.16452-5-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= The only accelerator allowed to use zero as default value is TCG. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index aa9e636800..16523a78d9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6384,6 +6384,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) * In this case, the default is the value used by TCG (40). */ if (cpu->phys_bits == 0) { + assert(tcg_enabled()); cpu->phys_bits = TCG_PHYS_ADDR_BITS; } } else { From patchwork Tue Feb 8 15:22:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12738987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40B0AC433FE for ; Tue, 8 Feb 2022 16:22:21 +0000 (UTC) Received: from localhost ([::1]:37156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHTFz-000736-Ur for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 11:22:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLN-00012R-Ux for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:50 -0500 Received: from [2607:f8b0:4864:20::42e] (port=35531 helo=mail-pf1-x42e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSL7-0000LJ-0X for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:49 -0500 Received: by mail-pf1-x42e.google.com with SMTP id z35so2352095pfw.2 for ; Tue, 08 Feb 2022 07:23:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rtxe9Y93qIuCM0racMwgqtnjaGKZPQJYzdIVlLbol78=; b=I8rNZr/9zcEK+Vq/KyM8CrsHYJMYKxV2eLmey/ZoaC06+wA7Fa+skLS9ZF7rOm3kkk FR2pIbgZT1cl1DiysM2hMTs2Pu6jqDGKlpAWNFrTGyoJtGGmZls0jECOKP8dEQN4wuNL zUslzLKb6mc/vxj5DaAGsw5zaduYDPfGQFktvhXZml/vX75pndwONzoSMwLzNKkjPGld hIh2/bTiQLTv2cfoJT2o42s4TVndsp5sCVyv23UQIriFBAarHBO6KiB4YmQLik7HcDvj ttXbgJIr5L9aZfNgVoHsQOnAGm+ocNC0TWnjfD+16+RhxTXSox+2XrcDBjkP3BqJk9G3 t4uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rtxe9Y93qIuCM0racMwgqtnjaGKZPQJYzdIVlLbol78=; b=Wf67a6MWnXTcfWF8T7roKHWifJem6jVBRPhh70KalZ2ONFeRtIeitLg+1d/zWSIwXT ymJ2vM5XiqTcIW73j0hsr/hqalPSxHv7n843BvQbJhsUOSrVh9SRT/gHZr+WkFSO89DE rhx9foCHVvdMO5x4qATSJzTpSoZRHNDQtaXhEohCQ5q983CIdbog3ntkPpajg4b7Ut/e BA9KNJiaOII6MibYvnx1C6uj+xi5n9AZn3phMnQyTVHcTOEk7HCDNtDrjfSI/fpGDEep hlSgc8i6p2zWYR8tUStfvewyUueIgug8YgKluwCuO7Meuxsts7P/CZfn8HhapgXG1Kww tBOQ== X-Gm-Message-State: AOAM532RLZ5sKCCEBU4iOE0AH/DvWQQN5yyDJCc0bGfSnR2kUW3n8d+x fofhRuabvBk1u8+unBRTPI4PHjFQzo8= X-Google-Smtp-Source: ABdhPJxC6bnKdN3J4b5gFVHI70nrLu4iso9aeYErA97WnAMmEVQ39umtEibZRuepMxYyq9FfrQgujw== X-Received: by 2002:a63:e70b:: with SMTP id b11mr3868540pgi.161.1644333810059; Tue, 08 Feb 2022 07:23:30 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id h9sm16838889pfi.124.2022.02.08.07.23.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:23:29 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 05/13] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header Date: Tue, 8 Feb 2022 16:22:35 +0100 Message-Id: <20220208152243.16452-6-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= excp_helper.c requires "exec/exec-all.h" for tlb_set_page_with_attrs() and misc_helper.c for tlb_flush(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 1 + target/i386/tcg/sysemu/misc_helper.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index 5ba739fbed..5627772e7c 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" #include "tcg/helper-tcg.h" int get_pg_mode(CPUX86State *env) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 9ccaa054c4..3715c1e262 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "exec/exec-all.h" #include "tcg/helper-tcg.h" void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) From patchwork Tue Feb 8 15:22:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6895C433F5 for ; Tue, 8 Feb 2022 17:38:29 +0000 (UTC) Received: from localhost ([::1]:51416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHURg-0007b2-B5 for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 12:38:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLP-00015E-06 for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:51 -0500 Received: from [2607:f8b0:4864:20::42d] (port=42804 helo=mail-pf1-x42d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSLD-0000MJ-Ea for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:50 -0500 Received: by mail-pf1-x42d.google.com with SMTP id c10so548231pfi.9 for ; Tue, 08 Feb 2022 07:23:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0jtvvYgmoY/nnkFak831H0YOxV9O4s5jsQ7IDO3Dzr0=; b=n/Mujt1nd3MLujLMEy0TZfWmAdY+CLQkn6aurf9gvrjpN/Ufq60dxF10EzLU0CSyP+ 2FvE7t/nlcCXYlwQhasROo46M4aESsZXYIb6nTcdYCcWQhy134RbtLDleX4sqrHFdTJt ifOIQ6KwjuFID3Ahqf3rc6mMS4FD7M6KPrHTVs1FA5CF6TNUHQRTaQPiXqnlXST9IFAz +YA+jVBU+6a5uwNVC1atRAvI5R3Lc3RxRQRbCMAqRo3o5cJ8QnTZhwhT995BxSDU5siE kKeidNnEiNPSqwhomHg3qFQoZsaoSOp4Fi0zCWzGZgWnnDdlt1i7c6eOj2rfuFz2xWbd 11BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0jtvvYgmoY/nnkFak831H0YOxV9O4s5jsQ7IDO3Dzr0=; b=hsq9LBVDP5hHMOQZ7sMmUUlCaSFdaOwbvnUyTzRGWovzOjdLzPlYL1VE6K1zTVi8Ar XI3+dNYnQLdGFk7RMNNl5XZLm34QjpuRs7MfISNUnm/oDkdVIUWzrvgxZQbMzfczCkmd 5zAB7DYIuk+NzJlHfHX88LKOLemsUBkIqoIOga4kK8BCUKFmMYo0ASxecjrFWQ8X3Zr8 qdZw27/TMwuo6lDARn8FRtXTP5OCG1n2hozbf1Lh4gqiYqbJolOhmj1v46szHvMhlRdp QYuKAo9OSKEoQNvWxQ9kBx23tu6KzoUa7tfLmvgeTjphOXMar7PnQzxav98XoU4Y84NT wlKA== X-Gm-Message-State: AOAM530wK5ALfsjyRUX9bHXLs+h4u0xwcdMtgMNk/t9nCfyE8dEhL28Y GCxduDSGbSuJtLEn9pK28byQGwEUpv8= X-Google-Smtp-Source: ABdhPJwJbJMby61JErPdGiD91jVPfeup5ElShowlhoe5iDjOxzcciQ8T/OzmxholSU3xyPPqC7srYA== X-Received: by 2002:a63:e643:: with SMTP id p3mr3824631pgj.7.1644333818067; Tue, 08 Feb 2022 07:23:38 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id i8sm6609410pgf.94.2022.02.08.07.23.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:23:37 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 06/13] cpu: Add missing 'exec/exec-all.h' and ''exec/exec-all.h'' headers Date: Tue, 8 Feb 2022 16:22:36 +0100 Message-Id: <20220208152243.16452-7-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= cpu.c requires "exec/exec-all.h" to call tlb_flush() and "qemu/accel.h" to call accel_cpu_realizefn(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cpu.c b/cpu.c index 834e2b4cdb..a728f3e762 100644 --- a/cpu.c +++ b/cpu.c @@ -35,10 +35,12 @@ #include "sysemu/tcg.h" #include "sysemu/kvm.h" #include "sysemu/replay.h" +#include "exec/exec-all.h" #include "exec/translate-all.h" #include "exec/log.h" #include "hw/core/accel-cpu.h" #include "trace/trace-root.h" +#include "qemu/accel.h" uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; From patchwork Tue Feb 8 15:22:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C5B9C433F5 for ; Tue, 8 Feb 2022 18:04:04 +0000 (UTC) Received: from localhost ([::1]:34342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHUqQ-0002c3-Qg for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 13:04:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLQ-00019g-Ma for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:52 -0500 Received: from [2607:f8b0:4864:20::102c] (port=45666 helo=mail-pj1-x102c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSLL-0000Me-9J for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:23:52 -0500 Received: by mail-pj1-x102c.google.com with SMTP id g15-20020a17090a67cf00b001b7d5b6bedaso3130255pjm.4 for ; Tue, 08 Feb 2022 07:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U6WJMSm90Sje6r4lVIrM5fq/n6jsW1aCmXrufIszTA8=; b=CPjCjXu7NCrMU6xdqc7266zC2xfw1j+mxGhNdoBbAstgW0OM8C24EvVOE0OBXoMEKN k8tvxyIMvI2HhNGjDnZh35SoTGDhM9gwn87rzrgU4qo8KnjiHcB02Uy5SPdFAfucvsVJ t+DybV3ZdTZPU2jRxoF//mgFSEnVF/ba/dkzqPC5p0wwmxwCKdqAALqaFR8oIMoayhg5 jx2s0dr7rM3+am4t4xKraLrB+KdJgz9qXS5cJdd2bRu6ataU/hl3WGb0ccV2pkq4MqyY sfzGWBYd38D4aTPRVBdgFKNu0GeHjUHIedaeTqRLX4aPkPmrZyfH7u59ccbWoq1nuzNH NqqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=U6WJMSm90Sje6r4lVIrM5fq/n6jsW1aCmXrufIszTA8=; b=OuOHmXp1yR5HfklwS0rh/MoZ/rgh169XeSFMm5k6lksMpR/gvTb/LCSZCumhPoZ7Bk CIFhknxTFhV+cLOsQl5NYEkCSSTNZBdSp2gHAhnz4AwwFtcQwsJaTAWsW4mwF/IRZxsc Pc2Kj0xMT661yqMglBaUnsGDcCx3JclaCNi9kYNZ/g5KnjGl+GisicOrWax62tRFQKDG 5kSwTb06J5NUt3Nx6G3PbK52lSPcV5B21FMhw3gZFu1qVakXqUMMmOcTUjOJR+Bgdq/V 0cUZZFwzDb0apc2P1/qjJhlsecHtKL4lEcVv7f953qukoam0CLo+uIYWPEjF/yKCypR1 5k9Q== X-Gm-Message-State: AOAM532pPPV21lLVC2PCO+ypefTYpLlHyiWXhOZ6697O6Ln4ENzW0+zH dW2DbsRYkjRr4JsWUKhNkDmVfSe4+mA= X-Google-Smtp-Source: ABdhPJz1PxphHYulHUy5qXLfS/QRJr03u6bBBHLvX2YHxNJZOV8pycUFvD5cdytANmrZF2RuLDvRXA== X-Received: by 2002:a17:90b:1d0d:: with SMTP id on13mr1900896pjb.171.1644333825851; Tue, 08 Feb 2022 07:23:45 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id t1sm16905613pfj.115.2022.02.08.07.23.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:23:45 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 07/13] cpu: Move common code to cpu-common Date: Tue, 8 Feb 2022 16:22:37 +0100 Message-Id: <20220208152243.16452-8-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= cpu_abort() and cpu_breakpoint*() don't use target-specific API. Signed-off-by: Philippe Mathieu-Daudé --- cpu.c | 109 ------------------------------------------------ cpus-common.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+), 109 deletions(-) diff --git a/cpu.c b/cpu.c index a728f3e762..c4ad6cb22e 100644 --- a/cpu.c +++ b/cpu.c @@ -34,10 +34,8 @@ #endif #include "sysemu/tcg.h" #include "sysemu/kvm.h" -#include "sysemu/replay.h" #include "exec/exec-all.h" #include "exec/translate-all.h" -#include "exec/log.h" #include "hw/core/accel-cpu.h" #include "trace/trace-root.h" #include "qemu/accel.h" @@ -275,77 +273,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) } #endif -/* Add a breakpoint. */ -int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, - CPUBreakpoint **breakpoint) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - CPUBreakpoint *bp; - - if (cc->gdb_adjust_breakpoint) { - pc = cc->gdb_adjust_breakpoint(cpu, pc); - } - - bp = g_malloc(sizeof(*bp)); - - bp->pc = pc; - bp->flags = flags; - - /* keep all GDB-injected breakpoints in front */ - if (flags & BP_GDB) { - QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); - } else { - QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); - } - - if (breakpoint) { - *breakpoint = bp; - } - - trace_breakpoint_insert(cpu->cpu_index, pc, flags); - return 0; -} - -/* Remove a specific breakpoint. */ -int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - CPUBreakpoint *bp; - - if (cc->gdb_adjust_breakpoint) { - pc = cc->gdb_adjust_breakpoint(cpu, pc); - } - - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc == pc && bp->flags == flags) { - cpu_breakpoint_remove_by_ref(cpu, bp); - return 0; - } - } - return -ENOENT; -} - -/* Remove a specific breakpoint by reference. */ -void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp) -{ - QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); - - trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags); - g_free(bp); -} - -/* Remove all matching breakpoints. */ -void cpu_breakpoint_remove_all(CPUState *cpu, int mask) -{ - CPUBreakpoint *bp, *next; - - QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { - if (bp->flags & mask) { - cpu_breakpoint_remove_by_ref(cpu, bp); - } - } -} - /* enable or disable single step mode. EXCP_DEBUG is returned by the CPU loop after each instruction */ void cpu_single_step(CPUState *cpu, int enabled) @@ -359,42 +286,6 @@ void cpu_single_step(CPUState *cpu, int enabled) } } -void cpu_abort(CPUState *cpu, const char *fmt, ...) -{ - va_list ap; - va_list ap2; - - va_start(ap, fmt); - va_copy(ap2, ap); - fprintf(stderr, "qemu: fatal: "); - vfprintf(stderr, fmt, ap); - fprintf(stderr, "\n"); - cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP); - if (qemu_log_separate()) { - FILE *logfile = qemu_log_lock(); - qemu_log("qemu: fatal: "); - qemu_log_vprintf(fmt, ap2); - qemu_log("\n"); - log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); - qemu_log_flush(); - qemu_log_unlock(logfile); - qemu_log_close(); - } - va_end(ap2); - va_end(ap); - replay_finish(); -#if defined(CONFIG_USER_ONLY) - { - struct sigaction act; - sigfillset(&act.sa_mask); - act.sa_handler = SIG_DFL; - act.sa_flags = 0; - sigaction(SIGABRT, &act, NULL); - } -#endif - abort(); -} - /* physical memory access (slow version, mainly for debug) */ #if defined(CONFIG_USER_ONLY) int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, diff --git a/cpus-common.c b/cpus-common.c index 6e73d3e58d..fbd66a9704 100644 --- a/cpus-common.c +++ b/cpus-common.c @@ -20,9 +20,14 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "exec/cpu-common.h" +#include "exec/log.h" #include "hw/core/cpu.h" #include "sysemu/cpus.h" +#include "sysemu/tcg.h" +#include "sysemu/kvm.h" +#include "sysemu/replay.h" #include "qemu/lockable.h" +#include "trace/trace-root.h" static QemuMutex qemu_cpu_list_lock; static QemuCond exclusive_cond; @@ -352,3 +357,110 @@ void process_queued_cpu_work(CPUState *cpu) qemu_mutex_unlock(&cpu->work_mutex); qemu_cond_broadcast(&qemu_work_cond); } + +/* Add a breakpoint. */ +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, + CPUBreakpoint **breakpoint) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + CPUBreakpoint *bp; + + if (cc->gdb_adjust_breakpoint) { + pc = cc->gdb_adjust_breakpoint(cpu, pc); + } + + bp = g_malloc(sizeof(*bp)); + + bp->pc = pc; + bp->flags = flags; + + /* keep all GDB-injected breakpoints in front */ + if (flags & BP_GDB) { + QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); + } else { + QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); + } + + if (breakpoint) { + *breakpoint = bp; + } + + trace_breakpoint_insert(cpu->cpu_index, pc, flags); + return 0; +} + +/* Remove a specific breakpoint. */ +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + CPUBreakpoint *bp; + + if (cc->gdb_adjust_breakpoint) { + pc = cc->gdb_adjust_breakpoint(cpu, pc); + } + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc == pc && bp->flags == flags) { + cpu_breakpoint_remove_by_ref(cpu, bp); + return 0; + } + } + return -ENOENT; +} + +/* Remove a specific breakpoint by reference. */ +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp) +{ + QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); + + trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags); + g_free(bp); +} + +/* Remove all matching breakpoints. */ +void cpu_breakpoint_remove_all(CPUState *cpu, int mask) +{ + CPUBreakpoint *bp, *next; + + QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { + if (bp->flags & mask) { + cpu_breakpoint_remove_by_ref(cpu, bp); + } + } +} + +void cpu_abort(CPUState *cpu, const char *fmt, ...) +{ + va_list ap; + va_list ap2; + + va_start(ap, fmt); + va_copy(ap2, ap); + fprintf(stderr, "qemu: fatal: "); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP); + if (qemu_log_separate()) { + FILE *logfile = qemu_log_lock(); + qemu_log("qemu: fatal: "); + qemu_log_vprintf(fmt, ap2); + qemu_log("\n"); + log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); + qemu_log_flush(); + qemu_log_unlock(logfile); + qemu_log_close(); + } + va_end(ap2); + va_end(ap); + replay_finish(); +#if defined(CONFIG_USER_ONLY) + { + struct sigaction act; + sigfillset(&act.sa_mask); + act.sa_handler = SIG_DFL; + act.sa_flags = 0; + sigaction(SIGABRT, &act, NULL); + } +#endif + abort(); +} From patchwork Tue Feb 8 15:22:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06CC0C433F5 for ; Tue, 8 Feb 2022 18:11:42 +0000 (UTC) Received: from localhost ([::1]:41890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHUxp-0007dX-Nl for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 13:11:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLl-0001M7-RJ for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:15 -0500 Received: from [2607:f8b0:4864:20::636] (port=41639 helo=mail-pl1-x636.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSLk-0000Nh-60 for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:13 -0500 Received: by mail-pl1-x636.google.com with SMTP id j4so1796627plj.8 for ; Tue, 08 Feb 2022 07:23:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yflQUiX7sYcNBUpLi7Jm2+bDnmb0i5/uhV0Mw+vbU28=; b=Kqnj12vp7zdPHflnIqY4W5t6JUNkYrAB49lnGAfQ5QCao0ky8QoRwHSyb5bRUZDuaX mVLiE1aoOMexacvy3y7e0q9YmmCe+8Xa4I2v2YEy9w+AY0sl+TfZHJASsSYJLEEJgO5B lsEgcRoY6ZqRFVLr9HGQtlkrSQ5/ojRTQ+YJaUmCYCo3OipQCMQkIK28jvfYIaOkAsbn LEOfV67HyZlK/ZnTWmacx3YVIcM27CkiVRV/RCshKhDP+sASg3WvSXiJ2ceqh4pT6zcV y9zWW/vJLIcrzagZWIks7AAtwQxpGEscHq9d/qf1/trgenN1uH4sT6vcdK1PCCthueNO L9gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yflQUiX7sYcNBUpLi7Jm2+bDnmb0i5/uhV0Mw+vbU28=; b=r5U4pAOmsnosk9G9oAMjIaCxI3E88FR70BvzIDkOsAh85jF3hbsFm2kJ8tkgtiACjS 9jFmt8n/UfH/nxp+2PuHeA2/zPW6KwjYHl4ZezO1OrhbOin/DRTM0MUpYI1Mul37fBOz ZiEZF8jHCgUWWp+rtLx8yb3MW2FNN0IQap1keJwHeYOM2rY5AJL3+iGDnretP5RanwD7 I2vyaD2/IWR9fICnWSG1EtnANySrE9U/75dOdaUxT4eBPFpQn40WEnuyRjp7CduJzv7v YESk/ursgPM+R3hdQ0Q+rPOUfR4KPbziXXnXRFiplaJ0gaKSI94PEmmsl+tu/TuSOT5Z eyJQ== X-Gm-Message-State: AOAM533k/JYN+b+3zMi2uwsQoOrxxcV/+R+HVgtqODPE3nvwY8CXi8NB Ux43X854rXr39Cpuj2aT4wuzZgqyh7I= X-Google-Smtp-Source: ABdhPJwfv9cA1gC5pOeXGnj4l8wQgqtPw7n1LvkeOdOsZySFu+HeQEUBqMLZmQz5HmDlym4j0/lXRg== X-Received: by 2002:a17:902:f612:: with SMTP id n18mr4848925plg.102.1644333833570; Tue, 08 Feb 2022 07:23:53 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id l2sm16857561pfc.183.2022.02.08.07.23.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:23:53 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 08/13] target: Include missing 'cpu.h' Date: Tue, 8 Feb 2022 16:22:38 +0100 Message-Id: <20220208152243.16452-9-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::636 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= These target-specific files use the target-specific CPU state but lack to include "cpu.h"; i.e.: ../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState' void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, ^ ../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State' void mmu_flip_um(CPUNios2State *env, unsigned int um); ^ ../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'; did you mean 'CPUState'? uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); ^~~~~~~~~~ CPUState Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/mmu.h | 2 ++ target/mips/internal.h | 1 + target/nios2/mmu.h | 2 ++ target/riscv/pmp.h | 2 ++ 4 files changed, 7 insertions(+) diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index b6b4b9ad60..1068bd2d52 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -20,6 +20,8 @@ #ifndef TARGET_MICROBLAZE_MMU_H #define TARGET_MICROBLAZE_MMU_H +#include "cpu.h" + #define MMU_R_PID 0 #define MMU_R_ZPR 1 #define MMU_R_TLBX 2 diff --git a/target/mips/internal.h b/target/mips/internal.h index daddb05fd4..f705d6bfa6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -12,6 +12,7 @@ #ifdef CONFIG_TCG #include "tcg/tcg-internal.h" #endif +#include "cpu.h" /* * MMU types, the first four entries have the same layout as the diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h index 4f46fbb82e..d36b8cc86a 100644 --- a/target/nios2/mmu.h +++ b/target/nios2/mmu.h @@ -21,6 +21,8 @@ #ifndef NIOS2_MMU_H #define NIOS2_MMU_H +#include "cpu.h" + typedef struct Nios2TLBEntry { target_ulong tag; target_ulong data; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index a9a0b363a7..fcb6b7c467 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -22,6 +22,8 @@ #ifndef RISCV_PMP_H #define RISCV_PMP_H +#include "cpu.h" + typedef enum { PMP_READ = 1 << 0, PMP_WRITE = 1 << 1, From patchwork Tue Feb 8 15:22:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6B51C433EF for ; Tue, 8 Feb 2022 18:14:38 +0000 (UTC) Received: from localhost ([::1]:48448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHV0f-0003zn-Eq for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 13:14:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLn-0001MD-5c for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:15 -0500 Received: from [2607:f8b0:4864:20::42c] (port=38686 helo=mail-pf1-x42c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSLk-0000O8-FZ for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:14 -0500 Received: by mail-pf1-x42c.google.com with SMTP id e28so19429579pfj.5 for ; Tue, 08 Feb 2022 07:24:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ha1poJJsMbEmVT2TWrI2VeQn1cQITks/LrH1hi0Yo+M=; b=edHs5JyHYxayOIUJSq6aIrr8cAiscbGxtNNij27g8yjUVcWon3Vz4udruDuZjAQX/B xVC5HSXms6Z99jUHSAQ75gpX5LbnduO8f410/4Rjel6me50aquW+hnMVG2Tbkh01ulRk zcQtgjzn70apHocJX01pmzct0v6U+YsZ6ay0WzoBLplgCzYVui9y8wNsUnCCnyCpDGlp L/q8GZtZJ7xsmkQjHCPkhIp09ruZNkW1yN3mvHv7YWWvYDqDUW52n2cchSwdOfsbOPSl udadMCWo7/ozXOBbh+6uvXOLCSGwzdDEEu/EGi/odJasABdZGbeow/Ur8mJGKFC5o+j4 OORQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ha1poJJsMbEmVT2TWrI2VeQn1cQITks/LrH1hi0Yo+M=; b=LQj1291KFm1lsvjYNwsC+TPvDIR2m9+MPVFX15mRgiZLxqETtaaIza+TVVvpNGJzqx JoUemp8knqxn3rj0hKAbs24EKSWQ3nCC7aggVk1Vq+2wFouL16ZXqcVxJPRhlCH5rF+e MtENIPSlMTHFPQfrCC7SRB4sDHwfN3tSuId1W0B3EjBN7QPBtsnd/LaCjj0M7pQCa9Ki fGIM2nilDPbyJ30dH2cnHULEfdc/7R4MEspTx4sHuGTtseFfKKXoFXxkyzKvA0vs8i/N 8ihfJDsJML/Czrc/MbTWYSaoyV4GPSUyAHod34uO0zmL2xVf5iBrv6TRU3B3ywSasXXH Dd9Q== X-Gm-Message-State: AOAM533RM2+nqd30TZFP6oSgxI7XsoJ12F6/V5nNo6XdBQFLPPZRl/yA DADLoXWUdmMg9WdGk/Z4356ON91WuRg= X-Google-Smtp-Source: ABdhPJzdfe3yio6xsl38g2VT8bjV2nvFoqpbqIt7KcLq1wGLGHsel6MhxV7V3ZG4MXMvZ8zR10mLJg== X-Received: by 2002:a05:6a00:2350:: with SMTP id j16mr4887278pfj.78.1644333841523; Tue, 08 Feb 2022 07:24:01 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id il18sm3304997pjb.27.2022.02.08.07.23.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:24:01 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 09/13] target: Use forward declared type instead of structure type Date: Tue, 8 Feb 2022 16:22:39 +0100 Message-Id: <20220208152243.16452-10-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= The CPU state is forward declared. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 14 +++++++------- target/xtensa/cpu.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index f705d6bfa6..ac6e03e2f2 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -134,14 +134,14 @@ struct r4k_tlb_t { struct CPUMIPSTLBContext { uint32_t nb_tlb; uint32_t tlb_in_use; - int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, + int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type); - void (*helper_tlbwi)(struct CPUMIPSState *env); - void (*helper_tlbwr)(struct CPUMIPSState *env); - void (*helper_tlbp)(struct CPUMIPSState *env); - void (*helper_tlbr)(struct CPUMIPSState *env); - void (*helper_tlbinv)(struct CPUMIPSState *env); - void (*helper_tlbinvf)(struct CPUMIPSState *env); + void (*helper_tlbwi)(CPUMIPSState *env); + void (*helper_tlbwr)(CPUMIPSState *env); + void (*helper_tlbp)(CPUMIPSState *env); + void (*helper_tlbr)(CPUMIPSState *env); + void (*helper_tlbinv)(CPUMIPSState *env); + void (*helper_tlbinvf)(CPUMIPSState *env); union { struct { r4k_tlb_t tlb[MIPS_TLB_MAX]; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 02143f2f77..f2165b17e2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -344,7 +344,7 @@ typedef struct XtensaGdbRegmap { } XtensaGdbRegmap; typedef struct XtensaCcompareTimer { - struct CPUXtensaState *env; + CPUXtensaState *env; QEMUTimer *timer; } XtensaCcompareTimer; From patchwork Tue Feb 8 15:22:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4BD7C433F5 for ; Tue, 8 Feb 2022 16:41:48 +0000 (UTC) Received: from localhost ([::1]:41662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHTYp-0004jA-H6 for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 11:41:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLo-0001Ok-Tn for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:18 -0500 Received: from [2607:f8b0:4864:20::42d] (port=41790 helo=mail-pf1-x42d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSLl-0000Pn-2J for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:16 -0500 Received: by mail-pf1-x42d.google.com with SMTP id i30so19411573pfk.8 for ; Tue, 08 Feb 2022 07:24:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IgBOe+/71p8VD2+WTRmPCpmKMyS03V8Or4ygo2HC2EI=; b=obHpR8LqRzZbVD+YooiS08VG7tOYCQeAfRETfL5csJzEezA3BztRv5fiIHCaBOfSvj phneYEVNsvBxbLgKNim+oo1HRW8xWaqdGrAAuHuJcbb/uRS6KJrf/UvgnYFt7rj2y8T4 RDvMjSAtz29w9TMJrQxgxsX9SzCB9y/dWT3x6R9k+JH6mIQ0mjSeaj7nTHfHDC/ZV7Aj j/wrXV+NDWWmDSeYf4LZunigoWv07Iu/esJVacvSW9vqYXrxB0+3rwb5ockDXYRm2B81 iUVeZ+EmvrXCPxXDId2c/gv4YRjU5nBq0lixOFf6JzXcpgy8I4ytynP6+reAFfdJH5rQ gzRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IgBOe+/71p8VD2+WTRmPCpmKMyS03V8Or4ygo2HC2EI=; b=Mb/m1Aeqa9W/xl4VTiqWwOyTH4d8feZraYdVHhh+E95buvFse0pr4teNX1RpeZQyLE O0IoNGjTB7bhVXhRG0kH+yLMYKFo3YRzd+aeu2Dn0mhBpJDBRD+KwDrqEU6QI01ml60P nnIgX+yni9AZP8pXXbJgD0jEiEE4vP8zUh1ZAbOBXy6zUmSyFtXuIvMMosDHkpzfYrl4 fMnPUnZzr7DSGZkpd8SdxyZ2x+RGh6c/9Y22C64TTZm6K6cIDxRMJf762B8BfsYjnV7w XPr8hQEulgiTrXoPCdwVY4YcfOVUKYVHJwToXJJfaMuz4PzOPTYyNHrOzOblm2HHqkpr iCTQ== X-Gm-Message-State: AOAM531TfOgAbwcvyFz6D1z/zUmX4m+4Xff7eXYBfLaOuktDmCMw6Dna TY9FfwwmfaN36CpvGOE2mYGW/y+iAFA= X-Google-Smtp-Source: ABdhPJxidsA0G/U2vOMpjV2OEKr23PsQkcRSUxWzW4PnxRx9EKqbYXo1SDrc07xN1Ph/FW14ijZ7ng== X-Received: by 2002:a63:6d0:: with SMTP id 199mr3903969pgg.78.1644333849333; Tue, 08 Feb 2022 07:24:09 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id g8sm16394545pfc.193.2022.02.08.07.24.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:24:09 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 10/13] target: Use CPUArchState as interface to target-specific CPU state Date: Tue, 8 Feb 2022 16:22:40 +0100 Message-Id: <20220208152243.16452-11-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/poison.h | 2 -- include/hw/core/cpu.h | 2 +- include/qemu/typedefs.h | 1 + target/alpha/cpu.h | 6 ++---- target/arm/cpu.h | 2 +- target/avr/cpu.h | 6 ++---- target/cris/cpu.h | 2 +- target/hexagon/cpu.h | 5 ++--- target/hppa/cpu.h | 6 ++---- target/i386/cpu.h | 2 +- target/m68k/cpu.h | 2 +- target/microblaze/cpu.h | 4 ++-- target/mips/cpu.h | 5 ++--- target/nios2/cpu.h | 4 ++-- target/openrisc/cpu.h | 2 +- target/ppc/cpu-qom.h | 2 +- target/ppc/cpu.h | 3 +-- target/riscv/cpu.h | 4 ++-- target/rx/cpu-qom.h | 2 -- target/rx/cpu.h | 2 +- target/s390x/cpu-qom.h | 2 +- target/s390x/cpu.h | 2 +- target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 4 ++-- target/tricore/cpu.h | 5 ++--- target/xtensa/cpu.h | 6 +++--- 26 files changed, 36 insertions(+), 49 deletions(-) diff --git a/include/exec/poison.h b/include/exec/poison.h index 7ad4ad18e8..7c5c02f03f 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -51,8 +51,6 @@ #pragma GCC poison TARGET_PAGE_BITS #pragma GCC poison TARGET_PAGE_ALIGN -#pragma GCC poison CPUArchState - #pragma GCC poison CPU_INTERRUPT_HARD #pragma GCC poison CPU_INTERRUPT_EXITTB #pragma GCC poison CPU_INTERRUPT_HALT diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3f2b681281..c9d41e4ece 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -340,7 +340,7 @@ struct CPUState { AddressSpace *as; MemoryRegion *memory; - void *env_ptr; /* CPUArchState */ + CPUArchState *env_ptr; IcountDecr *icount_decr_ptr; /* Accessed in parallel; all accesses must be atomic */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index ee60eb3de4..c6f692b0dd 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -39,6 +39,7 @@ typedef struct CompatProperty CompatProperty; typedef struct CoMutex CoMutex; typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUAddressSpace CPUAddressSpace; +typedef struct CPUArchState CPUArchState; typedef struct CPUState CPUState; typedef struct DeviceListener DeviceListener; typedef struct DeviceState DeviceState; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e819211503..1c12b4394c 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -197,9 +197,7 @@ enum { #define MMU_USER_IDX 1 #define MMU_PHYS_IDX 2 -typedef struct CPUAlphaState CPUAlphaState; - -struct CPUAlphaState { +typedef struct CPUArchState { uint64_t ir[31]; float64 fir[31]; uint64_t pc; @@ -251,7 +249,7 @@ struct CPUAlphaState { uint32_t features; uint32_t amask; int implver; -}; +} CPUAlphaState; /** * AlphaCPU: diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6a4d50e82..c3bdf4551e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -232,7 +232,7 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; -typedef struct CPUARMState { +typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; diff --git a/target/avr/cpu.h b/target/avr/cpu.h index dceacf3cd7..c39e435696 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -108,9 +108,7 @@ typedef enum AVRFeature { AVR_FEATURE_RAMPZ, } AVRFeature; -typedef struct CPUAVRState CPUAVRState; - -struct CPUAVRState { +typedef struct CPUArchState { uint32_t pc_w; /* 0x003fffff up to 22 bits */ uint32_t sregC; /* 0x00000001 1 bit */ @@ -137,7 +135,7 @@ struct CPUAVRState { bool fullacc; /* CPU/MEM if true MEM only otherwise */ uint64_t features; -}; +} CPUAVRState; /** * AVRCPU: diff --git a/target/cris/cpu.h b/target/cris/cpu.h index b445b194ea..6d5f7b859b 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -105,7 +105,7 @@ typedef struct { uint32_t lo; } TLBSet; -typedef struct CPUCRISState { +typedef struct CPUArchState { uint32_t regs[16]; /* P0 - P15 are referred to as special registers in the docs. */ uint32_t pregs[16]; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 58a0d3870b..18f963859e 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -75,7 +75,7 @@ typedef struct { /* Maximum number of vector temps in a packet */ #define VECTOR_TEMPS_MAX 4 -struct CPUHexagonState { +typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; target_ulong branch_taken; @@ -129,7 +129,7 @@ struct CPUHexagonState { target_ulong vstore_pending[VSTORES_MAX]; bool vtcm_pending; VTCMStoreLog vtcm_log; -}; +} CPUHexagonState; #define HEXAGON_CPU_CLASS(klass) \ OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU) @@ -180,7 +180,6 @@ static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) #endif } -typedef struct CPUHexagonState CPUArchState; typedef HexagonCPU ArchCPU; void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 93c119532a..53e33d01e7 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -138,8 +138,6 @@ #define CR_IPSW 22 #define CR_EIRR 23 -typedef struct CPUHPPAState CPUHPPAState; - #if TARGET_REGISTER_BITS == 32 typedef uint32_t target_ureg; typedef int32_t target_sreg; @@ -168,7 +166,7 @@ typedef struct { unsigned access_id : 16; } hppa_tlb_entry; -struct CPUHPPAState { +typedef struct CPUArchState { target_ureg gr[32]; uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ @@ -207,7 +205,7 @@ struct CPUHPPAState { /* ??? We should use a more intelligent data structure. */ hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; uint32_t tlb_last; -}; +} CPUHPPAState; /** * HPPACPU: diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9911d7c871..cdafefc2d6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1429,7 +1429,7 @@ typedef struct HVFX86LazyFlags { target_ulong auxbits; } HVFX86LazyFlags; -typedef struct CPUX86State { +typedef struct CPUArchState { /* standard registers */ target_ulong regs[CPU_NB_REGS]; target_ulong eip; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index a3423729ef..3ed40004bf 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -79,7 +79,7 @@ typedef CPU_LDoubleU FPReg; -typedef struct CPUM68KState { +typedef struct CPUArchState { uint32_t dregs[8]; uint32_t aregs[8]; uint32_t pc; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e9cd0b88de..06cff32e56 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -24,7 +24,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -typedef struct CPUMBState CPUMBState; +typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif @@ -239,7 +239,7 @@ typedef struct CPUMBState CPUMBState; #define USE_NON_SECURE_M_AXI_DC_MASK 0x4 #define USE_NON_SECURE_M_AXI_IC_MASK 0x8 -struct CPUMBState { +struct CPUArchState { uint32_t bvalue; /* TCG temporary, only valid during a TB */ uint32_t btarget; /* Full resolved branch destination */ diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 56b1cbd091..ec5b588edb 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -524,8 +524,7 @@ struct TCState { }; struct MIPSITUState; -typedef struct CPUMIPSState CPUMIPSState; -struct CPUMIPSState { +typedef struct CPUArchState { TCState active_tc; CPUMIPSFPUContext active_fpu; @@ -1161,7 +1160,7 @@ struct CPUMIPSState { QEMUTimer *timer; /* Internal timer */ target_ulong exception_base; /* ExceptionBase input to the core */ uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ -}; +} CPUMIPSState; /** * MIPSCPU: diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d2ba0c5bbd..629b9e2301 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -25,7 +25,7 @@ #include "hw/core/cpu.h" #include "qom/object.h" -typedef struct CPUNios2State CPUNios2State; +typedef struct CPUArchState CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif @@ -155,7 +155,7 @@ struct Nios2CPUClass { #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 -struct CPUNios2State { +struct CPUArchState { uint32_t regs[NUM_CORE_REGS]; #if !defined(CONFIG_USER_ONLY) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index ee069b080c..19c2d9e7be 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -242,7 +242,7 @@ typedef struct CPUOpenRISCTLBContext { } CPUOpenRISCTLBContext; #endif -typedef struct CPUOpenRISCState { +typedef struct CPUArchState { target_ulong shadow_gpr[16][32]; /* Shadow registers */ target_ulong pc; /* Program counter */ diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 99a6b509af..87ea91ef9c 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -32,7 +32,7 @@ OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) -typedef struct CPUPPCState CPUPPCState; +typedef struct CPUArchState CPUPPCState; typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_dcr_t ppc_dcr_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index dcd83b503c..55ae99e1b8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1080,7 +1080,7 @@ struct ppc_radix_page_info { #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 -struct CPUPPCState { +struct CPUArchState { /* Most commonly used resources during translated code execution first */ target_ulong gpr[32]; /* general purpose registers */ target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */ @@ -1476,7 +1476,6 @@ void ppc_compat_add_property(Object *obj, const char *name, uint32_t *compat_pvr, const char *basedesc); #endif /* defined(TARGET_PPC64) */ -typedef CPUPPCState CPUArchState; typedef PowerPCCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 55635d68d5..6e6475b7a4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,7 +97,7 @@ enum { #define MAX_RISCV_PMPS (16) -typedef struct CPURISCVState CPURISCVState; +typedef struct CPUArchState CPURISCVState; #if !defined(CONFIG_USER_ONLY) #include "pmp.h" @@ -112,7 +112,7 @@ FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) -struct CPURISCVState { +struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ uint64_t fpr[32]; /* assume both F and D extensions */ diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 7310558e0c..f918c46b00 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -45,6 +45,4 @@ struct RXCPUClass { DeviceReset parent_reset; }; -#define CPUArchState struct CPURXState - #endif diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 58adf9edf6..0f3d9d5bd9 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -65,7 +65,7 @@ enum { NUM_REGS = 16, }; -typedef struct CPURXState { +typedef struct CPUArchState { /* CPU registers */ uint32_t regs[NUM_REGS]; /* general registers */ uint32_t psw_o; /* O bit of status register */ diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 9f3a0d86c5..dfb9ce4d88 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -63,6 +63,6 @@ struct S390CPUClass { void (*reset)(CPUState *cpu, cpu_reset_type type); }; -typedef struct CPUS390XState CPUS390XState; +typedef struct CPUArchState CPUS390XState; #endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a75e559134..3fe628c911 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -51,7 +51,7 @@ typedef struct PSW { uint64_t addr; } PSW; -struct CPUS390XState { +struct CPUArchState { uint64_t regs[16]; /* GP registers */ /* * The floating point registers are part of the vector registers. diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index fb9dd9db2f..d023b087b1 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -130,7 +130,7 @@ typedef struct memory_content { struct memory_content *next; } memory_content; -typedef struct CPUSH4State { +typedef struct CPUArchState { uint32_t flags; /* general execution flags */ uint32_t gregs[24]; /* general registers */ float32 fregs[32]; /* floating point registers */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5a7f1ed5d6..cfa263a696 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -420,7 +420,7 @@ struct CPUTimer typedef struct CPUTimer CPUTimer; -typedef struct CPUSPARCState CPUSPARCState; +typedef struct CPUArchState CPUSPARCState; #if defined(TARGET_SPARC64) typedef union { uint64_t mmuregs[16]; @@ -439,7 +439,7 @@ typedef union { }; } SparcV9MMU; #endif -struct CPUSPARCState { +struct CPUArchState { target_ulong gregs[8]; /* general registers */ target_ulong *regwptr; /* pointer to current register window */ target_ulong pc; /* program counter */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c461387e71..50fe16ae9c 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -28,8 +28,7 @@ struct tricore_boot_info; typedef struct tricore_def_t tricore_def_t; -typedef struct CPUTriCoreState CPUTriCoreState; -struct CPUTriCoreState { +typedef struct CPUArchState { /* GPR Register */ uint32_t gpr_a[16]; uint32_t gpr_d[16]; @@ -189,7 +188,7 @@ struct CPUTriCoreState { const tricore_def_t *cpu_model; void *irq[8]; struct QEMUTimer *timer; /* Internal timer */ -}; +} CPUTriCoreState; /** * TriCoreCPU: diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f2165b17e2..ea0de568af 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -306,7 +306,7 @@ typedef enum { INTTYPE_MAX } interrupt_type; -struct CPUXtensaState; +typedef struct CPUArchState CPUXtensaState; typedef struct xtensa_tlb_entry { uint32_t vaddr; @@ -506,7 +506,7 @@ enum { }; #endif -typedef struct CPUXtensaState { +struct CPUArchState { const XtensaConfig *config; uint32_t regs[16]; uint32_t pc; @@ -545,7 +545,7 @@ typedef struct CPUXtensaState { /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; -} CPUXtensaState; +}; /** * XtensaCPU: From patchwork Tue Feb 8 15:22:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDA6FC433F5 for ; Tue, 8 Feb 2022 16:47:49 +0000 (UTC) Received: from localhost ([::1]:50606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHTef-0002sU-0M for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 11:47:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSLt-0001RC-7D for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:22 -0500 Received: from [2607:f8b0:4864:20::102c] (port=45669 helo=mail-pj1-x102c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSLr-0000Ql-7m for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:20 -0500 Received: by mail-pj1-x102c.google.com with SMTP id g15-20020a17090a67cf00b001b7d5b6bedaso3131652pjm.4 for ; Tue, 08 Feb 2022 07:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UWXw31Ssif2lgsyaqU6PaE6PgTRRfqWihjZzyOMk/e0=; b=L+kxNgqDw9JON2YVfL0KcHsRX41CSSoR4a7cDp6FhykLY/NkXecxw8IQ1O5+wyynUf Xh0MMsDhOuzNkl09vNq6Cti9lWCJ7APK9UeCkg1rzhUBDEORvwipGXtWilcmEDP8z5JR DeFj87tPVCia3x+ZarEIaJ019wuWQWu8FDbrkwcEzwWtzblzPeVr3avdY1Q79zD4F3Fe V8y7R9wELvPgOtahsNeCebdzSsootTwK+CPFWN5OFWWa/dHu+DJBxdS5HVPjRc7E+PVE 2usTPlQqXiRM7g5eJQxTERxQvu4kocUrmud5HYrpFvGGe+D0MuHkpacTrmBSGR0Dm95h yDvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UWXw31Ssif2lgsyaqU6PaE6PgTRRfqWihjZzyOMk/e0=; b=2GtnbpxOFYjK+JztADhxm9yvLTpyRfpwc5UnzMfruFnSmdmPVASK5CMjhu+kB9gjjJ S0Yz//wmfmOu0apB5Iyd5MbSaPmiI2PHItIiCzLpeuPW0QGcW8zqk8Bx9U4PcoPlWOpE p66iz529m2UsvHLO8EDK32t4sMdfUjjYqF2fuodPjSoFrhRqC5CwZ72qJMaHx+VJFGZY RxYGqrptJmQH3jczLNg8j5MbgGUbqYunoy1y93eSJke6PIuKZ3aZ9gnzibBfigG46RWk ts5aePhQHB0CPCN9zLOjfMa/F/RlgkcKkgR5y/2fq6Av7kbop276j/02UZUETpUAQ3nU uBIw== X-Gm-Message-State: AOAM530YhkUyMp1ZFQkL9/i2Jgwlc9N+izf/CZid0nJgaxep28dkDrER DMREWwaKNDzQRUJEk98FTK40BpvliKE= X-Google-Smtp-Source: ABdhPJxoMLQz0rbL0f6Mv68smgjYsB7EjPYQ11oU32Ry3s3hRinXaRP7wMC/wFX36AVblLg/Q2ibmw== X-Received: by 2002:a17:90b:1802:: with SMTP id lw2mr1938731pjb.232.1644333857389; Tue, 08 Feb 2022 07:24:17 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id j23sm11711265pgb.75.2022.02.08.07.24.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:24:17 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 11/13] exec/cpu_ldst: Restrict TCG-specific code Date: Tue, 8 Feb 2022 16:22:41 +0100 Message-Id: <20220208152243.16452-12-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu_ldst.h | 53 ++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5c999966de..0932096d29 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -321,6 +321,8 @@ void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, MemOpIdx oi, uintptr_t retaddr); +#ifdef CONFIG_TCG + #if defined(CONFIG_USER_ONLY) extern __thread uintptr_t helper_retaddr; @@ -374,9 +376,34 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, { return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } - #endif /* defined(CONFIG_USER_ONLY) */ +/** + * tlb_vaddr_to_host: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index to use for lookup + * + * Look up the specified guest virtual index in the TCG softmmu TLB. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. + */ +#ifdef CONFIG_USER_ONLY +static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx) +{ + return g2h(env_cpu(env), addr); +} +#else +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx); +#endif + +#endif /* CONFIG_TCG */ + #ifdef TARGET_WORDS_BIGENDIAN # define cpu_lduw_data cpu_lduw_be_data # define cpu_ldsw_data cpu_ldsw_be_data @@ -450,28 +477,4 @@ static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr) return (int16_t)cpu_lduw_code(env, addr); } -/** - * tlb_vaddr_to_host: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index to use for lookup - * - * Look up the specified guest virtual index in the TCG softmmu TLB. - * If we can translate a host virtual address suitable for direct RAM - * access, without causing a guest exception, then return it. - * Otherwise (TLB entry is for an I/O access, guest software - * TLB fill required, etc) return NULL. - */ -#ifdef CONFIG_USER_ONLY -static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_idx) -{ - return g2h(env_cpu(env), addr); -} -#else -void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_idx); -#endif - #endif /* CPU_LDST_H */ From patchwork Tue Feb 8 15:22:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12739127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD384C433F5 for ; Tue, 8 Feb 2022 17:43:51 +0000 (UTC) Received: from localhost ([::1]:60346 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHUWs-0005MF-Bi for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 12:43:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSM0-0001YP-Cz for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:29 -0500 Received: from [2607:f8b0:4864:20::629] (port=44629 helo=mail-pl1-x629.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSLy-0000SD-JB for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:28 -0500 Received: by mail-pl1-x629.google.com with SMTP id y18so4472279plb.11 for ; Tue, 08 Feb 2022 07:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lzb9vh8nFU10wNe9E6b+5YxWozx92LwuARa5FvCR48U=; b=Do88ks0GAN0Atd6jgy6DB7Cfii1DI0sw3Mfngvwrn9lqolVCoSBW/I317s7omph+cv 1csGaRyWVipZvgw5om21Uly3kqcg89HdCNOWt5NB/4x87vL89P5c1SbaQ1eiPjHqgSco k6VqntIEN1GlrMz1nfuceGryxD5/nJmpvLzvzpRZx2DYAw3rwbd2FeJynZQWZR6QkwfM gBzSqBPC05E08gDwoZIn2C+BLPc0AqxaJg3NehUDTV1XzAYtDzXCy0H1IRlhAs06VbtC qoYJAjkb5DhddAwAIKuBRE+bKxvH500wQXi4lS404gx20hdV7uKLIcaL3PQqrsXcIYaL CtSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Lzb9vh8nFU10wNe9E6b+5YxWozx92LwuARa5FvCR48U=; b=4og1aoXMwQUEegvwXvWgGWiAdc2ZrlNp9ySaoNd8EQI4Xqqso7xdh9Qm6Z8swnRpsN Otfp4UBC8VMOvlJtNPsiJ946zPryuAsPqOQn2lnLjxKpoYMLfV72e3zEijZKdIr/r0PQ IIhtxpu2rXx/TVHa+kcdYaMB7ZMvNLl3ovQkIfKBvsLGUvB1yUbF30JbnCYV4Zp30pWB ymLW3qtS74allIAHs3I7A8ywaTfoeFqaMTw+AiW2EACWlbJYt3VOnTTLAUgvIEjlGwEK evClqnZ5YBTi7uJSqWOOiIZQn1PvHkCFq8BgXip44lY9ETaVeDMZfRTHKCMzvsgynIy0 ZUKA== X-Gm-Message-State: AOAM530TRGnIyK/oXTufbAXn03jo70/aVUHyEcNTt6yHdYAFbcGiVtfl NWrjSrcgTMUYqMXPUekfRTfP6Ht5b18= X-Google-Smtp-Source: ABdhPJzoEP4LODic+dibLIn+cKGZw/+2CqrMC3Yy/xy1PS6X+tftgNOoNNvvVxTpnCN4WDrli2oP+w== X-Received: by 2002:a17:902:cec5:: with SMTP id d5mr4814354plg.115.1644333865129; Tue, 08 Feb 2022 07:24:25 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id a12sm12428776pfv.18.2022.02.08.07.24.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:24:24 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 12/13] exec/cpu-all: Restrict cpu_copy() to user emulation Date: Tue, 8 Feb 2022 16:22:42 +0100 Message-Id: <20220208152243.16452-13-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::629 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c0f0fab28a..84188febfa 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -296,10 +296,11 @@ void *page_alloc_target_data(target_ulong address, size_t size); * at @address, as per page_alloc_target_data. */ void *page_get_target_data(target_ulong address); -#endif CPUArchState *cpu_copy(CPUArchState *env); +#endif /* CONFIG_USER_ONLY */ + /* Flags for use in ENV->INTERRUPT_PENDING. The numbers assigned here are non-sequential in order to preserve From patchwork Tue Feb 8 15:22:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12738990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 602BAC433F5 for ; Tue, 8 Feb 2022 16:27:26 +0000 (UTC) Received: from localhost ([::1]:46246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHTKv-0004rA-68 for qemu-devel@archiver.kernel.org; Tue, 08 Feb 2022 11:27:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHSMD-0001xg-OX for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:41 -0500 Received: from [2607:f8b0:4864:20::1034] (port=53977 helo=mail-pj1-x1034.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHSM9-0000Tt-3p for qemu-devel@nongnu.org; Tue, 08 Feb 2022 10:24:41 -0500 Received: by mail-pj1-x1034.google.com with SMTP id qe15so7127436pjb.3 for ; Tue, 08 Feb 2022 07:24:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Fg4IjbLcHTX9hqYq7qkMPcz1t9uhjiu/PXI4XLXN4Lk=; b=Js6mSOFBzJA4rDbHVDyzia5svZ3iQdNFRkyna7cX+nDIpt/d63eyaSUQSCiPnjP/Vs ry2PgieMIIrG+V4V9bhTFJ0DV+92AsBPVJrtclnZvPWd58X2O10rbeTPL8ZiVKhFHU/+ DkzuM28qnSpa1J/KS4j1WUYdQcVUmEInddiQaEsH9svZPtg132xlWZz1rl0DXSuFehZU tMMgjOKOy3/qcS7U5G5smZpNw0DsBZG6WNBb6tpsfJ/szEov4Clj2y2BfrSeajyYY668 k9P8PRlyQ3CHz6Vb9Piv0kWU++qKic6MCr6rkR76hzLveE5h16IzL3PdHe+kI6A+RFmo ksCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Fg4IjbLcHTX9hqYq7qkMPcz1t9uhjiu/PXI4XLXN4Lk=; b=VEqwTjQ/9HMLnM0V631JM2taR0eL3tZCrYFTwmM0b0yoExUKpT1Xf/V6LnHMACMFlH 57SJQGhyPFgZ3lUIXTGblLV1v6ew1Dpxg11Php6cdJDbzDtlqSOIYOwaFac3Wg/1UwNU kidhRWDE+uLtJ8TqAcIl5WYKBGqEx0718X+2lF1uWJBz+AYht3ud6fOhdMIPMz3le/UC K8UvkT7ABo1JsWFhexB8ypt98or5iHG8dFK+AzZVWPJu01CkuEfQiRA8mVXxm13+HXfR O39k7wSLjFBP1DHUivFDWSufQDOTXooLAChmAYRoFfQMby031ZQG30I7oXKJa/DaKKpN yDfg== X-Gm-Message-State: AOAM531SLBE3UVQHmPcalqP8xqPayPICFCiqWrV6vXSt/egR/BZzq3Mt 2b8QzNEZFidDcXiDYOpJMqAqRzJhLxc= X-Google-Smtp-Source: ABdhPJx+kZgiqtHE83gyrUjGuqRHnPJ/ZA5J2uilHSbkmo2nTMzvQEOqk01MRFYk6AUKclwKjk3KaA== X-Received: by 2002:a17:90a:3846:: with SMTP id l6mr1855201pjf.221.1644333873485; Tue, 08 Feb 2022 07:24:33 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id nn12sm3148055pjb.24.2022.02.08.07.24.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 08 Feb 2022 07:24:33 -0800 (PST) To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 13/13] exec: Move translation declarations to 'translate-all.h' Date: Tue, 8 Feb 2022 16:22:43 +0100 Message-Id: <20220208152243.16452-14-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220208152243.16452-1-f4bug@amsat.org> References: <20220208152243.16452-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Translation declarations are only useful to TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé --- accel/stubs/tcg-stub.c | 1 + accel/tcg/cpu-exec-common.c | 1 + accel/tcg/cpu-exec.c | 1 + accel/tcg/cputlb.c | 1 + accel/tcg/hmp.c | 2 +- accel/tcg/internal.h | 2 +- accel/tcg/plugin-gen.c | 2 +- accel/tcg/tb-hash.h | 2 +- accel/tcg/tcg-accel-ops-icount.c | 2 +- accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/tcg-accel-ops.c | 2 +- accel/tcg/tcg-runtime.c | 1 + accel/tcg/translate-all.c | 1 + accel/tcg/translator.c | 2 +- accel/tcg/user-exec.c | 2 +- bsd-user/main.c | 2 +- bsd-user/qemu.h | 2 +- gdbstub.c | 1 + hw/ppc/spapr_hcall.c | 1 + include/exec/cpu-all.h | 5 - include/exec/cpu_ldst.h | 1 + include/exec/exec-all.h | 350 ---------------------- include/exec/ram_addr.h | 2 - include/exec/translate-all.h | 372 +++++++++++++++++++++++- linux-user/main.c | 2 +- linux-user/user-internals.h | 2 +- plugins/api.c | 2 +- plugins/core.c | 2 +- plugins/loader.c | 2 +- semihosting/console.c | 1 + target/alpha/cpu.c | 2 +- target/alpha/fpu_helper.c | 2 +- target/alpha/helper.c | 1 + target/alpha/int_helper.c | 2 +- target/alpha/mem_helper.c | 1 + target/alpha/sys_helper.c | 1 + target/alpha/translate.c | 2 +- target/alpha/vax_helper.c | 2 +- target/arm/cpu.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 2 +- target/arm/m_helper.c | 2 +- target/arm/mte_helper.c | 2 +- target/arm/mve_helper.c | 2 +- target/arm/op_helper.c | 1 + target/arm/pauth_helper.c | 2 +- target/arm/sve_helper.c | 2 +- target/arm/tlb_helper.c | 1 + target/arm/translate-a64.c | 2 +- target/arm/translate-mve.c | 2 +- target/arm/translate-neon.c | 2 +- target/arm/translate-sve.c | 2 +- target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 2 +- target/avr/cpu.c | 2 +- target/avr/helper.c | 1 + target/avr/translate.c | 2 +- target/cris/helper.c | 1 + target/cris/mmu.c | 1 + target/cris/op_helper.c | 1 + target/cris/translate.c | 2 +- target/hexagon/cpu.c | 2 +- target/hexagon/op_helper.c | 1 + target/hppa/cpu.c | 1 + target/hppa/helper.c | 1 + target/hppa/mem_helper.c | 1 + target/hppa/op_helper.c | 1 + target/hppa/translate.c | 2 +- target/i386/helper.c | 1 + target/i386/machine.c | 1 + target/i386/tcg/excp_helper.c | 1 + target/i386/tcg/fpu_helper.c | 2 + target/i386/tcg/helper-tcg.h | 2 +- target/i386/tcg/int_helper.c | 2 +- target/i386/tcg/mem_helper.c | 1 + target/i386/tcg/misc_helper.c | 1 + target/i386/tcg/mpx_helper.c | 2 +- target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/sysemu/bpt_helper.c | 1 + target/i386/tcg/sysemu/svm_helper.c | 1 + target/i386/tcg/translate.c | 2 +- target/i386/tcg/user/excp_helper.c | 1 + target/i386/tcg/user/seg_helper.c | 1 + target/m68k/fpu_helper.c | 2 +- target/m68k/helper.c | 1 + target/m68k/op_helper.c | 1 + target/m68k/translate.c | 2 +- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 1 + target/microblaze/mmu.c | 1 + target/microblaze/op_helper.c | 1 + target/microblaze/translate.c | 2 +- target/mips/cpu.c | 2 +- target/mips/sysemu/cp0.c | 1 + target/mips/sysemu/physaddr.c | 2 +- target/mips/tcg/exception.c | 1 + target/mips/tcg/fpu_helper.c | 2 +- target/mips/tcg/ldst_helper.c | 2 +- target/mips/tcg/msa_helper.c | 2 +- target/mips/tcg/op_helper.c | 2 +- target/mips/tcg/sysemu/cp0_helper.c | 1 + target/mips/tcg/sysemu/special_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 1 + target/nios2/helper.c | 1 + target/nios2/mmu.c | 1 + target/nios2/op_helper.c | 1 + target/nios2/translate.c | 2 +- target/openrisc/exception.c | 1 + target/openrisc/exception_helper.c | 1 + target/openrisc/interrupt.c | 2 +- target/openrisc/interrupt_helper.c | 2 +- target/openrisc/mmu.c | 1 + target/openrisc/sys_helper.c | 1 + target/openrisc/translate.c | 2 +- target/ppc/excp_helper.c | 1 + target/ppc/fpu_helper.c | 2 +- target/ppc/helper_regs.c | 1 + target/ppc/machine.c | 2 +- target/ppc/mem_helper.c | 2 +- target/ppc/misc_helper.c | 1 + target/ppc/mmu-hash32.c | 2 +- target/ppc/mmu-hash64.c | 2 +- target/ppc/mmu-radix64.c | 2 +- target/ppc/mmu_common.c | 2 +- target/ppc/mmu_helper.c | 1 + target/ppc/power8-pmu.c | 2 +- target/ppc/timebase_helper.c | 2 +- target/ppc/translate.c | 2 +- target/ppc/user_only_helper.c | 1 + target/riscv/bitmanip_helper.c | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 1 + target/riscv/csr.c | 1 + target/riscv/fpu_helper.c | 2 +- target/riscv/m128_helper.c | 2 +- target/riscv/op_helper.c | 1 + target/riscv/pmp.c | 1 + target/riscv/translate.c | 2 +- target/riscv/vector_helper.c | 2 +- target/rx/cpu.c | 1 + target/rx/op_helper.c | 1 + target/rx/translate.c | 2 +- target/s390x/gdbstub.c | 1 + target/s390x/interrupt.c | 2 +- target/s390x/mmu_helper.c | 1 + target/s390x/sigp.c | 1 + target/s390x/tcg/cc_helper.c | 1 + target/s390x/tcg/crypto_helper.c | 2 +- target/s390x/tcg/excp_helper.c | 1 + target/s390x/tcg/fpu_helper.c | 2 +- target/s390x/tcg/int_helper.c | 2 +- target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/s390x/tcg/translate.c | 2 +- target/s390x/tcg/vec_fpu_helper.c | 2 +- target/s390x/tcg/vec_helper.c | 2 +- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 1 + target/sh4/op_helper.c | 1 + target/sh4/translate.c | 2 +- target/sparc/cpu.c | 2 +- target/sparc/fop_helper.c | 1 + target/sparc/helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/sparc/machine.c | 2 +- target/sparc/mmu_helper.c | 1 + target/sparc/translate.c | 2 +- target/sparc/win_helper.c | 2 +- target/tricore/cpu.c | 2 +- target/tricore/helper.c | 1 + target/tricore/op_helper.c | 1 + target/tricore/translate.c | 2 +- target/xtensa/dbg_helper.c | 2 +- target/xtensa/exc_helper.c | 1 + target/xtensa/fpu_helper.c | 2 +- target/xtensa/helper.c | 1 + target/xtensa/mmu_helper.c | 1 + target/xtensa/op_helper.c | 2 +- target/xtensa/translate.c | 2 +- target/xtensa/win_helper.c | 2 +- tcg/region.c | 2 +- tcg/tcg-op.c | 2 +- tcg/tcg.c | 2 +- 185 files changed, 553 insertions(+), 459 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index d8162673ae..7ff11ac604 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" void tb_flush(CPUState *cpu) { diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index be6fe45aa5..40fbffebe6 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -21,6 +21,7 @@ #include "sysemu/cpus.h" #include "sysemu/tcg.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" bool tcg_allowed; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8b4cd6c59d..fd96f2725c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -27,6 +27,7 @@ #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" #include "qemu/atomic.h" #include "qemu/compiler.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5e0d0eebc3..158b2f0df7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -21,6 +21,7 @@ #include "qemu/main-loop.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/memory.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" diff --git a/accel/tcg/hmp.c b/accel/tcg/hmp.c index d2ea352655..144767e0f8 100644 --- a/accel/tcg/hmp.c +++ b/accel/tcg/hmp.c @@ -2,7 +2,7 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/qapi-commands-machine.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "monitor/monitor.h" #include "sysemu/tcg.h" diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 881bc1ede0..6cb7579b58 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -9,7 +9,7 @@ #ifndef ACCEL_TCG_INTERNAL_H #define ACCEL_TCG_INTERNAL_H -#include "exec/exec-all.h" +#include "exec/translate-all.h" TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags, diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 22d95fe1c3..bc9946ebfd 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -45,7 +45,7 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/plugin-gen.h" #include "exec/translator.h" diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index 0a273d9605..e0f8edef37 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -21,7 +21,7 @@ #define EXEC_TB_HASH_H #include "exec/cpu-defs.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/xxhash.h" #ifdef CONFIG_SOFTMMU diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index bdaf2c943b..ff93abdf5a 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -30,7 +30,7 @@ #include "sysemu/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-icount.h" diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c index dc421c8fd7..d49af140d4 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -31,7 +31,7 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "hw/boards.h" #include "tcg-accel-ops.h" diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index a805fb6bdd..2678815a43 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -31,7 +31,7 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index ea7dcad674..ed484eb226 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -32,7 +32,7 @@ #include "sysemu/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index e4e030043f..74f27be5ee 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "disas/disas.h" #include "exec/log.h" #include "tcg/tcg.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bd71db59a9..b635e8ce14 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -24,6 +24,7 @@ #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" #if defined(CONFIG_USER_ONLY) #include "qemu.h" diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index f06c314266..3aa252a2a0 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -11,7 +11,7 @@ #include "qemu/error-report.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gen-icount.h" #include "exec/log.h" #include "exec/translator.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 6f5d4933f0..f463e61844 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "hw/core/tcg-cpu-ops.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index f1d58e905e..0412d65cab 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -38,7 +38,7 @@ #include "qemu/path.h" #include "qemu/help_option.h" #include "qemu/module.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" #include "qemu/timer.h" #include "qemu/envlist.h" diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 02921ac8b3..0ee7380c6a 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -21,7 +21,7 @@ #include "cpu.h" #include "qemu/units.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #undef DEBUG_REMAP diff --git a/gdbstub.c b/gdbstub.c index 3c14c6a038..2f5ab828bf 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -31,6 +31,7 @@ #include "qemu/cutils.h" #include "qemu/module.h" #include "trace/trace-root.h" +#include "exec/translate-all.h" #include "exec/gdbstub.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 222c1b6bbd..1873a0e719 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -8,6 +8,7 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "helper_regs.h" #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_cpu_core.h" diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 84188febfa..efe1832c61 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -429,11 +429,6 @@ void dump_opcount_info(GString *buf); #endif /* !CONFIG_USER_ONLY */ -/* accel/tcg/cpu-exec.c */ -int cpu_exec(CPUState *cpu); -void tcg_exec_realizefn(CPUState *cpu, Error **errp); -void tcg_exec_unrealizefn(CPUState *cpu); - /** * cpu_set_cpustate_pointers(cpu) * @cpu: The cpu object diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 0932096d29..a1802306eb 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -62,6 +62,7 @@ #ifndef CPU_LDST_H #define CPU_LDST_H +#include "exec/cpu-defs.h" #include "exec/memopidx.h" #include "qemu/int128.h" #include "cpu.h" diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d2cb0981f4..c9d4be3fec 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -39,30 +39,6 @@ typedef ram_addr_t tb_page_addr_t; #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT #endif -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns); -void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb, - target_ulong *data); - -/** - * cpu_restore_state: - * @cpu: the vCPU state is to be restore to - * @searched_pc: the host PC the fault occurred at - * @will_exit: true if the TB executed will be interrupted after some - cpu adjustments. Required for maintaining the correct - icount valus - * @return: true if state was restored, false otherwise - * - * Attempt to restore the state for a fault occurring in translated - * code. If the searched_pc is not in translated code no state is - * restored and the function returns false. - */ -bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit); - -void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); -void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); -void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); -void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); - /** * cpu_loop_exit_requested: * @cpu: The CPU state to be tested @@ -381,207 +357,6 @@ static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, { } #endif -/** - * probe_access: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @size: size of the access - * @access_type: read, write or execute permission - * @mmu_idx: MMU index to use for lookup - * @retaddr: return address for unwinding - * - * Look up the guest virtual address @addr. Raise an exception if the - * page does not satisfy @access_type. Raise an exception if the - * access (@addr, @size) hits a watchpoint. For writes, mark a clean - * page as dirty. - * - * Finally, return the host address for a page that is backed by RAM, - * or NULL if the page requires I/O. - */ -void *probe_access(CPUArchState *env, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - -static inline void *probe_write(CPUArchState *env, target_ulong addr, int size, - int mmu_idx, uintptr_t retaddr) -{ - return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); -} - -static inline void *probe_read(CPUArchState *env, target_ulong addr, int size, - int mmu_idx, uintptr_t retaddr) -{ - return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); -} - -/** - * probe_access_flags: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: read, write or execute permission - * @mmu_idx: MMU index to use for lookup - * @nonfault: suppress the fault - * @phost: return value for host address - * @retaddr: return address for unwinding - * - * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for - * the page, and storing the host address for RAM in @phost. - * - * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK. - * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags. - * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. - * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. - */ -int probe_access_flags(CPUArchState *env, target_ulong addr, - MMUAccessType access_type, int mmu_idx, - bool nonfault, void **phost, uintptr_t retaddr); - -#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ - -/* Estimated block size for TB allocation. */ -/* ??? The following is based on a 2015 survey of x86_64 host output. - Better would seem to be some sort of dynamically sized TB array, - adapting to the block sizes actually being produced. */ -#if defined(CONFIG_SOFTMMU) -#define CODE_GEN_AVG_BLOCK_SIZE 400 -#else -#define CODE_GEN_AVG_BLOCK_SIZE 150 -#endif - -/* - * Translation Cache-related fields of a TB. - * This struct exists just for convenience; we keep track of TB's in a binary - * search tree, and the only fields needed to compare TB's in the tree are - * @ptr and @size. - * Note: the address of search data can be obtained by adding @size to @ptr. - */ -struct tb_tc { - const void *ptr; /* pointer to the translated code */ - size_t size; -}; - -struct TranslationBlock { - target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ - target_ulong cs_base; /* CS base for this block */ - uint32_t flags; /* flags defining in which context the code was generated */ - uint32_t cflags; /* compile flags */ - -/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ -#define CF_COUNT_MASK 0x000001ff -#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ -#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ -#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ -#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ -#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ -#define CF_CLUSTER_SHIFT 24 - - /* Per-vCPU dynamic tracing state used to generate this TB */ - uint32_t trace_vcpu_dstate; - - /* - * Above fields used for comparing - */ - - /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ - uint16_t size; - uint16_t icount; - - struct tb_tc tc; - - /* first and second physical page containing code. The lower bit - of the pointer tells the index in page_next[]. - The list is protected by the TB's page('s) lock(s) */ - uintptr_t page_next[2]; - tb_page_addr_t page_addr[2]; - - /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */ - QemuSpin jmp_lock; - - /* The following data are used to directly call another TB from - * the code of this one. This can be done either by emitting direct or - * indirect native jump instructions. These jumps are reset so that the TB - * just continues its execution. The TB can be linked to another one by - * setting one of the jump targets (or patching the jump instruction). Only - * two of such jumps are supported. - */ - uint16_t jmp_reset_offset[2]; /* offset of original jump target */ -#define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ - uintptr_t jmp_target_arg[2]; /* target address or offset */ - - /* - * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps. - * Each TB can have two outgoing jumps, and therefore can participate - * in two lists. The list entries are kept in jmp_list_next[2]. The least - * significant bit (LSB) of the pointers in these lists is used to encode - * which of the two list entries is to be used in the pointed TB. - * - * List traversals are protected by jmp_lock. The destination TB of each - * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock - * can be acquired from any origin TB. - * - * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is - * being invalidated, so that no further outgoing jumps from it can be set. - * - * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained - * to a destination TB that has CF_INVALID set. - */ - uintptr_t jmp_list_head; - uintptr_t jmp_list_next[2]; - uintptr_t jmp_dest[2]; -}; - -/* Hide the qatomic_read to make code a little easier on the eyes */ -static inline uint32_t tb_cflags(const TranslationBlock *tb) -{ - return qatomic_read(&tb->cflags); -} - -/* current cflags for hashing/comparison */ -uint32_t curr_cflags(CPUState *cpu); - -/* TranslationBlock invalidate API */ -#if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(target_ulong addr); -void tb_invalidate_phys_range(target_ulong start, target_ulong end); -#else -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); -#endif -void tb_flush(CPUState *cpu); -void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); -TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags, - uint32_t cflags); -void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); - -/* GETPC is the true target of the return instruction that we'll execute. */ -#if defined(CONFIG_TCG_INTERPRETER) -extern __thread uintptr_t tci_tb_ptr; -# define GETPC() tci_tb_ptr -#else -# define GETPC() \ - ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) -#endif - -/* The true return address will often point to a host insn that is part of - the next translated guest insn. Adjust the address backward to point to - the middle of the call insn. Subtracting one would do the job except for - several compressed mode architectures (arm, mips) which set the low bit - to indicate the compressed mode; subtracting two works around that. It - is also the case that there are no host isas that contain a call insn - smaller than 4 bytes, so we don't worry about special-casing this. */ -#define GETPC_ADJ 2 - -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG) -void assert_no_pages_locked(void); -#else -static inline void assert_no_pages_locked(void) -{ -} -#endif #if !defined(CONFIG_USER_ONLY) @@ -596,131 +371,6 @@ static inline void assert_no_pages_locked(void) */ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs); -#endif - -#if defined(CONFIG_USER_ONLY) -void mmap_lock(void); -void mmap_unlock(void); -bool have_mmap_lock(void); - -/** - * get_page_addr_code() - user-mode version - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * Returns @addr. - */ -static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, - target_ulong addr) -{ - return addr; -} - -/** - * get_page_addr_code_hostp() - user-mode version - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * Returns @addr. - * - * If @hostp is non-NULL, sets *@hostp to the host address where @addr's content - * is kept. - */ -static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, - target_ulong addr, - void **hostp) -{ - if (hostp) { - *hostp = g2h_untagged(addr); - } - return addr; -} - -/** - * adjust_signal_pc: - * @pc: raw pc from the host signal ucontext_t. - * @is_write: host memory operation was write, or read-modify-write. - * - * Alter @pc as required for unwinding. Return the type of the - * guest memory access -- host reads may be for guest execution. - */ -MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); - -/** - * handle_sigsegv_accerr_write: - * @cpu: the cpu context - * @old_set: the sigset_t from the signal ucontext_t - * @host_pc: the host pc, adjusted for the signal - * @host_addr: the host address of the fault - * - * Return true if the write fault has been handled, and should be re-tried. - */ -bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, - uintptr_t host_pc, abi_ptr guest_addr); - -/** - * cpu_loop_exit_sigsegv: - * @cpu: the cpu context - * @addr: the guest address of the fault - * @access_type: access was read/write/execute - * @maperr: true for invalid page, false for permission fault - * @ra: host pc for unwinding - * - * Use the TCGCPUOps hook to record cpu state, do guest operating system - * specific things to raise SIGSEGV, and jump to the main cpu loop. - */ -void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, - MMUAccessType access_type, - bool maperr, uintptr_t ra); - -/** - * cpu_loop_exit_sigbus: - * @cpu: the cpu context - * @addr: the guest address of the alignment fault - * @access_type: access was read/write/execute - * @ra: host pc for unwinding - * - * Use the TCGCPUOps hook to record cpu state, do guest operating system - * specific things to raise SIGBUS, and jump to the main cpu loop. - */ -void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, - MMUAccessType access_type, - uintptr_t ra); - -#else -static inline void mmap_lock(void) {} -static inline void mmap_unlock(void) {} - -/** - * get_page_addr_code() - full-system version - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * If we cannot translate and execute from the entire RAM page, or if - * the region is not backed by RAM, returns -1. Otherwise, returns the - * ram_addr_t corresponding to the guest code at @addr. - * - * Note: this function can trigger an exception. - */ -tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr); - -/** - * get_page_addr_code_hostp() - full-system version - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * See get_page_addr_code() (full-system version) for documentation on the - * return value. - * - * Sets *@hostp (when @hostp is non-NULL) as follows. - * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp - * to the host address where @addr's content is kept. - * - * Note: this function can trigger an exception. - */ -tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, - void **hostp); - void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 64fb936c7c..4c0b614d56 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -147,8 +147,6 @@ static inline void qemu_ram_block_writeback(RAMBlock *block) #define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) #define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE)) -void tb_invalidate_phys_range(ram_addr_t start, ram_addr_t end); - static inline bool cpu_physical_memory_get_dirty(ram_addr_t start, ram_addr_t length, unsigned client) diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index 9f646389af..9e4f75b784 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -19,8 +19,299 @@ #ifndef TRANSLATE_ALL_H #define TRANSLATE_ALL_H -#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +/* allow to see translation results - the slowdown should be negligible, so we leave it */ +#define DEBUG_DISAS + +/* Page tracking code uses ram addresses in system mode, and virtual + addresses in userspace mode. Define tb_page_addr_t to be an appropriate + type. */ +#if defined(CONFIG_USER_ONLY) +typedef abi_ulong tb_page_addr_t; +#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx +#else +typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT +#endif + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns); +void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb, + target_ulong *data); + +#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ + +/* Estimated block size for TB allocation. */ +/* ??? The following is based on a 2015 survey of x86_64 host output. + Better would seem to be some sort of dynamically sized TB array, + adapting to the block sizes actually being produced. */ +#if defined(CONFIG_SOFTMMU) +#define CODE_GEN_AVG_BLOCK_SIZE 400 +#else +#define CODE_GEN_AVG_BLOCK_SIZE 150 +#endif + +/* + * Translation Cache-related fields of a TB. + * This struct exists just for convenience; we keep track of TB's in a binary + * search tree, and the only fields needed to compare TB's in the tree are + * @ptr and @size. + * Note: the address of search data can be obtained by adding @size to @ptr. + */ +struct tb_tc { + const void *ptr; /* pointer to the translated code */ + size_t size; +}; + +struct TranslationBlock { + target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ + target_ulong cs_base; /* CS base for this block */ + uint32_t flags; /* flags defining in which context the code was generated */ + uint32_t cflags; /* compile flags */ + +/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ +#define CF_COUNT_MASK 0x000001ff +#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ +#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_CLUSTER_SHIFT 24 + + /* Per-vCPU dynamic tracing state used to generate this TB */ + uint32_t trace_vcpu_dstate; + + /* + * Above fields used for comparing + */ + + /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ + uint16_t size; + uint16_t icount; + + struct tb_tc tc; + + /* first and second physical page containing code. The lower bit + of the pointer tells the index in page_next[]. + The list is protected by the TB's page('s) lock(s) */ + uintptr_t page_next[2]; + tb_page_addr_t page_addr[2]; + + /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */ + QemuSpin jmp_lock; + + /* The following data are used to directly call another TB from + * the code of this one. This can be done either by emitting direct or + * indirect native jump instructions. These jumps are reset so that the TB + * just continues its execution. The TB can be linked to another one by + * setting one of the jump targets (or patching the jump instruction). Only + * two of such jumps are supported. + */ + uint16_t jmp_reset_offset[2]; /* offset of original jump target */ +#define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ + uintptr_t jmp_target_arg[2]; /* target address or offset */ + + /* + * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps. + * Each TB can have two outgoing jumps, and therefore can participate + * in two lists. The list entries are kept in jmp_list_next[2]. The least + * significant bit (LSB) of the pointers in these lists is used to encode + * which of the two list entries is to be used in the pointed TB. + * + * List traversals are protected by jmp_lock. The destination TB of each + * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock + * can be acquired from any origin TB. + * + * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is + * being invalidated, so that no further outgoing jumps from it can be set. + * + * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained + * to a destination TB that has CF_INVALID set. + */ + uintptr_t jmp_list_head; + uintptr_t jmp_list_next[2]; + uintptr_t jmp_dest[2]; +}; + +/* Hide the qatomic_read to make code a little easier on the eyes */ +static inline uint32_t tb_cflags(const TranslationBlock *tb) +{ + return qatomic_read(&tb->cflags); +} + +/* current cflags for hashing/comparison */ +uint32_t curr_cflags(CPUState *cpu); + +/* TranslationBlock invalidate API */ +#if defined(CONFIG_USER_ONLY) +void tb_invalidate_phys_addr(target_ulong addr); +void tb_invalidate_phys_range(target_ulong start, target_ulong end); +#else +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); +void tb_invalidate_phys_range(ram_addr_t start, ram_addr_t end); +#endif +void tb_flush(CPUState *cpu); +void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); +TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, + target_ulong cs_base, uint32_t flags, + uint32_t cflags); +void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); + +/* GETPC is the true target of the return instruction that we'll execute. */ +#if defined(CONFIG_TCG_INTERPRETER) +extern __thread uintptr_t tci_tb_ptr; +# define GETPC() tci_tb_ptr +#else +# define GETPC() \ + ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) +#endif + +/* The true return address will often point to a host insn that is part of + the next translated guest insn. Adjust the address backward to point to + the middle of the call insn. Subtracting one would do the job except for + several compressed mode architectures (arm, mips) which set the low bit + to indicate the compressed mode; subtracting two works around that. It + is also the case that there are no host isas that contain a call insn + smaller than 4 bytes, so we don't worry about special-casing this. */ +#define GETPC_ADJ 2 + +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG) +void assert_no_pages_locked(void); +#else +static inline void assert_no_pages_locked(void) +{ +} +#endif + +#if defined(CONFIG_USER_ONLY) +void mmap_lock(void); +void mmap_unlock(void); +bool have_mmap_lock(void); + +/** + * get_page_addr_code() - user-mode version + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * Returns @addr. + */ +static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, + target_ulong addr) +{ + return addr; +} + +/** + * get_page_addr_code_hostp() - user-mode version + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * Returns @addr. + * + * If @hostp is non-NULL, sets *@hostp to the host address where @addr's content + * is kept. + */ +static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, + target_ulong addr, + void **hostp) +{ + if (hostp) { + *hostp = g2h_untagged(addr); + } + return addr; +} + +/** + * adjust_signal_pc: + * @pc: raw pc from the host signal ucontext_t. + * @is_write: host memory operation was write, or read-modify-write. + * + * Alter @pc as required for unwinding. Return the type of the + * guest memory access -- host reads may be for guest execution. + */ +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); + +/** + * handle_sigsegv_accerr_write: + * @cpu: the cpu context + * @old_set: the sigset_t from the signal ucontext_t + * @host_pc: the host pc, adjusted for the signal + * @host_addr: the host address of the fault + * + * Return true if the write fault has been handled, and should be re-tried. + */ +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, + uintptr_t host_pc, abi_ptr guest_addr); + +/** + * cpu_loop_exit_sigsegv: + * @cpu: the cpu context + * @addr: the guest address of the fault + * @access_type: access was read/write/execute + * @maperr: true for invalid page, false for permission fault + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGSEGV, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); + +/** + * cpu_loop_exit_sigbus: + * @cpu: the cpu context + * @addr: the guest address of the alignment fault + * @access_type: access was read/write/execute + * @ra: host pc for unwinding + * + * Use the TCGCPUOps hook to record cpu state, do guest operating system + * specific things to raise SIGBUS, and jump to the main cpu loop. + */ +void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + uintptr_t ra); + +#else +static inline void mmap_lock(void) {} +static inline void mmap_unlock(void) {} + +/** + * get_page_addr_code() - full-system version + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * If we cannot translate and execute from the entire RAM page, or if + * the region is not backed by RAM, returns -1. Otherwise, returns the + * ram_addr_t corresponding to the guest code at @addr. + * + * Note: this function can trigger an exception. + */ +tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr); + +/** + * get_page_addr_code_hostp() - full-system version + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * See get_page_addr_code() (full-system version) for documentation on the + * return value. + * + * Sets *@hostp (when @hostp is non-NULL) as follows. + * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp + * to the host address where @addr's content is kept. + * + * Note: this function can trigger an exception. + */ +tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, + void **hostp); + +#endif /* translate-all.c */ struct page_collection *page_collection_lock(tb_page_addr_t start, @@ -37,4 +328,83 @@ void page_protect(tb_page_addr_t page_addr); int page_unprotect(target_ulong address, uintptr_t pc); #endif +/** + * probe_access: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @size: size of the access + * @access_type: read, write or execute permission + * @mmu_idx: MMU index to use for lookup + * @retaddr: return address for unwinding + * + * Look up the guest virtual address @addr. Raise an exception if the + * page does not satisfy @access_type. Raise an exception if the + * access (@addr, @size) hits a watchpoint. For writes, mark a clean + * page as dirty. + * + * Finally, return the host address for a page that is backed by RAM, + * or NULL if the page requires I/O. + */ +void *probe_access(CPUArchState *env, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); + +static inline void *probe_write(CPUArchState *env, target_ulong addr, int size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); +} + +static inline void *probe_read(CPUArchState *env, target_ulong addr, int size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); +} + +/** + * probe_access_flags: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: read, write or execute permission + * @mmu_idx: MMU index to use for lookup + * @nonfault: suppress the fault + * @phost: return value for host address + * @retaddr: return address for unwinding + * + * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for + * the page, and storing the host address for RAM in @phost. + * + * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK. + * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags. + * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. + * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. + */ +int probe_access_flags(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, uintptr_t retaddr); + +/** + * cpu_restore_state: + * @cpu: the vCPU state is to be restore to + * @searched_pc: the host PC the fault occurred at + * @will_exit: true if the TB executed will be interrupted after some + cpu adjustments. Required for maintaining the correct + icount valus + * @return: true if state was restored, false otherwise + * + * Attempt to restore the state for a fault occurring in translated + * code. If the searched_pc is not in translated code no state is + * restored and the function returns false. + */ +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit); + +void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); +void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); +void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); +void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); + +/* accel/tcg/cpu-exec.c */ +int cpu_exec(CPUState *cpu); +void tcg_exec_realizefn(CPUState *cpu, Error **errp); +void tcg_exec_unrealizefn(CPUState *cpu); + #endif /* TRANSLATE_ALL_H */ diff --git a/linux-user/main.c b/linux-user/main.c index 16def5215d..7bd4ce01e2 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -39,7 +39,7 @@ #include "qemu/help_option.h" #include "qemu/module.h" #include "qemu/plugin.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gdbstub.h" #include "tcg/tcg.h" #include "qemu/timer.h" diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index a8fdd6933b..5fc8d91a3d 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -19,7 +19,7 @@ #define LINUX_USER_USER_INTERNALS_H #include "exec/user/thunk.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/log.h" extern char *exec_path; diff --git a/plugins/api.c b/plugins/api.c index 19595460fb..974e6d6c29 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -38,7 +38,7 @@ #include "qemu/plugin.h" #include "qemu/log.h" #include "tcg/tcg.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/ram_addr.h" #include "disas/disas.h" #include "plugin.h" diff --git a/plugins/core.c b/plugins/core.c index 792262da08..22a8ba8237 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -23,7 +23,7 @@ #include "hw/core/cpu.h" #include "exec/cpu-common.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" diff --git a/plugins/loader.c b/plugins/loader.c index a4ec281692..2597198c42 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -27,7 +27,7 @@ #include "qemu/xxhash.h" #include "qemu/plugin.h" #include "hw/core/cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif diff --git a/semihosting/console.c b/semihosting/console.c index ef6958d844..3c4ea3c2f8 100644 --- a/semihosting/console.c +++ b/semihosting/console.c @@ -20,6 +20,7 @@ #include "semihosting/console.h" #include "exec/gdbstub.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/log.h" #include "chardev/char.h" #include "chardev/char-fe.h" diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index a8990d401b..34c7117b4a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -23,7 +23,7 @@ #include "qapi/error.h" #include "qemu/qemu-print.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" static void alpha_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 3ff8bb456d..0841eed9b0 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/alpha/helper.c b/target/alpha/helper.c index dcaa2d03ad..18acd2a8a0 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" diff --git a/target/alpha/int_helper.c b/target/alpha/int_helper.c index 5672696f6f..413fb02b1a 100644 --- a/target/alpha/int_helper.c +++ b/target/alpha/int_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 47283a0612..558ae46e67 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retaddr) diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 25f6cb8894..62de612245 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 66768ab47a..341e2854ca 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -22,7 +22,7 @@ #include "sysemu/cpus.h" #include "disas/disas.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/alpha/vax_helper.c b/target/alpha/vax_helper.c index f94fb519db..a575808cfb 100644 --- a/target/alpha/vax_helper.c +++ b/target/alpha/vax_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9555f6707b..f082f61fdf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -31,7 +31,7 @@ #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ #include "internals.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 32f3caec23..71e781c479 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -8,7 +8,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" /* Return true if the linked breakpoint entry lbn passes its checks */ diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d6a6fd73d9..78363f0912 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -28,7 +28,7 @@ #include "qemu/bitops.h" #include "internals.h" #include "qemu/crc32c.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 883ea3a4e1..e38d5131fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -20,7 +20,7 @@ #include "qemu/bitops.h" #include "qemu/crc32c.h" #include "qemu/qemu-print.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include /* For crc32 */ #include "hw/irq.h" #include "semihosting/semihost.h" diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 648a3b3fc1..aa98f6d868 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -20,7 +20,7 @@ #include "qemu/crc32c.h" #include "qemu/qemu-print.h" #include "qemu/log.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include /* For crc32 */ #include "semihosting/semihost.h" #include "sysemu/cpus.h" diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d11a8c70d0..06d661632d 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 846962bf4c..637c760881 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -23,7 +23,7 @@ #include "vec_internal.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 70b42b55fd..a7a70ae5f6 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #define SIGNBIT (uint32_t)0x80000000 diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index cd6df18150..1ad474ffe1 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 07be55b7e1..33d257bdac 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index b79004e0cc..ae4d05f910 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" static inline uint32_t merge_syn_data_abort(uint32_t template_syn, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5a1df25f91..4d43cc6f19 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/log.h" diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4267d43cc7..b8df82d6b9 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 3854dd3516..acea38a2fc 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -23,7 +23,7 @@ #include "qemu/osdep.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 33ca1bcfac..70e18c225c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 17f796e32a..ad908b8690 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -23,7 +23,7 @@ #include "qemu/osdep.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/translate.c b/target/arm/translate.c index bf2196b9e2..e375919ac7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -23,7 +23,7 @@ #include "cpu.h" #include "internals.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/log.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d70e34dd5..9dfd48b108 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/qemu-print.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "cpu.h" #include "disas/dis-asm.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index c27f702901..ad5e0d9545 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" diff --git a/target/avr/translate.c b/target/avr/translate.c index af8a3e0f9c..1ef6341915 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -22,7 +22,7 @@ #include "qemu/qemu-print.h" #include "tcg/tcg.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/cris/helper.c b/target/cris/helper.c index 91e4aeb178..bdd0c89240 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -25,6 +25,7 @@ #include "mmu.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/cris/mmu.c b/target/cris/mmu.c index b574ec6e5b..501910fddf 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "mmu.h" #ifdef DEBUG diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index d55a18a213..5e16831550 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" //#define CRIS_OP_HELPER_DEBUG diff --git a/target/cris/translate.c b/target/cris/translate.c index 3656cd6db1..1a81ec3c4e 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -26,7 +26,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "mmu.h" diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fa9bd702d6..e3e88e101f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -19,7 +19,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qapi/error.h" #include "hw/qdev-properties.h" #include "fpu/softfloat-helpers.h" diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 057baf9a48..c71d1edc7f 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5f46ba801e..07797b7afd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "qemu/module.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "fpu/softfloat.h" diff --git a/target/hppa/helper.c b/target/hppa/helper.c index e2758d8df3..77d6e98fd0 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "fpu/softfloat.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 5046cc8f9d..286d699ce1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" #include "trace.h" diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 2810361be0..f2e4a8fb8c 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "qemu/timer.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5c0b1eb274..a2c71df793 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "disas/disas.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 0639aea11b..6c93f4412d 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,6 +21,7 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY diff --git a/target/i386/machine.c b/target/i386/machine.c index 6202f47793..f6c9e86661 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "hw/isa/isa.h" #include "migration/cpu.h" #include "kvm/hyperv.h" diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index bdae887d0a..16af80a935 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/log.h" #include "sysemu/runstate.h" #include "exec/helper-proto.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index cdd8e9f947..d957a0bc4e 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,6 +21,8 @@ #include #include "cpu.h" #include "tcg-cpu.h" +#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 0a4401e917..55a49fb074 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -20,7 +20,7 @@ #ifndef I386_HELPER_TCG_H #define I386_HELPER_TCG_H -#include "exec/exec-all.h" +#include "exec/translate-all.h" /* Maximum instruction code size */ #define TARGET_MAX_INSN_SIZE 16 diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index 599ac968b0..841c2a1f47 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "qapi/error.h" diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e3cdafd2d4..8f6e19b4bd 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 24a0eaa3d5..57dcd7ec04 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "helper-tcg.h" /* diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index 22423eedcd..dc6156ada8 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "helper-tcg.h" diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index baa905a0cd..1e9df14863 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "helper-tcg.h" diff --git a/target/i386/tcg/sysemu/bpt_helper.c b/target/i386/tcg/sysemu/bpt_helper.c index 4d96a48a3c..ccd4ff0dfd 100644 --- a/target/i386/tcg/sysemu/bpt_helper.c +++ b/target/i386/tcg/sysemu/bpt_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "tcg/helper-tcg.h" diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 2b6f450af9..78cdd1eb96 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 77878cd832..d590306d82 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -21,7 +21,7 @@ #include "qemu/host-utils.h" #include "cpu.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/translator.h" diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp_helper.c index cd507e2a1b..a70c1b08b3 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/helper-tcg.h" void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_helper.c index 67481b0aa8..86d303ff0a 100644 --- a/target/i386/tcg/user/seg_helper.c +++ b/target/i386/tcg/user/seg_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" #include "tcg/seg_helper.h" diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index fdc4937e29..c36d4dd569 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "softfloat.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 5728e48585..820e3d54e3 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 8decc61240..8bd094af31 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "semihosting/semihost.h" diff --git a/target/m68k/translate.c b/target/m68k/translate.c index af43c8eab8..d28dda58c8 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index aed200dcff..3302fe38b5 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -27,7 +27,7 @@ #include "cpu.h" #include "qemu/module.h" #include "hw/qdev-properties.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "fpu/softfloat-helpers.h" static const struct { diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a607fe68e5..d3760ff32d 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/host-utils.h" #include "exec/log.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 75651979a9..c2e8a0f9d6 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" static unsigned int tlb_decode_size(unsigned int f) { diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5b745d0928..1215545333 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2561b904b9..22d7338824 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4aae23934b..7ebe31e4e1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -28,7 +28,7 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "sysemu/qtest.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" #include "semihosting/semihost.h" diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c index bae37f515b..00cdf0cbc2 100644 --- a/target/mips/sysemu/cp0.c +++ b/target/mips/sysemu/cp0.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" /* Called for updates to CP0_Status. */ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 1918633aa1..22f70c845d 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "../internal.h" static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 0b21e0872b..040e20b5c6 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -24,6 +24,7 @@ #include "internal.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" target_ulong exception_resume_pc(CPUMIPSState *env) { diff --git a/target/mips/tcg/fpu_helper.c b/target/mips/tcg/fpu_helper.c index 8ce56ed7c8..9a2658e6b0 100644 --- a/target/mips/tcg/fpu_helper.c +++ b/target/mips/tcg/fpu_helper.c @@ -24,7 +24,7 @@ #include "cpu.h" #include "internal.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu_helper.h" diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index d0bd0267b2..18fd868a2d 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -23,7 +23,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/memop.h" #include "internal.h" diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 5667b1f0a1..2bb33c4e62 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "internal.h" #include "tcg/tcg.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "exec/memop.h" #include "fpu/softfloat.h" diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index ef3dafcbb3..a57cd74409 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "internal.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/memop.h" #include "fpu_helper.h" diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index aae2af6ecc..37ae357636 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -28,6 +28,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" /* SMP helpers. */ diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c index f4f8fe8afc..8699b489de 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -22,7 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "internal.h" /* Specials */ diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 73254d1929..10ed2a5987 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e5c98650e1..518c8e83a5 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 2545c06761..8746d53a52 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "mmu.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a59003855a..0e45724a42 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/main-loop.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f9abc2fdd2..6f2aff796e 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -24,7 +24,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "tcg/tcg-op.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/openrisc/exception.c b/target/openrisc/exception.c index 28c1fce523..c752d84a2a 100644 --- a/target/openrisc/exception.c +++ b/target/openrisc/exception.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exception.h" void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception_helper.c index d02a1cf0aa..f87dbd50a1 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "exception.h" diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index e5724f5371..cddc17b780 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" #ifndef CONFIG_USER_ONLY diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index ab4ea88b69..bcc8607e52 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" void HELPER(rfe)(CPUOpenRISCState *env) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index d7e1320998..2078667508 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" #include "hw/loader.h" diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 48674231e7..b3b3519c10 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ca79e609da..5db817b897 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "disas/disas.h" #include "tcg/tcg-op.h" #include "qemu/log.h" diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index cbac63d53c..89c61f8fd6 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "internal.h" #include "helper_regs.h" diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index e5c29b53b8..b8f3af97e7 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "internal.h" #include "fpu/softfloat.h" diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 5b12cb03c9..07e61c5266 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "sysemu/kvm.h" #include "helper_regs.h" #include "power8-pmu.h" diff --git a/target/ppc/machine.c b/target/ppc/machine.c index a503e00ddc..81db34dc9b 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "sysemu/kvm.h" #include "helper_regs.h" #include "mmu-hash64.h" diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 39945d9ea5..e924586390 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "exec/helper-proto.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 129432be01..6742c98ae7 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 3957aab2dc..c4ee7068ba 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" #include "internal.h" diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index da9fe99ff8..2a22777d8c 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 040c055bff..a3bdb8ea4a 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 6512ee031c..f9392c0399 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -24,7 +24,7 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "mmu-hash32.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index a2a52a12c3..e52de17223 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -25,6 +25,7 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 236e8e66e9..8f8132b233 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "helper_regs.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index af378318c1..2193550956 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/log.h" #include "qemu/main-loop.h" diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2f436f8d3..d862256f25 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "internal.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/host-utils.h" diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 7ff76f7a06..3c21f8c637 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "internal.h" void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index f1b5e5549f..6fd7b53010 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "tcg/tcg.h" diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1cb0436187..be9458e83f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,7 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 327a2c4f1d..20bf62e8ea 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 45f04c701a..1815d4ee91 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "sysemu/cpu-timers.h" /* CSR function table public API */ diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 4a5982d594..cff7363f5b 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "internals.h" diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c index 7bf115b85e..86e7114f38 100644 --- a/target/riscv/m128_helper.c +++ b/target/riscv/m128_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" target_ulong HELPER(divu_i128)(CPURISCVState *env, diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1a75ba11e6..bad53d6c87 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" /* Exceptions processing helpers */ diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 81b61bb65c..0b5f23aaa5 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "trace.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0bbe80875..cdfc102de3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -22,7 +22,7 @@ #include "tcg/tcg-op.h" #include "disas/disas.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 020d2e841f..327b79f35d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -21,7 +21,7 @@ #include "qemu/bitops.h" #include "cpu.h" #include "exec/memop.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 25a4aa2976..da5f8e1d2c 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -23,6 +23,7 @@ #include "qemu-common.h" #include "migration/vmstate.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "hw/loader.h" #include "fpu/softfloat.h" diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 11f952d340..41f343111d 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" diff --git a/target/rx/translate.c b/target/rx/translate.c index 5db8f79a82..3a585a3214 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -20,7 +20,7 @@ #include "qemu/bswap.h" #include "qemu/qemu-print.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index a5d69d0e0b..ae3a9bacb6 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "s390x-internal.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gdbstub.h" #include "qemu/bitops.h" #include "sysemu/hw_accel.h" diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index 5195f060ec..6936114911 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -11,7 +11,7 @@ #include "cpu.h" #include "kvm/kvm_s390x.h" #include "s390x-internal.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "hw/s390x/ioinst.h" diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index b04b57c235..fcd98811d6 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -24,6 +24,7 @@ #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "trace.h" #include "hw/hw.h" #include "hw/s390x/storage-keys.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index 9dd977349a..08af079f04 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -15,6 +15,7 @@ #include "sysemu/runstate.h" #include "exec/address-spaces.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "sysemu/tcg.h" #include "trace.h" #include "qapi/qapi-types-machine.h" diff --git a/target/s390x/tcg/cc_helper.c b/target/s390x/tcg/cc_helper.c index 8d04097f78..5eb95c2254 100644 --- a/target/s390x/tcg/cc_helper.c +++ b/target/s390x/tcg/cc_helper.c @@ -23,6 +23,7 @@ #include "s390x-internal.h" #include "tcg_s390x.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_helper.c index 138d9e7ad9..f45a0db5d7 100644 --- a/target/s390x/tcg/crypto_helper.c +++ b/target/s390x/tcg/crypto_helper.c @@ -15,7 +15,7 @@ #include "s390x-internal.h" #include "tcg_s390x.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" uint32_t HELPER(msa)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t r3, diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index be6c966cfa..967e6544dc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -25,6 +25,7 @@ #include "exec/helper-proto.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "hw/s390x/ioinst.h" #include "exec/address-spaces.h" diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 4067205405..ff97a3cfc5 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "s390x-internal.h" #include "tcg_s390x.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 954542388a..490ae6814b 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "s390x-internal.h" #include "tcg_s390x.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index b5523ef3c7..8b97790e3c 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index aab9c47747..0fe6147b5d 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -28,6 +28,7 @@ #include "exec/helper-proto.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 46dea73357..8430775171 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -32,7 +32,7 @@ #include "cpu.h" #include "s390x-internal.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/log.h" diff --git a/target/s390x/tcg/vec_fpu_helper.c b/target/s390x/tcg/vec_fpu_helper.c index 1a77993471..561407bd95 100644 --- a/target/s390x/tcg/vec_fpu_helper.c +++ b/target/s390x/tcg/vec_fpu_helper.c @@ -16,7 +16,7 @@ #include "vec.h" #include "tcg_s390x.h" #include "tcg/tcg-gvec-desc.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index ededf13cf0..405f593889 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -17,7 +17,7 @@ #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3, uint32_t desc) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 06b2691dc4..c2a1da2730 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -24,7 +24,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "migration/vmstate.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "fpu/softfloat-helpers.h" static void superh_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 6a620e36fc..af02fae0af 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/log.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 752669825f..7d7ec41f5a 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 43bc88b7b3..a4f0e838c3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -22,7 +22,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 55268ed2a1..54cbca84e5 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "qemu/module.h" #include "qemu/qemu-print.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "hw/qdev-properties.h" #include "qapi/visitor.h" diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index f54fa9b959..64b56b9a40 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/sparc/helper.c b/target/sparc/helper.c index c4358bba84..ab971a64d0 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/timer.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index ec4fae78c3..4598b70f4f 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "asi.h" diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 44b9e7d75d..1370ba6b1d 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/timer.h" #include "migration/cpu.h" diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 346a6dfa35..f04504a20b 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/qemu-print.h" #include "trace.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4c7c7b5347..216b2a4168 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -23,7 +23,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c index 3a7c0ff943..9d1e7fc387 100644 --- a/target/sparc/win_helper.c +++ b/target/sparc/win_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "trace.h" diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f0..c5cc8a0707 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "qemu/error-report.h" static inline void set_feature(CPUTriCoreState *env, int feature) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 1db32808e8..8a235ea502 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -19,6 +19,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 9476d10d00..f7d3026266 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include /* for crc32 */ diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 417edbd3f0..4a967d1e9a 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index ce2a820c60..25f203d3a8 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -31,7 +31,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/address-spaces.h" static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index d4823a65cd..3e96c440fc 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -32,6 +32,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index d2a10cc797..6d2f0a2e17 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -31,7 +31,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "fpu/softfloat.h" enum { diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index e0a9caab4b..d1899226c2 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -29,6 +29,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index fa66e8e867..3be1f3a649 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -34,6 +34,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #define XTENSA_MPU_SEGMENT_MASK 0x0000001f diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index d85d3516d6..fc03f2f624 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -30,7 +30,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/cpu_ldst.h" #include "qemu/timer.h" diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index b1491ed625..4f3bca77ba 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -31,7 +31,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "disas/disas.h" #include "tcg/tcg-op.h" #include "qemu/log.h" diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c index 5a1555360a..368f983731 100644 --- a/target/xtensa/win_helper.c +++ b/target/xtensa/win_helper.c @@ -31,7 +31,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" static void copy_window_from_phys(CPUXtensaState *env, uint32_t window, uint32_t phys, uint32_t n) diff --git a/tcg/region.c b/tcg/region.c index 9cc30d4922..b970d7cdda 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 61b492d89f..90098cef71 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -23,7 +23,7 @@ */ #include "qemu/osdep.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 5d2f0d8b10..0c33c2e578 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -42,7 +42,7 @@ instructions */ #define NO_CPU_IO_DEFS -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "tcg/tcg-op.h" #if UINTPTR_MAX == UINT32_MAX