From patchwork Wed Feb 9 08:49:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12740181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F1B9C433F5 for ; Wed, 9 Feb 2022 11:59:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229732AbiBIL7A (ORCPT ); Wed, 9 Feb 2022 06:59:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231452AbiBIL5w (ORCPT ); Wed, 9 Feb 2022 06:57:52 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36491E00FED8; Wed, 9 Feb 2022 03:00:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644404429; x=1675940429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BRMP6Uo4uFbPv2FKo1aqyoKoVbyJUj8pdBISKbB0UIU=; b=Qu8WFE0elgPxYW8h6dTZY6XvqQnPkDirDJjgBE52FqenZGYfwwGlZqt0 YXzm5sEmdAkGFjJk470ifmiAq5h1Riqnxvb1/O+nUG0R6wVtEw6cTOsA3 4K9zy2W3H7ekDn2qrAt1GOYSYahqosWOTA6tDF9cDqY2H/2Kr3X22YxG7 4EzhUfrlLoqGDHiBbPb298mWGTQWxV4eml8bTS2uV7DINl6KgoPwfALr+ S0rx2p95I+t6eP337i1DMHB1PKJ90htsxPbV5MnDlNJs8Av8WourmAfNK PgRlohKpqhv2MNbIuPRtnejBkE/gFe8f3JwrA4FJ334xo+f7uqR6d/07g A==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="247992184" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="247992184" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:49:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169190" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:49:34 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 01/11] perf/x86: Fix native_perf_sched_clock_from_tsc() with __sched_clock_offset Date: Wed, 9 Feb 2022 10:49:19 +0200 Message-Id: <20220209084929.54331-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org native_perf_sched_clock_from_tsc() is used to produce a time value that can be consistent with perf_clock(). Consequently, it should be adjusted by __sched_clock_offset, the same as perf_clock() would be. Fixes: 698eff6355f735 ("sched/clock, x86/perf: Fix perf test tsc") Signed-off-by: Adrian Hunter --- arch/x86/kernel/tsc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a698196377be..c1c73fe324cd 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -242,7 +242,8 @@ u64 native_sched_clock(void) */ u64 native_sched_clock_from_tsc(u64 tsc) { - return cycles_2_ns(tsc); + return cycles_2_ns(tsc) + + (sched_clock_stable() ? __sched_clock_offset : 0); } /* We need to define a real function for sched_clock, to override the From patchwork Wed Feb 9 08:49:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12740165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51A0BC433FE for ; Wed, 9 Feb 2022 11:58:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231646AbiBIL57 (ORCPT ); Wed, 9 Feb 2022 06:57:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230081AbiBIL5K (ORCPT ); Wed, 9 Feb 2022 06:57:10 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CC13E03E22B; Wed, 9 Feb 2022 02:56:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644404200; x=1675940200; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UjE7mw19dKJDom0MhaIR0CBU7W0myMKVcMbKBeE/xDk=; b=LPHxBdeRsVsHIsNSq0c5Gh+z07PzXfK7N39AsS20LC1tjjEboHT68eRa pdr8uQoXr66uAjYZjunamBTgjgeAswTWxWWXKnIe/DmkddDbuTyh1bmAy YZqUGQAUv8t8Upon7UcSsNJj1oIAMuB0MorMiXTXsdf4Qz6o3M6+JlVV8 /bHjQAPDoevn+oruEZmaWA955MAZbhJNjohS1cV8lZOUkoY42OX8qwa5k cF4UaaVay1x6NGg/RQ6VwPns39vdnjdTZlQqOuzH/18yqRlbJx1HYzGmf 1LNjjkKsW0aTnGejfKv5w0X2eRVHYi/erlR7iKJYrxYH5Y5nmckqmy5ur Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="229128582" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="229128582" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:49:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169205" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:49:38 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 02/11] perf/x86: Add support for TSC as a perf event clock Date: Wed, 9 Feb 2022 10:49:20 +0200 Message-Id: <20220209084929.54331-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, using Intel PT to trace a VM guest is limited to kernel space because decoding requires side band events such as MMAP and CONTEXT_SWITCH. While these events can be collected for the host, there is not a way to do that yet for a guest. One approach, would be to collect them inside the guest, but that would require being able to synchronize with host timestamps. The motivation for this patch is to provide a clock that can be used within a VM guest, and that correlates to a VM host clock. In the case of TSC, if the hypervisor leaves rdtsc alone, the TSC value will be subject only to the VMCS TSC Offset and Scaling. Adjusting for that would make it possible to inject events from a guest perf.data file, into a host perf.data file. Thus making possible the collection of VM guest side band for Intel PT decoding. There are other potential benefits of TSC as a perf event clock: - ability to work directly with TSC - ability to inject non-Intel-PT-related events from a guest Signed-off-by: Adrian Hunter --- arch/x86/events/core.c | 14 ++++++++++++++ arch/x86/include/asm/perf_event.h | 3 +++ include/uapi/linux/perf_event.h | 8 ++++++++ kernel/events/core.c | 7 +++++++ 4 files changed, 32 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e686c5e0537b..e2ad3f9cca93 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2728,6 +2728,15 @@ void arch_perf_update_userpage(struct perf_event *event, !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); userpg->pmc_width = x86_pmu.cntval_bits; + if (event->attr.use_clockid && event->attr.clockid == CLOCK_PERF_HW_CLOCK) { + userpg->cap_user_time_zero = 1; + userpg->time_mult = 1; + userpg->time_shift = 0; + userpg->time_offset = 0; + userpg->time_zero = 0; + return; + } + if (!using_native_sched_clock() || !sched_clock_stable()) return; @@ -2980,6 +2989,11 @@ unsigned long perf_misc_flags(struct pt_regs *regs) return misc; } +u64 perf_hw_clock(void) +{ + return rdtsc_ordered(); +} + void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) { cap->version = x86_pmu.version; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 58d9e4b1fa0a..5288ea1ae2ba 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -451,6 +451,9 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs); extern unsigned long perf_misc_flags(struct pt_regs *regs); #define perf_misc_flags(regs) perf_misc_flags(regs) +extern u64 perf_hw_clock(void); +#define perf_hw_clock perf_hw_clock + #include /* diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 82858b697c05..150d2b70a41f 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -290,6 +290,14 @@ enum { PERF_TXN_ABORT_SHIFT = 32, }; +/* + * If supported, clockid value to select an architecture dependent hardware + * clock. Note this means the unit of time is ticks not nanoseconds. + * On x86, this is provided by the rdtsc instruction, and is not + * paravirtualized. + */ +#define CLOCK_PERF_HW_CLOCK 0x10000000 + /* * The format of the data returned by read() on a perf event fd, * as specified by attr.read_format: diff --git a/kernel/events/core.c b/kernel/events/core.c index 57249f37c37d..aab78f033711 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -12035,6 +12035,13 @@ static int perf_event_set_clock(struct perf_event *event, clockid_t clk_id) event->clock = &ktime_get_clocktai_ns; break; +#ifdef perf_hw_clock + case CLOCK_PERF_HW_CLOCK: + event->clock = &perf_hw_clock; + nmi_safe = true; + break; +#endif + default: return -EINVAL; } From patchwork Wed Feb 9 08:49:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12740164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2FBFC433FE for ; Wed, 9 Feb 2022 11:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231623AbiBIL5z (ORCPT ); Wed, 9 Feb 2022 06:57:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231379AbiBIL5O (ORCPT ); Wed, 9 Feb 2022 06:57:14 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ED0FE03E22C; Wed, 9 Feb 2022 02:56:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644404200; x=1675940200; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=29bl/kV2j4h8E0ChTQ4IHW+W/ZMcObLTcVjx5zQdF58=; b=XgbQSWNLzQvn087joWXSrmyV9b/af5rSOO1tndZgV0OnhnG/ZHGmW4cx Emldo7VOiBVZUnoHeDN4Wkk/8I1HqbeB4nyYqK3RzgD58ZJECKUbCSe/Q Bcgz6A+3nRb9wmNjvosvrGg0yci20mXhbSMG6X2vTBVbFpLXubCc3SLTM m+MZWXW2I8TXtzY3r4v1wsKeXhsQZRSzcXsryaVZi17xHI4RLtDSmF8H4 UeMTgTrh2QPuBwzecmxR5rIOdU3EpZnq2gcLdWKhTuW9sz16x2ViynZGC 4P3kVpy04XwUhm4eEsznFjGu4ArhUumknjPAV5tWoEMNnLgXMJmkodkiV g==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="229128583" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="229128583" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:49:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169215" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:49:43 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock Date: Wed, 9 Feb 2022 10:49:21 +0200 Message-Id: <20220209084929.54331-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, when Intel PT is used within a VM guest, it is not possible to make use of TSC because perf clock is subject to paravirtualization. If the hypervisor leaves rdtsc alone, the TSC value will be subject only to the VMCS TSC Offset and Scaling, the same as the TSC packet from Intel PT. The new clock is based on rdtsc and not subject to paravirtualization. Hence it would be possible to use this new clock for Intel PT decoding within a VM guest. Signed-off-by: Adrian Hunter --- arch/x86/events/core.c | 43 +++++++++++++++++++++---------- arch/x86/include/asm/perf_event.h | 2 ++ include/uapi/linux/perf_event.h | 6 +++++ kernel/events/core.c | 6 +++++ 4 files changed, 43 insertions(+), 14 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e2ad3f9cca93..e81374f0ccaa 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "perf_event.h" @@ -2728,39 +2729,48 @@ void arch_perf_update_userpage(struct perf_event *event, !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); userpg->pmc_width = x86_pmu.cntval_bits; - if (event->attr.use_clockid && event->attr.clockid == CLOCK_PERF_HW_CLOCK) { - userpg->cap_user_time_zero = 1; - userpg->time_mult = 1; - userpg->time_shift = 0; - userpg->time_offset = 0; - userpg->time_zero = 0; - return; + if (event->attr.use_clockid) { + if (event->attr.clockid == CLOCK_PERF_HW_CLOCK) { + userpg->cap_user_time_zero = 1; + userpg->time_mult = 1; + userpg->time_shift = 0; + userpg->time_offset = 0; + userpg->time_zero = 0; + return; + } + if (event->attr.clockid == CLOCK_PERF_HW_CLOCK_NS) + userpg->cap_user_time_zero = 1; + } + + userpg->cap_user_time = using_native_sched_clock(); + if (sched_clock_stable()) { + offset = __sched_clock_offset; + } else { + offset = 0; + userpg->cap_user_time = 0; } - if (!using_native_sched_clock() || !sched_clock_stable()) + if (!userpg->cap_user_time && !userpg->cap_user_time_zero) return; cyc2ns_read_begin(&data); - offset = data.cyc2ns_offset + __sched_clock_offset; + offset += data.cyc2ns_offset; /* * Internal timekeeping for enabled/running/stopped times * is always in the local_clock domain. */ - userpg->cap_user_time = 1; userpg->time_mult = data.cyc2ns_mul; userpg->time_shift = data.cyc2ns_shift; userpg->time_offset = offset - now; /* * cap_user_time_zero doesn't make sense when we're using a different - * time base for the records. + * time base for the records, except for CLOCK_PERF_HW_CLOCK_NS. */ - if (!event->attr.use_clockid) { - userpg->cap_user_time_zero = 1; + if (userpg->cap_user_time_zero) userpg->time_zero = offset; - } cyc2ns_read_end(); } @@ -2994,6 +3004,11 @@ u64 perf_hw_clock(void) return rdtsc_ordered(); } +u64 perf_hw_clock_ns(void) +{ + return native_sched_clock_from_tsc(perf_hw_clock()); +} + void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) { cap->version = x86_pmu.version; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 5288ea1ae2ba..46cbca90cdd1 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -453,6 +453,8 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); extern u64 perf_hw_clock(void); #define perf_hw_clock perf_hw_clock +extern u64 perf_hw_clock_ns(void); +#define perf_hw_clock_ns perf_hw_clock_ns #include diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 150d2b70a41f..28d5d6a7d89f 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -297,6 +297,12 @@ enum { * paravirtualized. */ #define CLOCK_PERF_HW_CLOCK 0x10000000 +/* + * Same as CLOCK_PERF_HW_CLOCK but in nanoseconds. Note support of + * CLOCK_PERF_HW_CLOCK_NS does not necesssarily imply support of + * CLOCK_PERF_HW_CLOCK or vice versa. + */ +#define CLOCK_PERF_HW_CLOCK_NS 0x10000001 /* * The format of the data returned by read() on a perf event fd, diff --git a/kernel/events/core.c b/kernel/events/core.c index aab78f033711..d048f8aae0a6 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -12041,6 +12041,12 @@ static int perf_event_set_clock(struct perf_event *event, clockid_t clk_id) nmi_safe = true; break; #endif +#ifdef perf_hw_clock_ns + case CLOCK_PERF_HW_CLOCK_NS: + event->clock = &perf_hw_clock_ns; + nmi_safe = true; + break; +#endif default: return -EINVAL; From patchwork Wed Feb 9 08:49:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12740162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D510C433EF for ; Wed, 9 Feb 2022 11:57:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbiBIL5s (ORCPT ); Wed, 9 Feb 2022 06:57:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231393AbiBIL5O (ORCPT ); Wed, 9 Feb 2022 06:57:14 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91E57E03E22D; Wed, 9 Feb 2022 02:56:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644404201; x=1675940201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hPtON+dDWCgD9fpDPWm80v7glxOinJzDbnNHVr6cmo0=; b=IZ1MlJpeORJ9YzOnPhdf+xSZmLa3+rGSWXvYgXHsyA5kkAExXEzzqmiQ r2WW8rStIBP+X9HdgBbRF4gkWArgEJ4UPxrcq2kNbZSQq0NfHki72q0qP c7NipfN+1Fu917ofuOn1TKHcP8wngwtQNsnM1/Lhxhs9ZGXPwmdgTVkuH POVRfAIw1A3srVecIWduNp5pqfgfCS9TodNfuOaPDKaGCTD7WTjXtt+fh XAbB3nnEvLFLaSJ1+qmiFWaGhyx9yVLeJ97CF7XZ9MgP8ZwtW4Y1bj/Np 8YjEUMP27SOMZ3m25J8pjmsqJ/zXm2Eyl8pOjXNIyF6ZSj45Bfn0/Nd9Z g==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="229128607" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="229128607" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:49:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169243" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:49:47 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 04/11] perf tools: Add new perf clock IDs Date: Wed, 9 Feb 2022 10:49:22 +0200 Message-Id: <20220209084929.54331-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add support for new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. Signed-off-by: Adrian Hunter --- tools/include/uapi/linux/perf_event.h | 14 ++++++++++++++ tools/perf/Documentation/perf-record.txt | 9 ++++++++- tools/perf/builtin-record.c | 2 +- tools/perf/util/clockid.c | 5 +++++ 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index 1b65042ab1db..9fbb2eddd2ca 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -290,6 +290,20 @@ enum { PERF_TXN_ABORT_SHIFT = 32, }; +/* + * If supported, clockid value to select an architecture dependent hardware + * clock. Note this means the unit of time is ticks not nanoseconds. + * On x86, this is provided by the rdtsc instruction, and is not + * paravirtualized. + */ +#define CLOCK_PERF_HW_CLOCK 0x10000000 +/* + * Same as CLOCK_PERF_HW_CLOCK but in nanoseconds. Note support of + * CLOCK_PERF_HW_CLOCK_NS does not necesssarily imply support of + * CLOCK_PERF_HW_CLOCK or vice versa. + */ +#define CLOCK_PERF_HW_CLOCK_NS 0x10000001 + /* * The format of the data returned by read() on a perf event fd, * as specified by attr.read_format: diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index 9ccc75935bc5..a5ef4813093a 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -444,7 +444,14 @@ Record running and enabled time for read events (:S) Sets the clock id to use for the various time fields in the perf_event_type records. See clock_gettime(). In particular CLOCK_MONOTONIC and CLOCK_MONOTONIC_RAW are supported, some events might also allow -CLOCK_BOOTTIME, CLOCK_REALTIME and CLOCK_TAI. +CLOCK_BOOTTIME, CLOCK_REALTIME and CLOCK_TAI. In addition, the kernel might +support CLOCK_PERF_HW_CLOCK to select an architecture dependent hardware +clock, for which the unit of time is ticks not nanoseconds. On x86, +CLOCK_PERF_HW_CLOCK is provided by the rdtsc instruction, and is not +paravirtualized. There is also CLOCK_PERF_HW_CLOCK_NS which is the same as +CLOCK_PERF_HW_CLOCK, but converted to nanoseconds. Note support of +CLOCK_PERF_HW_CLOCK_NS does not necessarily imply support of +CLOCK_PERF_HW_CLOCK or vice versa. -S:: --snapshot:: diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index bb716c953d02..52eaffa0b77f 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -1553,7 +1553,7 @@ static int record__init_clock(struct record *rec) struct timeval ref_tod; u64 ref; - if (!rec->opts.use_clockid) + if (!rec->opts.use_clockid || rec->opts.clockid >= CLOCK_PERF_HW_CLOCK) return 0; if (rec->opts.use_clockid && rec->opts.clockid_res_ns) diff --git a/tools/perf/util/clockid.c b/tools/perf/util/clockid.c index 74365a5d99c1..380429725df1 100644 --- a/tools/perf/util/clockid.c +++ b/tools/perf/util/clockid.c @@ -49,6 +49,9 @@ static const struct clockid_map clockids[] = { CLOCKID_MAP("real", CLOCK_REALTIME), CLOCKID_MAP("boot", CLOCK_BOOTTIME), + CLOCKID_MAP("perf_hw_clock", CLOCK_PERF_HW_CLOCK), + CLOCKID_MAP("perf_hw_clock_ns", CLOCK_PERF_HW_CLOCK_NS), + CLOCKID_END, }; @@ -57,6 +60,8 @@ static int get_clockid_res(clockid_t clk_id, u64 *res_ns) struct timespec res; *res_ns = 0; + if (clk_id >= CLOCK_PERF_HW_CLOCK) + return 0; if (!clock_getres(clk_id, &res)) *res_ns = res.tv_nsec + res.tv_sec * NSEC_PER_SEC; else From patchwork Wed Feb 9 08:49:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12740163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B0CCC433EF for ; Wed, 9 Feb 2022 11:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231577AbiBIL5w (ORCPT ); Wed, 9 Feb 2022 06:57:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231395AbiBIL5Q (ORCPT ); Wed, 9 Feb 2022 06:57:16 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93F93E03E22E; Wed, 9 Feb 2022 02:56:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644404201; x=1675940201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FR54Ul9wkB7B9HE0EPdcDIwgDv3R7OaEomUk2L58kKs=; b=SuCxVL6ARdvgevReo3mhA5gGUxuJrChPbJucIXADMbz+qhEm2BL+V6/L mrq5zS3Ymu1b77+oGyhlnrmX8BvlHnWjcElct36fGQPDt85PVBrRBuzro X7k2cejKvsU/n+yT7ApdWA+T0AMmCWwJMAjb37FL/B2xiTj1lroiy/zPw TiSoJXh/MgLgVSIezXojK07RBKaPNUGAZ3Ya413s/4BdBOXSF2+hsBkM3 8ouLCKhKKdfFMVskoTEkEnRXCs/MtCnyp3ZnXV3sbSYPGcepsKQfYQd+P xlsLnEJZPn+vehed4TptaPDCyMfNVGUIMpI09/JjNMmr0WGYmJPBkka2B A==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="229128626" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="229128626" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:49:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169257" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:49:51 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 05/11] perf tools: Add API probes for new clock IDs Date: Wed, 9 Feb 2022 10:49:23 +0200 Message-Id: <20220209084929.54331-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add ability to check whether the kernel supports new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. They will be used in a subsequent patch. Signed-off-by: Adrian Hunter --- tools/perf/util/perf_api_probe.c | 22 ++++++++++++++++++++++ tools/perf/util/perf_api_probe.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/tools/perf/util/perf_api_probe.c b/tools/perf/util/perf_api_probe.c index c28dd50bd571..c70af544a08c 100644 --- a/tools/perf/util/perf_api_probe.c +++ b/tools/perf/util/perf_api_probe.c @@ -109,6 +109,18 @@ static void perf_probe_cgroup(struct evsel *evsel) evsel->core.attr.cgroup = 1; } +static void perf_probe_hw_clock(struct evsel *evsel) +{ + evsel->core.attr.use_clockid = 1; + evsel->core.attr.clockid = CLOCK_PERF_HW_CLOCK; +} + +static void perf_probe_hw_clock_ns(struct evsel *evsel) +{ + evsel->core.attr.use_clockid = 1; + evsel->core.attr.clockid = CLOCK_PERF_HW_CLOCK_NS; +} + bool perf_can_sample_identifier(void) { return perf_probe_api(perf_probe_sample_identifier); @@ -195,3 +207,13 @@ bool perf_can_record_cgroup(void) { return perf_probe_api(perf_probe_cgroup); } + +bool perf_can_perf_clock_hw_clock(void) +{ + return perf_probe_api(perf_probe_hw_clock); +} + +bool perf_can_perf_clock_hw_clock_ns(void) +{ + return perf_probe_api(perf_probe_hw_clock_ns); +} diff --git a/tools/perf/util/perf_api_probe.h b/tools/perf/util/perf_api_probe.h index b104168efb15..5b30cbd260cf 100644 --- a/tools/perf/util/perf_api_probe.h +++ b/tools/perf/util/perf_api_probe.h @@ -13,5 +13,7 @@ bool perf_can_record_text_poke_events(void); bool perf_can_sample_identifier(void); bool perf_can_record_build_id(void); bool perf_can_record_cgroup(void); +bool perf_can_perf_clock_hw_clock(void); +bool perf_can_perf_clock_hw_clock_ns(void); #endif // __PERF_API_PROBE_H From patchwork Wed Feb 9 08:49:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12739832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 959AFC433FE for ; Wed, 9 Feb 2022 08:52:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238415AbiBIIwt (ORCPT ); Wed, 9 Feb 2022 03:52:49 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:42576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236979AbiBIIwk (ORCPT ); Wed, 9 Feb 2022 03:52:40 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AD80C02B647; Wed, 9 Feb 2022 00:52:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644396755; x=1675932755; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N2F7TIMJv5p51QRiR0PjjnEjpwG2HqCv0tEcgH5DpDc=; b=XmQZnbI9NCnkero63LeDNizVfBy+u4vP/Cs2j3IAWhrzuxDf9tKoVW6l F6qBPBtkx/ypZAk6y85orFrBZyP0Nm5VdsyouB0iyEYVZAm4wj5Nv0Diq v6jpuRy2QoLPWnM+VGjEBdjSWg6x7LApS50caYUc8xCc5UDLwmyGeVAeI mr7rw3l7RCZZfqjm2yqKxRDdIHhQ1b9PJBKLSS59zaNzrdLMa6AsrQ0+z yy90tlsxeewCqFXVyRvhhWvgPHaEGpJu1y8EJ1BNBPJEJTiA4l27Bmtyr e7INHxXzmc7XWMlisTvxgGib15KEtFwxdsK0Ii4HYiOl476mzWwdeyhNW g==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="309903005" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="309903005" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:50:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169270" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:49:56 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 06/11] perf tools: Add new clock IDs to "perf time to TSC" test Date: Wed, 9 Feb 2022 10:49:24 +0200 Message-Id: <20220209084929.54331-7-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The same "Convert perf time to TSC" test can be used with new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. Signed-off-by: Adrian Hunter --- tools/perf/tests/perf-time-to-tsc.c | 41 ++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c index d12d0ad81801..1044bc4acacb 100644 --- a/tools/perf/tests/perf-time-to-tsc.c +++ b/tools/perf/tests/perf-time-to-tsc.c @@ -22,6 +22,7 @@ #include "tests.h" #include "pmu.h" #include "pmu-hybrid.h" +#include "perf_api_probe.h" /* * Except x86_64/i386 and Arm64, other archs don't support TSC in perf. Just @@ -47,15 +48,7 @@ } \ } -/** - * test__perf_time_to_tsc - test converting perf time to TSC. - * - * This function implements a test that checks that the conversion of perf time - * to and from TSC is consistent with the order of events. If the test passes - * %0 is returned, otherwise %-1 is returned. If TSC conversion is not - * supported then then the test passes but " (not supported)" is printed. - */ -static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int subtest __maybe_unused) +static int perf_time_to_tsc_test(bool use_clockid, s32 clockid) { struct record_opts opts = { .mmap_pages = UINT_MAX, @@ -104,6 +97,8 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su evsel->core.attr.comm = 1; evsel->core.attr.disabled = 1; evsel->core.attr.enable_on_exec = 0; + evsel->core.attr.use_clockid = use_clockid; + evsel->core.attr.clockid = clockid; /* * For hybrid "cycles:u", it creates two events. @@ -200,4 +195,32 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su return err; } +/** + * test__perf_time_to_tsc - test converting perf time to TSC. + * + * This function implements a test that checks that the conversion of perf time + * to and from TSC is consistent with the order of events. If the test passes + * %0 is returned, otherwise %-1 is returned. If TSC conversion is not + * supported then the test passes but " (not supported)" is printed. + */ +static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + int err; + + err = perf_time_to_tsc_test(false, 0); + + if (!err && perf_can_perf_clock_hw_clock()) { + pr_debug("Testing CLOCK_PERF_HW_CLOCK\n"); + err = perf_time_to_tsc_test(true, CLOCK_PERF_HW_CLOCK); + } + + if (!err && perf_can_perf_clock_hw_clock_ns()) { + pr_debug("Testing CLOCK_PERF_HW_CLOCK_NS\n"); + err = perf_time_to_tsc_test(true, CLOCK_PERF_HW_CLOCK_NS); + } + + return err; +} + DEFINE_SUITE("Convert perf time to TSC", perf_time_to_tsc); From patchwork Wed Feb 9 08:49:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12739833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAED9C433EF for ; Wed, 9 Feb 2022 08:52:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239084AbiBIIww (ORCPT ); Wed, 9 Feb 2022 03:52:52 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:43194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238823AbiBIIwv (ORCPT ); Wed, 9 Feb 2022 03:52:51 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 247E1DF48F17; Wed, 9 Feb 2022 00:52:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644396765; x=1675932765; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UvkvAiHghoxYj3prOUwWIM8u+bIgeXtt/bvpfm45/LY=; b=Xiq8amNxyLkMLnanRTAffBrNuBPe1mc0IZT9sfuZyRsaHwIoO9qc3yKT Q+0XwZW6TnCU0SY7yCcuWm1hlybeVhGx5od/s1YWNU39W1JYDf/08PfC1 zXoQyJLyasHEvIeDO/Y+CenZVi4JklRKUu1D5K+yGJUEo01R78QsBQt2Y Bk2gT5VH8MaG+iC25SkR85Apv+Gns5OqLc/p9KXMdxUkhZcdHb75RgFk7 BwKXqlehXBxi8qn8P+0yd60lB0Yi2np9LoKjzXIALSEjdyxfSIBaSp6BE qDXSZZnXt/2QwfLThu+H5QHwWFV9hHRcivcAd8cdZOdeildA4+GwMTpW5 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="309903006" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="309903006" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:50:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169321" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:50:00 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 07/11] perf tools: Add perf_read_tsc_conv_for_clockid() Date: Wed, 9 Feb 2022 10:49:25 +0200 Message-Id: <20220209084929.54331-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a function to read TSC conversion information for a particular clock ID. It will be used in a subsequent patch. Signed-off-by: Adrian Hunter --- tools/perf/util/tsc.c | 56 +++++++++++++++++++++++++++++++++++++++++++ tools/perf/util/tsc.h | 1 + 2 files changed, 57 insertions(+) diff --git a/tools/perf/util/tsc.c b/tools/perf/util/tsc.c index f19791d46e99..175a6e43ad94 100644 --- a/tools/perf/util/tsc.c +++ b/tools/perf/util/tsc.c @@ -3,6 +3,8 @@ #include #include +#include + #include #include #include @@ -14,6 +16,9 @@ #include "synthetic-events.h" #include "debug.h" #include "tsc.h" +#include "cpumap.h" +#include "perf-sys.h" +#include /* page_size */ u64 perf_time_to_tsc(u64 ns, struct perf_tsc_conversion *tc) { @@ -71,6 +76,57 @@ int perf_read_tsc_conversion(const struct perf_event_mmap_page *pc, return 0; } +static int perf_read_tsc_conv_attr_cpu(struct perf_event_attr *attr, int cpu, + struct perf_tsc_conversion *tc) +{ + size_t len = 2 * page_size; + int fd, err = -EINVAL; + void *addr; + + fd = sys_perf_event_open(attr, 0, cpu, -1, 0); + if (fd == -1) + return -EINVAL; + + addr = mmap(NULL, len, PROT_READ, MAP_SHARED, fd, 0); + if (addr == MAP_FAILED) + goto out_close; + + err = perf_read_tsc_conversion(addr, tc); + + munmap(addr, len); +out_close: + close(fd); + return err; +} + +static int find_a_cpu(void) +{ + struct perf_cpu_map *cpus; + int cpu; + + cpus = perf_cpu_map__new(NULL); + if (!cpus) + return 0; + cpu = cpus->map[0]; + perf_cpu_map__put(cpus); + return cpu; +} + +int perf_read_tsc_conv_for_clockid(s32 clockid, struct perf_tsc_conversion *tc) +{ + struct perf_event_attr attr = { + .size = sizeof(attr), + .type = PERF_TYPE_SOFTWARE, + .config = PERF_COUNT_SW_DUMMY, + .exclude_kernel = 1, + .use_clockid = 1, + .clockid = clockid, + }; + int cpu = find_a_cpu(); + + return perf_read_tsc_conv_attr_cpu(&attr, cpu, tc); +} + int perf_event__synth_time_conv(const struct perf_event_mmap_page *pc, struct perf_tool *tool, perf_event__handler_t process, diff --git a/tools/perf/util/tsc.h b/tools/perf/util/tsc.h index 7d83a31732a7..ba9a52a9d70f 100644 --- a/tools/perf/util/tsc.h +++ b/tools/perf/util/tsc.h @@ -21,6 +21,7 @@ struct perf_event_mmap_page; int perf_read_tsc_conversion(const struct perf_event_mmap_page *pc, struct perf_tsc_conversion *tc); +int perf_read_tsc_conv_for_clockid(s32 clockid, struct perf_tsc_conversion *tc); u64 perf_time_to_tsc(u64 ns, struct perf_tsc_conversion *tc); u64 tsc_to_perf_time(u64 cyc, struct perf_tsc_conversion *tc); From patchwork Wed Feb 9 08:49:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12739834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA652C433F5 for ; Wed, 9 Feb 2022 08:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239608AbiBIIxD (ORCPT ); Wed, 9 Feb 2022 03:53:03 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:43812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238823AbiBIIxA (ORCPT ); Wed, 9 Feb 2022 03:53:00 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B33EEDF48F28; Wed, 9 Feb 2022 00:52:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644396775; x=1675932775; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sd2FUc95Y8Z/wafs1Ffg650oA/a+/88+ru79bgVwagI=; b=Sq+erksLmQ1jnn4El0i0afKLatLfREszbOZyTJPPZUuCQ/p7e/wu7xiV 6E02RyAVBURQj5nhpEcDnkjQkakkm25BDdeJofm6zEoWbWte7fYMU0eJs KoyjTkw2qoHTpxHqiuB6839l80OX0iPD3Rz0z29kMCUDq612djRoLbBbC W7qt3qOayEePVHA4v77SiQSbwK/0FLQbV6B+sJweh5JjWCGSAZPk/A7pj pQRbDUtA38AFwrmRIbullrXi5EeP6sDUfL6vYe10A37N9mgVuAE6q6YxJ 3y+DRyKC0+7nH/E6unkYQeGxKdCibIWFmBugp0ci1ukZR2Ffr/CWk66P4 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="309903026" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="309903026" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:50:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169367" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:50:05 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 08/11] perf intel-pt: Add support for new clock IDs Date: Wed, 9 Feb 2022 10:49:26 +0200 Message-Id: <20220209084929.54331-9-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add support for new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. Mainly this means also keeping TSC conversion information for CLOCK_PERF_HW_CLOCK_NS when CLOCK_PERF_HW_CLOCK is being used, so that conversions from nanoseconds can still be done when the perf event clock is TSC. Signed-off-by: Adrian Hunter --- tools/perf/arch/x86/util/intel-pt.c | 36 ++++++++++++++++++++++++++--- tools/perf/util/intel-pt.c | 21 +++++++++++++---- tools/perf/util/intel-pt.h | 2 +- 3 files changed, 51 insertions(+), 8 deletions(-) diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index 8c31578d6f4a..ce5dc70e392a 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -290,6 +290,20 @@ static const char *intel_pt_find_filter(struct evlist *evlist, return NULL; } +static bool intel_pt_clockid(struct evlist *evlist, struct perf_pmu *intel_pt_pmu, s32 clockid) +{ + struct evsel *evsel; + + evlist__for_each_entry(evlist, evsel) { + if (evsel->core.attr.type == intel_pt_pmu->type && + evsel->core.attr.use_clockid && + evsel->core.attr.clockid == clockid) + return true; + } + + return false; +} + static size_t intel_pt_filter_bytes(const char *filter) { size_t len = filter ? strlen(filter) : 0; @@ -304,9 +318,11 @@ intel_pt_info_priv_size(struct auxtrace_record *itr, struct evlist *evlist) container_of(itr, struct intel_pt_recording, itr); const char *filter = intel_pt_find_filter(evlist, ptr->intel_pt_pmu); - ptr->priv_size = (INTEL_PT_AUXTRACE_PRIV_MAX * sizeof(u64)) + + ptr->priv_size = (INTEL_PT_AUXTRACE_PRIV_FIXED * sizeof(u64)) + intel_pt_filter_bytes(filter); ptr->priv_size += sizeof(u64); /* Cap Event Trace */ + ptr->priv_size += sizeof(u64); /* ns Time Shift */ + ptr->priv_size += sizeof(u64); /* ns Time Multiplier */ return ptr->priv_size; } @@ -414,6 +430,18 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, *info++ = event_trace; + if (intel_pt_clockid(session->evlist, ptr->intel_pt_pmu, CLOCK_PERF_HW_CLOCK)) { + struct perf_tsc_conversion ns_tc; + + if (perf_read_tsc_conv_for_clockid(CLOCK_PERF_HW_CLOCK_NS, &ns_tc)) + return -EINVAL; + *info++ = ns_tc.time_shift; + *info++ = ns_tc.time_mult; + } else { + *info++ = tc.time_shift; + *info++ = tc.time_mult; + } + return 0; } @@ -664,8 +692,10 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, return -EINVAL; } - if (opts->use_clockid) { - pr_err("Cannot use clockid (-k option) with " INTEL_PT_PMU_NAME "\n"); + if (opts->use_clockid && opts->clockid != CLOCK_PERF_HW_CLOCK_NS && + opts->clockid != CLOCK_PERF_HW_CLOCK) { + pr_err("Cannot use clockid (-k option) with " INTEL_PT_PMU_NAME + " except CLOCK_PERF_HW_CLOCK_NS and CLOCK_PERF_HW_CLOCK\n"); return -EINVAL; } diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index ec43d364d0de..10d47759a41e 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -89,6 +89,8 @@ struct intel_pt { struct perf_tsc_conversion tc; bool cap_user_time_zero; + u16 ns_time_shift; + u32 ns_time_mult; struct itrace_synth_opts synth_opts; @@ -1100,10 +1102,10 @@ static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns) { u64 quot, rem; - quot = ns / pt->tc.time_mult; - rem = ns % pt->tc.time_mult; - return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) / - pt->tc.time_mult; + quot = ns / pt->ns_time_mult; + rem = ns % pt->ns_time_mult; + return (quot << pt->ns_time_shift) + (rem << pt->ns_time_shift) / + pt->ns_time_mult; } static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt) @@ -3987,6 +3989,17 @@ int intel_pt_process_auxtrace_info(union perf_event *event, pt->cap_event_trace); } + if ((void *)info < info_end) { + pt->ns_time_shift = *info++; + pt->ns_time_mult = *info++; + if (dump_trace) { + fprintf(stdout, " ns Time Shift %d\n", pt->ns_time_shift); + fprintf(stdout, " ns Time Multiplier %d\n", pt->ns_time_mult); + } + } + if (!pt->ns_time_mult) + pt->ns_time_mult = 1; + pt->timeless_decoding = intel_pt_timeless_decoding(pt); if (pt->timeless_decoding && !pt->tc.time_mult) pt->tc.time_mult = 1; diff --git a/tools/perf/util/intel-pt.h b/tools/perf/util/intel-pt.h index c7d6068e3a6b..a2c4474641c0 100644 --- a/tools/perf/util/intel-pt.h +++ b/tools/perf/util/intel-pt.h @@ -27,7 +27,7 @@ enum { INTEL_PT_CYC_BIT, INTEL_PT_MAX_NONTURBO_RATIO, INTEL_PT_FILTER_STR_LEN, - INTEL_PT_AUXTRACE_PRIV_MAX, + INTEL_PT_AUXTRACE_PRIV_FIXED, }; struct auxtrace_record; From patchwork Wed Feb 9 08:49:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12739835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2924C433EF for ; Wed, 9 Feb 2022 08:53:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238823AbiBIIxG (ORCPT ); Wed, 9 Feb 2022 03:53:06 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:44042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240072AbiBIIxF (ORCPT ); Wed, 9 Feb 2022 03:53:05 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DEB5DF48F3D; Wed, 9 Feb 2022 00:53:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644396780; x=1675932780; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=miD0Yf9C+MQxqIFghTdlVvKVbagPjG3BXOKwIH4J4CM=; b=nUv1FqocQ81NKMPgW55BTvWZ9k3LEx0TAEUC2b4bW4sDaDHQpcYnm/p6 pY4a2RBr5Hm92t9ZOJyfYEmHx1PQbENY5lPhhHf/B2obcA8yC4v0ocepV wcea2VHcfC93hAC+l9uyilzCshwm+KYQfMxmnDmWSfsdq78keT5Nmxpn7 pgILqXpbrAqSCRaptQPsfMi/rLb9/52+rDaADinpgcwD2cXf5NtmltJpE V73x63eX+EREn7Kzw0JcDcLX8yl1E+7mDNeqByKx2HITaLdTdgeUydQEn elbyZNd9DP/22mWDXElDTkZXaOZOYsCu3ZkXHbSkljhYxoQ7/HDmi9YTZ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="309903054" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="309903054" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:50:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169401" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:50:09 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 09/11] perf intel-pt: Use CLOCK_PERF_HW_CLOCK_NS by default Date: Wed, 9 Feb 2022 10:49:27 +0200 Message-Id: <20220209084929.54331-10-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Make CLOCK_PERF_HW_CLOCK_NS the default for Intel PT if it is supported. To allow that to be overridden, support also --no-clockid. Signed-off-by: Adrian Hunter --- tools/perf/arch/x86/util/intel-pt.c | 5 +++++ tools/perf/util/clockid.c | 1 + tools/perf/util/record.h | 1 + 3 files changed, 7 insertions(+) diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index ce5dc70e392a..d5cdc53471ff 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -926,6 +926,11 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, evsel__reset_sample_bit(tracking_evsel, BRANCH_STACK); } + if (!opts->use_clockid && !opts->no_clockid && perf_can_perf_clock_hw_clock_ns()) { + opts->use_clockid = true; + opts->clockid = CLOCK_PERF_HW_CLOCK_NS; + } + /* * Warn the user when we do not have enough information to decode i.e. * per-cpu with no sched_switch (except workload-only). diff --git a/tools/perf/util/clockid.c b/tools/perf/util/clockid.c index 380429725df1..e3500a254103 100644 --- a/tools/perf/util/clockid.c +++ b/tools/perf/util/clockid.c @@ -78,6 +78,7 @@ int parse_clockid(const struct option *opt, const char *str, int unset) if (unset) { opts->use_clockid = 0; + opts->no_clockid = true; return 0; } diff --git a/tools/perf/util/record.h b/tools/perf/util/record.h index ef6c2715fdd9..20bcd4310146 100644 --- a/tools/perf/util/record.h +++ b/tools/perf/util/record.h @@ -67,6 +67,7 @@ struct record_opts { bool sample_transaction; int initial_delay; bool use_clockid; + bool no_clockid; clockid_t clockid; u64 clockid_res_ns; int nr_cblocks; From patchwork Wed Feb 9 08:49:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12739836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 122BDC433EF for ; Wed, 9 Feb 2022 08:53:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242009AbiBIIxP (ORCPT ); Wed, 9 Feb 2022 03:53:15 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:44406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241143AbiBIIxK (ORCPT ); Wed, 9 Feb 2022 03:53:10 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80CFBDF28A7A; Wed, 9 Feb 2022 00:53:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644396785; x=1675932785; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NDRPuOyBPlZxfUKuBy6kNTLDmbdhFCgmtwTRiLV6mak=; b=SWnE/slGPk6P/GthsRYrCNjgxbu1TJEhuPP3pyLAg/SwiAJPUCraMHK1 aFqWZDvOU5FnYq0FaSr5btbshJooH/pmI3RSDb6NFcwkAhcGLJ7+Hv8AS dTJT8dyJjJGMWsu9rbcxVKf5yHM1UDZr5V5QgicA1uNf5AbZ22Cb/8ZDz +2gJBz3U13jvNN8cOit1hqZDZqiCs+PqJTKTkV14Pq7PWYX4rZP8qtTAm qUcjs4Y6hJVYgFZAVRtZSSavcBanaeg3/UWVWjeAZzZ49+k1UV7v9f3bn PAqKYXv++wUWE0YxwBYB62+HE2wCsSJkBuT/jK4pT6nWnCYl6tLtTnQSn g==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="309903082" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="309903082" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:50:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169446" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:50:13 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 10/11] perf intel-pt: Add config variables for timing parameters Date: Wed, 9 Feb 2022 10:49:28 +0200 Message-Id: <20220209084929.54331-11-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Parameters needed to correctly interpret timing packets might be missing in a virtual machine because the CPUID leaf or MSR is not supported by the hypervisor / KVM. Add perf config variables to overcome that for max_nonturbo_ratio (missing from MSR_PLATFORM_INFO) and tsc_art_ratio (missing from CPUID leaf 0x15), which were seen to be missing from QEMU / KVM. Signed-off-by: Adrian Hunter --- tools/perf/Documentation/perf-config.txt | 18 ++++++++ tools/perf/arch/x86/util/intel-pt.c | 52 +++++++++++++++++++++++- tools/perf/util/intel-pt.c | 6 +++ tools/perf/util/intel-pt.h | 5 +++ 4 files changed, 79 insertions(+), 2 deletions(-) diff --git a/tools/perf/Documentation/perf-config.txt b/tools/perf/Documentation/perf-config.txt index 0420e71698ee..3c4fc641fde7 100644 --- a/tools/perf/Documentation/perf-config.txt +++ b/tools/perf/Documentation/perf-config.txt @@ -709,7 +709,11 @@ stat.*:: intel-pt.*:: + Variables that affect Intel PT. + intel-pt.cache-divisor:: + If set, the decoder instruction cache size is based on DSO size + divided by this number. intel-pt.mispred-all:: If set, Intel PT decoder will set the mispred flag on all @@ -721,6 +725,20 @@ intel-pt.*:: the maximum is exceeded there will be a "Never-ending loop" error. The default is 100000. + intel-pt.max_nonturbo_ratio:: + The kernel provides /sys/bus/event_source/devices/intel_pt/max_nonturbo_ratio + which can be zero in a virtual machine. The decoder needs this + information to correctly interpret timing packets, so the value + can be provided by this variable in that case. Note in the absence + of VMCS TSC Scaling, this is probably the same as the host value. + + intel-pt.tsc_art_ratio:: + The kernel provides /sys/bus/event_source/devices/intel_pt/tsc_art_ratio + which can be 0:0 in a virtual machine. The decoder needs this + information to correctly interpret timing packets, so the value + can be provided by this variable in that case. Note in the absence + of VMCS TSC Scaling, this is probably the same as the host value. + auxtrace.*:: auxtrace.dumpdir:: diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index d5cdc53471ff..6b48f7e38a1c 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -24,6 +24,7 @@ #include "../../../util/parse-events.h" #include "../../../util/pmu.h" #include "../../../util/debug.h" +#include "../../../util/config.h" #include "../../../util/auxtrace.h" #include "../../../util/perf_api_probe.h" #include "../../../util/record.h" @@ -327,15 +328,60 @@ intel_pt_info_priv_size(struct auxtrace_record *itr, struct evlist *evlist) return ptr->priv_size; } +struct tsc_art_ratio { + u32 *n; + u32 *d; +}; + +static int intel_pt_tsc_art_ratio(const char *var, const char *value, void *data) +{ + if (!strcmp(var, "intel-pt.tsc_art_ratio")) { + struct tsc_art_ratio *r = data; + + if (sscanf(value, "%u:%u", r->n, r->d) != 2) + return -EINVAL; + } + return 0; +} + +void intel_pt_tsc_ctc_ratio_from_config(u32 *n, u32 *d) +{ + struct tsc_art_ratio data = { .n = n, .d = d }; + + *n = 0; + *d = 0; + perf_config(intel_pt_tsc_art_ratio, &data); +} + static void intel_pt_tsc_ctc_ratio(u32 *n, u32 *d) { unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; __get_cpuid(0x15, &eax, &ebx, &ecx, &edx); + if (!eax || !ebx) { + intel_pt_tsc_ctc_ratio_from_config(n, d); + return; + } *n = ebx; *d = eax; } +static int intel_pt_max_nonturbo_ratio(const char *var, const char *value, void *data) +{ + if (!strcmp(var, "intel-pt.max_nonturbo_ratio")) { + unsigned int *max_nonturbo_ratio = data; + + if (sscanf(value, "%u", max_nonturbo_ratio) != 1) + return -EINVAL; + } + return 0; +} + +void intel_pt_max_nonturbo_ratio_from_config(unsigned int *max_non_turbo_ratio) +{ + perf_config(intel_pt_max_nonturbo_ratio, max_non_turbo_ratio); +} + static int intel_pt_info_fill(struct auxtrace_record *itr, struct perf_session *session, struct perf_record_auxtrace_info *auxtrace_info, @@ -349,7 +395,7 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, bool cap_user_time_zero = false, per_cpu_mmaps; u64 tsc_bit, mtc_bit, mtc_freq_bits, cyc_bit, noretcomp_bit; u32 tsc_ctc_ratio_n, tsc_ctc_ratio_d; - unsigned long max_non_turbo_ratio; + unsigned int max_non_turbo_ratio; size_t filter_str_len; const char *filter; int event_trace; @@ -373,8 +419,10 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, intel_pt_tsc_ctc_ratio(&tsc_ctc_ratio_n, &tsc_ctc_ratio_d); if (perf_pmu__scan_file(intel_pt_pmu, "max_nonturbo_ratio", - "%lu", &max_non_turbo_ratio) != 1) + "%u", &max_non_turbo_ratio) != 1) max_non_turbo_ratio = 0; + if (!max_non_turbo_ratio) + intel_pt_max_nonturbo_ratio_from_config(&max_non_turbo_ratio); if (perf_pmu__scan_file(intel_pt_pmu, "caps/event_trace", "%d", &event_trace) != 1) event_trace = 0; diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index 10d47759a41e..6fa76b584537 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -3934,6 +3934,9 @@ int intel_pt_process_auxtrace_info(union perf_event *event, INTEL_PT_CYC_BIT); } + if (!pt->tsc_ctc_ratio_n || !pt->tsc_ctc_ratio_d) + intel_pt_tsc_ctc_ratio_from_config(&pt->tsc_ctc_ratio_n, &pt->tsc_ctc_ratio_d); + if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) { pt->max_non_turbo_ratio = auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO]; @@ -3942,6 +3945,9 @@ int intel_pt_process_auxtrace_info(union perf_event *event, INTEL_PT_MAX_NONTURBO_RATIO); } + if (!pt->max_non_turbo_ratio) + intel_pt_max_nonturbo_ratio_from_config(&pt->max_non_turbo_ratio); + info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1; info_end = (void *)auxtrace_info + auxtrace_info->header.size; diff --git a/tools/perf/util/intel-pt.h b/tools/perf/util/intel-pt.h index a2c4474641c0..99ac73f4a648 100644 --- a/tools/perf/util/intel-pt.h +++ b/tools/perf/util/intel-pt.h @@ -7,6 +7,8 @@ #ifndef INCLUDE__PERF_INTEL_PT_H__ #define INCLUDE__PERF_INTEL_PT_H__ +#include + #define INTEL_PT_PMU_NAME "intel_pt" enum { @@ -44,4 +46,7 @@ int intel_pt_process_auxtrace_info(union perf_event *event, struct perf_event_attr *intel_pt_pmu_default_config(struct perf_pmu *pmu); +void intel_pt_tsc_ctc_ratio_from_config(u32 *n, u32 *d); +void intel_pt_max_nonturbo_ratio_from_config(unsigned int *max_non_turbo_ratio); + #endif From patchwork Wed Feb 9 08:49:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12739837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CBEFC4332F for ; Wed, 9 Feb 2022 08:53:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242386AbiBIIxQ (ORCPT ); Wed, 9 Feb 2022 03:53:16 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:44644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241314AbiBIIxN (ORCPT ); Wed, 9 Feb 2022 03:53:13 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2263E02460E; Wed, 9 Feb 2022 00:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644396789; x=1675932789; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LMcqPNXnMe4ZfRX2pvOSR54SRmRLNEnmPESpB5J91po=; b=kzpK9D2O35WlxQ38NsneJrzID6bFn+0DrNqI8IqG2Ifs2sMddkKJ1ss0 7LFLni7Vn+0cqEmbNFj5KSETokL7v2lsD5y0AcWr9rX0LqALTiFp8AtJL lZg7suBPq/Gbg1VuSUCFaqrQdwPj/pSpWgaXO+pO5oMZUNxfUl5oUwtdx YCYvfXKJBpZCVhQn+ZX5CIdqxn6pP4mhYPwoKQEzwQIZB7/4JHlX9vqxr kncV4kbidaoHFgHc+KomhCFri30y99vqgEooxiv63t+CcPdLQzEvpWOta 9qsRaZQEdFvJfL3UmYoi2uGFdP6y/VnCNQJ5mrGtpLXZDoEW2tH19VGUL g==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="309903113" X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="309903113" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 00:50:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,355,1635231600"; d="scan'208";a="568169493" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga001.jf.intel.com with ESMTP; 09 Feb 2022 00:50:18 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH 11/11] perf intel-pt: Add documentation for new clock IDs Date: Wed, 9 Feb 2022 10:49:29 +0200 Message-Id: <20220209084929.54331-12-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209084929.54331-1-adrian.hunter@intel.com> References: <20220209084929.54331-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add brief documentation for new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS, as well as new config variables intel-pt.max_nonturbo_ratio and intel-pt.tsc_art_ratio. Signed-off-by: Adrian Hunter --- tools/perf/Documentation/perf-intel-pt.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tools/perf/Documentation/perf-intel-pt.txt b/tools/perf/Documentation/perf-intel-pt.txt index ff58bd4c381b..45f750024e3d 100644 --- a/tools/perf/Documentation/perf-intel-pt.txt +++ b/tools/perf/Documentation/perf-intel-pt.txt @@ -509,6 +509,31 @@ notnt Disable TNT packets. Without TNT packets, it is not possible to walk "0" otherwise. +perf event clock +~~~~~~~~~~~~~~~~ + +Newer kernel and tools support 2 special clocks: CLOCK_PERF_HW_CLOCK which is +TSC and CLOCK_PERF_HW_CLOCK_NS which is TSC converted to nanoseconds. +CLOCK_PERF_HW_CLOCK_NS is the same as the default perf event clock, but it is +not subject to paravirtualization, so it still works with Intel PT in a VM +guest. CLOCK_PERF_HW_CLOCK_NS is used by default if it is supported. + +To use TSC instead of nanoseconds, use the option: + + --clockid CLOCK_PERF_HW_CLOCK + +Beware forgetting that the time stamp of events will show TSC ticks +(divided by 1,000,000,000) not seconds. + +To use the default perf event clock instead of CLOCK_PERF_HW_CLOCK_NS when +CLOCK_PERF_HW_CLOCK_NS is supported, use the option: + + --no-clockid + +Other clocks are not supported for use with Intel PT because they cannot be +converted to/from TSC. + + AUX area sampling option ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1398,6 +1423,28 @@ There were none. :17006 17006 [001] 11500.262869216: ffffffff8220116e error_entry+0xe ([guest.kernel.kallsyms]) pushq %rax +Tracing within a Virtual Machine +-------------------------------- + +When supported, using Intel PT within a virtual machine does not support TSC +because the perf event clock is subject to paravirtualization. That is +overcome by the new CLOCK_PERF_HW_CLOCK_NS clock - refer 'perf event clock' +above. In addition, in a VM, the following might be zero: + + /sys/bus/event_source/devices/intel_pt/max_nonturbo_ratio + /sys/bus/event_source/devices/intel_pt/tsc_art_ratio + +The decoder needs this information to correctly interpret timing packets, +so the values can be provided by config variables in that case. Note in +the absence of VMCS TSC Scaling, this is probably the same as the host values. +The config variables are: + + intel-pt.max_nonturbo_ratio + intel-pt.tsc_art_ratio + +For more information about perf config variables, refer linkperf:perf-config[1] + + Event Trace -----------