From patchwork Wed Feb 9 21:54:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 670DEC433FE for ; Wed, 9 Feb 2022 21:58:03 +0000 (UTC) Received: from localhost ([::1]:45620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHuyQ-00076p-AU for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 16:58:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuvX-0004rJ-OI for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:03 -0500 Received: from [2607:f8b0:4864:20::102e] (port=42651 helo=mail-pj1-x102e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHuvW-0007qI-2W for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:03 -0500 Received: by mail-pj1-x102e.google.com with SMTP id h7-20020a17090a648700b001b927560c2bso2453969pjj.1 for ; Wed, 09 Feb 2022 13:55:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x8Cva6nCIUoDekI5oK77jag6eRVxIc3cZd/244xh9Bg=; b=SLUho44oz/7RWNSV3AiGmK1BzYcEV3CxyN99HxZk/C4oyUNi+yekCHONkJ6XVrLxQn yMbsnzXxwv5hHqqF/pWVvIOuMHFhXd4eqgTgv4FzhN9UKRdD2spIwc00lxt09bB6ZFhr jiBCv0X3eY/Gwj2gJ0lIuvLppn7puDa3f30OE1BFWCyYfFOZOUbj2mViUEMTQm5Ea1Uk Z2loe4TflPSRDE2vKLrwaeK7+iNpmtRGy12gxE20Sb+QpD739GGg8UeIf0zs0rDV6wbr hSqWJZUy+i+eG9vvk33grafpkXMkMfz62+cOQvqxp7DnPbjzt8q2u487nowGhMrcr3/e BZmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=x8Cva6nCIUoDekI5oK77jag6eRVxIc3cZd/244xh9Bg=; b=r0MXm9sxQcnQb3b37fZpWFJY1ksCDr3mHDbxIP/JWv5Jt/7FCS/BGCS/7i0iSPxBoF U/FbaVu8KMwuYbJKDgiDeoT+JUmgN3GhrKWq8WsGYLZzYsCFvl+ej0qLsyGd+zCVoxsW yx7ITKnjt05TW4fkN7gaDSE7EBqojHrUTIaq4j5PsAX4ISVO+vlNxN+SE6mbbLySxJNm i8Z3QRbF7iUscfFIleza6daCqwZrhWjgq4uDvK4XogcipzhXLsS8no+PSbenalQ9chsy 1bVcvTi9dabCpAY7DM9boFIgfkxXuDb+KbR/hnGHZ8Zw8UIqUScekqfS62URFUUqNlzr 97ww== X-Gm-Message-State: AOAM5324CvQISosFnTExQWCy53s4pQEoJS323oXEVCDPA2CMqQVD8dAK FymUqxtlHx7UUgPr9KNJoVnhT6WLBGM= X-Google-Smtp-Source: ABdhPJx/oWD+ZfiDV/pRR8BmcjWcFJThKkeuUbdpKh8OPQ4FbIvvl8ey/aspaprKsvu0DTLcoVamLw== X-Received: by 2002:a17:90b:38c7:: with SMTP id nn7mr4870729pjb.124.1644443700753; Wed, 09 Feb 2022 13:55:00 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id o8sm21188521pfu.52.2022.02.09.13.54.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:55:00 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 01/15] meson: Display libfdt as disabled when system emulation is disabled Date: Wed, 9 Feb 2022 22:54:32 +0100 Message-Id: <20220209215446.58402-2-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= When configuring QEMU with --disable-system, meson keeps showing libfdt as "auto". Mark it as disabled instead. Acked-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daudé --- meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 571af34b7d..3c274386bb 100644 --- a/meson.build +++ b/meson.build @@ -2271,8 +2271,8 @@ if get_option('cfi') and slirp_opt == 'system' endif fdt = not_found -fdt_opt = get_option('fdt') if have_system + fdt_opt = get_option('fdt') if fdt_opt in ['enabled', 'auto', 'system'] have_internal = fs.exists(meson.current_source_dir() / 'dtc/libfdt/Makefile.libfdt') fdt = cc.find_library('fdt', kwargs: static_kwargs, @@ -2315,6 +2315,8 @@ if have_system fdt = declare_dependency(link_with: libfdt, include_directories: fdt_inc) endif +else + fdt_opt = 'disabled' endif if not fdt.found() and fdt_required.length() > 0 error('fdt not available but required by targets ' + ', '.join(fdt_required)) From patchwork Wed Feb 9 21:54:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF4C0C433EF for ; Wed, 9 Feb 2022 22:02:50 +0000 (UTC) Received: from localhost ([::1]:54342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHv33-0004xF-Q0 for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 17:02:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuvu-00050Z-QQ for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:26 -0500 Received: from [2607:f8b0:4864:20::102d] (port=38874 helo=mail-pj1-x102d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHuvg-00081Z-1K for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:18 -0500 Received: by mail-pj1-x102d.google.com with SMTP id h14-20020a17090a130e00b001b88991a305so6548327pja.3 for ; Wed, 09 Feb 2022 13:55:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J84qIjygQPTZULeHT6lJUDBBJVkyzL5iTTMxavo/mCM=; b=bTbdcsOPl0yWfiNamSpfUi4uc7DH8hvDraepJl7v+uvfMZOuRaywxKoFym+O5+2ok5 KG3MEnbEUjYLU8YKQxGHI07S/Pft4QHyl8swKJ4o9dUkGUWYrMFM9Fomwx7EQVyuxlBK qKaiXTVDkgeCkPve4/uPXR+BdMqX9pAYtWEa/eExYxN3ZZTfTNIHk5yd4JS56YqGk+us /AXY75Pl0PBHHTeJtxtPDz/YDs259dT99RW2TPPBKeHmx9gIlgYOAlWA4RUStVNGDk7Z ED8S5f7sdWPWRf46IgtnPNo1OfGdg9Cv1SAUr+UJzdMUj9MKJP/yoMx1iI6S4oAJAd6J 5cng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=J84qIjygQPTZULeHT6lJUDBBJVkyzL5iTTMxavo/mCM=; b=r7VyO24VfSZtCSbJx25fhxfz4PSs1vqSxTg/9gLkBtLVN39FHIcgZW3fcUFtdw/xsH cdjRcNB2jolnFfaKDyILnMe6ziT0X9yZSHT8M+ZthH8zxNmW5YA4+cubQ1548xvmmK8x ZkbEGNmZiIJ3OIAD/HrmLJlVjOctJjmvR6yOQdhcqdcC86z8xeG7FdKYjSOXCMYZY5RU LYoX3zskHfdmVdM469LHTvp7QnS5t03ChRo3rHSR/J8R4aEv4bz3iP5WEDSVP9kNIALs TyjxQmuZMcXX4rKwpyNNxKWk25pRpPqDjxv3gpx2yjJG7EddY9bfn3cbhnZwv1gPCbWl TOoQ== X-Gm-Message-State: AOAM530L2DX5S1B7ppvSF/368jChqOsjuL1zcmVydA88r5pfOzobHRYu 3Ewyy7YrfHKzFivcAdCOI71iVKHQ7LA= X-Google-Smtp-Source: ABdhPJykWeRkoGBfOahJGYTcIYGubLUNjpX0REAxi5eKTjxOMp1k7lrpWTPEOflRiD1MamrDDcadMg== X-Received: by 2002:a17:90a:1987:: with SMTP id 7mr4848706pji.215.1644443708824; Wed, 09 Feb 2022 13:55:08 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- include/hw/m68k/mcf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h index decf17ce42..8cbd587bbf 100644 --- a/include/hw/m68k/mcf.h +++ b/include/hw/m68k/mcf.h @@ -2,6 +2,7 @@ #define HW_MCF_H /* Motorola ColdFire device prototypes. */ +#include "exec/hwaddr.h" #include "target/m68k/cpu-qom.h" /* mcf_uart.c */ From patchwork Wed Feb 9 21:54:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0BC1C433FE for ; Wed, 9 Feb 2022 22:02:27 +0000 (UTC) Received: from localhost ([::1]:53770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHv2g-0004Zv-Q4 for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 17:02:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuvx-00055B-6n for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:29 -0500 Received: from [2607:f8b0:4864:20::42f] (port=45724 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHuvv-00082B-0Z for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:28 -0500 Received: by mail-pf1-x42f.google.com with SMTP id 9so3859148pfx.12 for ; Wed, 09 Feb 2022 13:55:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=towQfqS0jMqw5GnfvXlTSNN7JfZiHl4TlvOHlC1CNHc=; b=NN1L2zC/McZb47pqln3giILB0k38X9STl+rHzZx/rjtpm8cnmfztB6+hxl+mA5IN+q mj4R2QAmDPAMGGM4HNpHpH/j3WGWCsF9CBPXvhk5j24A2DWcMgLPl1Mq5Da2c0cvTHHx etAhIpaM2fUd5B0oaBvb1D0lvppZJN9yd7cPj4IWU9Z9DnfQolwU1SCF26VXiws70iQI V3tqRv9JpY/eueoPXpo1gWuG6P8uucBbw8oHY7HlP0JUjVMIr5BAnYGGt/F/yccV1ctM sgp7B8XoIn9NpdaKe7GrgftZe17+WSTAHjA3NcoImuxla7+Q/hOvt4nBbDcu2S7pAOBS LCKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=towQfqS0jMqw5GnfvXlTSNN7JfZiHl4TlvOHlC1CNHc=; b=D/7djAWcB4Dz91uQccGPsvsrnR+ZzRi5S09pg9IyGUPAFbIGEf+c6C9CxGAwejhhPH EOFjMKX8cdhMJ2j4/y7Eo6+XG7W1dILlvl4znwefUVb8AmaRQJ34FDZlgpPpCNGrIRpb SK2xcYff3fipQkg0ETJygkCqk2rHGf7kuj27EZ3TlFiEkERpNpEVJBcjXBGIyy0wsWQd DfZqo1BxLT08fmV9AuLtzRKAptEUwfF4H5d/uD08/tIozUYh9a3lEhkjIaNDhHm6a+5d UAwd5P8YjQHrdivpDR69Q1D6QtntfTemyTGTLlo6FVYgFJKnlk/aRtDOWTyRTVr4FyXR CuHA== X-Gm-Message-State: AOAM532X4BU4o72dSudfVIa+SCAHcQTMfqk/kHx6aCy265dsTwc0sGzr 4pRygw2a9CSqYabkA78DT5wDKVVCM9Q= X-Google-Smtp-Source: ABdhPJzc5W2htK/qIlFFT4c8DaCwtKp4zS4jO5GtYEPGEpuXJPM5X2sMHT+Ks4kaTRUH3JR72XemrQ== X-Received: by 2002:aa7:9486:: with SMTP id z6mr4390337pfk.76.1644443716635; Wed, 09 Feb 2022 13:55:16 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id pj8sm3208982pjb.26.2022.02.09.13.55.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:55:16 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 03/15] hw/tricore: Remove unused and incorrect header Date: Wed, 9 Feb 2022 22:54:34 +0100 Message-Id: <20220209215446.58402-4-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= TriCore boards certainly don't need the ARM loader API :) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- include/hw/tricore/triboard.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h index f3844be447..094c8bd563 100644 --- a/include/hw/tricore/triboard.h +++ b/include/hw/tricore/triboard.h @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/boards.h" -#include "hw/arm/boot.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "qom/object.h" From patchwork Wed Feb 9 21:54:35 2022 Content-Type: text/plain; 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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id k14sm21200538pff.25.2022.02.09.13.55.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:55:32 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 05/15] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers Date: Wed, 9 Feb 2022 22:54:36 +0100 Message-Id: <20220209215446.58402-6-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= cpu.c requires "exec/exec-all.h" to call tlb_flush() and "qemu/accel.h" to call accel_cpu_realizefn(). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cpu.c b/cpu.c index 97d42b6b2a..6b4aa53775 100644 --- a/cpu.c +++ b/cpu.c @@ -35,10 +35,12 @@ #include "sysemu/tcg.h" #include "sysemu/kvm.h" #include "sysemu/replay.h" +#include "exec/exec-all.h" #include "exec/translate-all.h" #include "exec/log.h" #include "hw/core/accel-cpu.h" #include "trace/trace-root.h" +#include "qemu/accel.h" uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; From patchwork Wed Feb 9 21:54:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0614C433F5 for ; Wed, 9 Feb 2022 22:13:10 +0000 (UTC) Received: from localhost ([::1]:43068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHvD2-0000Gl-Lv for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 17:13:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuwD-0005Xy-UX for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:45 -0500 Received: from [2607:f8b0:4864:20::1035] (port=46965 helo=mail-pj1-x1035.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHuwA-00086F-Nb for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:45 -0500 Received: by mail-pj1-x1035.google.com with SMTP id t4-20020a17090a510400b001b8c4a6cd5dso3622915pjh.5 for ; Wed, 09 Feb 2022 13:55:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cwzAoSrGJ3x/bKluviqLTkKJTgNhXDXBL+z+UP/egkI=; b=qsYixGPkXVy5qm7zcx6NNvjA6SqpxDl3yMstkeOEzFJ+E4Wx5deFpGTlWlcqIWbZif Iw6foF7LviOLFWmE3JVb/rt9dmlmbC98wRK4npMpGX0dmr1peIQH1ia4Mk52Ze5/xybU Fxvnv81VdZ3jaur3hPpn2dULY/j6akaid+Jkfa6BIo3xziPNhaG1z6tCcEUlxzLZmvC0 x4Hb7l7/v/U5/ENaqcXtCfEJqS0INeqSW+WXnnb9oHJzVvoqz5kPPbGHDba2sADIeRhf xZwswQQZd5/dCK6VPtqNrWQETnw1INxDtK2jLmvt4beSjq2pWph3kIA/P/GQ8RNwEnxX WJHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cwzAoSrGJ3x/bKluviqLTkKJTgNhXDXBL+z+UP/egkI=; b=IviAvMIdM9pKv8b1H3+M4boCRCPyIxODddkQDYtUOgKJ6oiYUEo0UFZ2h9t6A2o2hz saBqA0JvtkszRkgIY2G8NjjU4wN12hg4fITv5PLB5vVDHBSbFKjBvEzIhCJh6343vTBS VASTyfunzDoXKgGVL/pm+mlS4FZaF/wxo643YACDVX3M4AmNYVO8u569Yqjve5Jwk92J UdiDCLu5hwzJeo6WLrZQbKCF0ADpb6XwYEWHeWiHKK8/goPvMA7w7RVOwd9NDlIkISY2 f11YwDMkUpxM5lcYMKWKyMAgBMkyj0R442edrybvqhshSJhAGhxE1005mRcIOC/9h1/x 06ng== X-Gm-Message-State: AOAM531h4n86wlOWSN7OxpuiegVLQuhAsLT69rHldvgxjMxcCoqLmLGi 3S4/5sozjHu+DFhTANe8qw1mbGX3Oks= X-Google-Smtp-Source: ABdhPJyDX6LYHTl089fisc7yWraY7QSnjcngtiFuEbnhEVVbEkkCXrbdDpF2zcSGDbZbMpXM/LT2Ow== X-Received: by 2002:a17:90a:72c2:: with SMTP id l2mr4833458pjk.14.1644443741257; Wed, 09 Feb 2022 13:55:41 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id 13sm8304240pfx.122.2022.02.09.13.55.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:55:40 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 06/15] target/i386/cpu: Ensure accelerators set CPU addressble physical bits Date: Wed, 9 Feb 2022 22:54:37 +0100 Message-Id: <20220209215446.58402-7-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= The only accelerator allowed to use zero as default value is TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index aa9e636800..16523a78d9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6384,6 +6384,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) * In this case, the default is the value used by TCG (40). */ if (cpu->phys_bits == 0) { + assert(tcg_enabled()); cpu->phys_bits = TCG_PHYS_ADDR_BITS; } } else { From patchwork Wed Feb 9 21:54:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 871D3C433F5 for ; Wed, 9 Feb 2022 22:19:11 +0000 (UTC) Received: from localhost ([::1]:51612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHvIs-0006CG-Fr for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 17:19:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuwK-0005ju-8L for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:52 -0500 Received: from [2607:f8b0:4864:20::433] (port=46795 helo=mail-pf1-x433.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHuwI-0008A4-M9 for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:55:51 -0500 Received: by mail-pf1-x433.google.com with SMTP id i21so5257389pfd.13 for ; Wed, 09 Feb 2022 13:55:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HEX583CN6Lejo1CTi/cSn0WJLHR6qP5OaDMjAKT4qKE=; b=D0jTc3j6QXz+t79Fx7xk418Typ6VUKPTbkNJej7L/UpQz5dc1NgiL/SUCFC7IkQu8m 5rercoH8PPGpGvpUqGFq62tD1qr0b0IrPGYba9SazoXB1b2A2qOc75brAW4d/0kF1fhB MIaR0TPHi5DTIgQxbgIIWx6IkxiyMSNzzubJeWjfQjJR02iOR1JeJjlAU/+d4DM4wXky S0yBJ4HQ/GzI75I9ciVNtYlva/XGPNwf0mtZ7LHShjv2M/ufTUwe8U69KufEg9dH7M1C 5YHwYK3EY6NgFMtyqb0gnjhxqJ5WHG+DSN7HRTLVjwCdb1jR/KfKHpnA0ywyzfv8auHd QSqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HEX583CN6Lejo1CTi/cSn0WJLHR6qP5OaDMjAKT4qKE=; b=VcxzeHdwPRRk5yKQN+iEOx5e7Xdzf1koa/v34WU49OeFvZPdXXwKecDkwhlqo+g6FR qZFpJr4lPyxHT44F+7E/xwu6oW1oNNDvRQG5/1yrRRCFDFIleFpK5RlJbnlOLJ/no9bR PfxtIyCldAy1GFd+lgEo33uOcA7Yg7SsfzHG9n+wNXKEu0v9BSElymjYPi6ej0aWBom9 jq4dy+vHFqNQ3I1fAm896yBM9oFdWXwas2nctVEu9eTP5ai03SBnDJmkf+gwQVusqFwh gYkO/J0/UX1upigP/W3MbsdNb0aTRk8aSAWJYO6YQx64OD9U5OmjCUrN3mjTlmd0zAif 6pbw== X-Gm-Message-State: AOAM5321w/jDvD6A2wnYWqaapK1695UNCJ5GK2QCkin9JzmY4NTl8P4t NQX50qXbkTuDwYfjAsPmtmrU3iIVTok= X-Google-Smtp-Source: ABdhPJwzShSz71ShZ5QNqpFyJNUG20tLAEqptFv8xlP09/FScIGUlNhGe3BFmTIXVQbO7/BJWJoMQw== X-Received: by 2002:a05:6a00:198f:: with SMTP id d15mr4390926pfl.78.1644443749336; Wed, 09 Feb 2022 13:55:49 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id u9sm12890935pfi.19.2022.02.09.13.55.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:55:49 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 07/15] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header Date: Wed, 9 Feb 2022 22:54:38 +0100 Message-Id: <20220209215446.58402-8-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::433 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= excp_helper.c requires "exec/exec-all.h" for tlb_set_page_with_attrs() and misc_helper.c for tlb_flush(). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/sysemu/excp_helper.c | 1 + target/i386/tcg/sysemu/misc_helper.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index 5ba739fbed..5627772e7c 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" #include "tcg/helper-tcg.h" int get_pg_mode(CPUX86State *env) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 9ccaa054c4..3715c1e262 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "exec/exec-all.h" #include "tcg/helper-tcg.h" void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) From patchwork Wed Feb 9 21:54:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D493C433F5 for ; Wed, 9 Feb 2022 22:09:16 +0000 (UTC) Received: from localhost ([::1]:37920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHv9H-0004kt-Mi for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 17:09:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuwa-0005w3-W3 for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:56:09 -0500 Received: from [2607:f8b0:4864:20::1030] (port=33622 helo=mail-pj1-x1030.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHuwW-0008Cz-3b for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:56:08 -0500 Received: by mail-pj1-x1030.google.com with SMTP id k60-20020a17090a4cc200b001b932781f3eso420548pjh.0 for ; Wed, 09 Feb 2022 13:55:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e8DQWHfKGeT/pxGHQ+jFVIO6FZ9E+wxAU1QxxX34iiM=; b=YC9tagVwMNzFg2egX2AdenX7iDmbjMiR1zPP6NB0gTm3Ndou855tSP9RituCzTD5LI bpTs9rjyjk11N5yNryN6Ga6GzoXTuCo9c406kwNOkryPYZMr/c0ATUHku05GNaykNVdW YTxsE/4Y2+gWtK7BLLN7R6yZAx6feoPgV1sYnlkjsSvxZEJ7oxMxDsWHf8P5CUQj6bu/ +W1ZO/Ds2tE4c6KK+XG3buYhbQ7HvyxnAxcqBrLyeInLEK3tYr3EamgQwFEBdla3cJDA hMLu1uR2Prr0UJUGbt+PWWpb9mRqLN32C0eG9MpCHUXf+5xrPQucJwYpiLjBKXceC/kz rmoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=e8DQWHfKGeT/pxGHQ+jFVIO6FZ9E+wxAU1QxxX34iiM=; b=hhixMSassE7WM+KmlefNjQqN4Sx8zyufwJ47VNYQsfRe3TSnRTYUp1rUgeZVzhzUyN 2egr4UVoI4FpxS/O2oEM7dXUBgTp6f4kz/O8LMF20jQyvZSXaza/ReQ5GJmBJvyH+Xnc WQcWxjTfpoMtvSno21MBdcp24Hiw7f0hvvofRXogK8Mv1sHxP3JV1W01TpMaOp49Pttl Yp4+eTduLa/Md1lLSleI3cl2EBLPMcZSu70V0p76yM0QWNW6Rxbu06I06ZWSou8NIr3g 1Sjo+wPOPSgbd62+9npnbaMj8ghUfSgCVY90V9b9ns+x2etob8Ouz1DoDQ7j9vqErCT6 RzUQ== X-Gm-Message-State: AOAM531AyRMViKnZADJrKn9dyVObit0HzT5/J+nyUiQjSe24R7Pd9D0b TS15k90uEYVNkOYmrwPa7i0cZVEjj3A= X-Google-Smtp-Source: ABdhPJzoHMaOiDAC4rwTDoX41BZ7HWj2xDFM+B8+B4HFBqZJGJP5cBqiOk26dQeAU9irR5sM8X2oMg== X-Received: by 2002:a17:902:ab43:: with SMTP id ij3mr4591636plb.25.1644443757069; Wed, 09 Feb 2022 13:55:57 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id lp17sm7613636pjb.25.2022.02.09.13.55.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:55:56 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 08/15] target: Include missing 'cpu.h' Date: Wed, 9 Feb 2022 22:54:39 +0100 Message-Id: <20220209215446.58402-9-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1030 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= These target-specific files use the target-specific CPU state but lack to include "cpu.h"; i.e.: ../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState' void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, ^ ../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State' void mmu_flip_um(CPUNios2State *env, unsigned int um); ^ ../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'; did you mean 'CPUState'? uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); ^~~~~~~~~~ CPUState Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/mmu.h | 2 ++ target/mips/internal.h | 1 + target/nios2/mmu.h | 2 ++ target/riscv/pmp.h | 2 ++ 4 files changed, 7 insertions(+) diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index b6b4b9ad60..1068bd2d52 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -20,6 +20,8 @@ #ifndef TARGET_MICROBLAZE_MMU_H #define TARGET_MICROBLAZE_MMU_H +#include "cpu.h" + #define MMU_R_PID 0 #define MMU_R_ZPR 1 #define MMU_R_TLBX 2 diff --git a/target/mips/internal.h b/target/mips/internal.h index daddb05fd4..f705d6bfa6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -12,6 +12,7 @@ #ifdef CONFIG_TCG #include "tcg/tcg-internal.h" #endif +#include "cpu.h" /* * MMU types, the first four entries have the same layout as the diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h index 4f46fbb82e..d36b8cc86a 100644 --- a/target/nios2/mmu.h +++ b/target/nios2/mmu.h @@ -21,6 +21,8 @@ #ifndef NIOS2_MMU_H #define NIOS2_MMU_H +#include "cpu.h" + typedef struct Nios2TLBEntry { target_ulong tag; target_ulong data; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index a9a0b363a7..fcb6b7c467 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -22,6 +22,8 @@ #ifndef RISCV_PMP_H #define RISCV_PMP_H +#include "cpu.h" + typedef enum { PMP_READ = 1 << 0, PMP_WRITE = 1 << 1, From patchwork Wed Feb 9 21:54:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C61AC433F5 for ; Wed, 9 Feb 2022 22:05:04 +0000 (UTC) Received: from localhost ([::1]:57748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHv5D-0007El-Bt for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 17:05:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuwb-0005wI-42 for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:56:09 -0500 Received: from [2607:f8b0:4864:20::62e] (port=35638 helo=mail-pl1-x62e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nHuwY-0008EQ-LU for qemu-devel@nongnu.org; Wed, 09 Feb 2022 16:56:08 -0500 Received: by mail-pl1-x62e.google.com with SMTP id y7so131608plp.2 for ; Wed, 09 Feb 2022 13:56:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lt5xGKR3Z7vKxq8vzU4efggY71T1A412lzm5UN/xys0=; b=HZgOlTky7vG1yIzXJb3/Wd1otP7NrtCJqJ1lTu8Gz0K+y3JIUMR41KragsktnXLIpf XBUfx/qKs+QXkjBNQJk7w3z03qOhNH6sDK1+04Bvh3o8Tl+HYw1CjD+HjP/C38rx6V37 ogbzW1mXJFe14FokaZG4/OhS6RXzvE9Sm4uJkh5mGLjlZJpCdjX0YcZrVKtyOwJrutEi WK8yKe1EszrQxDtj+Wny0I4uc5KpDaByU3nkqzr9iYybZd19mZ3YAqnoDd6qBxSJA24D lIJyQtDUAueRErlISlVErYYRRLHR/DckFMYVQAm/IrJzydBtHHBZB6XGKRQphm9ouds7 IMbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Lt5xGKR3Z7vKxq8vzU4efggY71T1A412lzm5UN/xys0=; b=r86uNy+XkK/uMzlc1ZbMspl9hguInDZyaUqfiegFARwhhjbGkg6QTyqwSFzCCODYcm eJiSOLCE3Wu1C+An8wCdL8/RvUKhqnrZzgo1/uEZ6xrPt1ECtuqyiFiwTt9oHPCWmDl5 gZDn++Hatp22JRifG8xfZkf3bu96zaseVdN3YAyuYQqElvTcVF5PtTrDmfDqXOm6/58w G+ErHVSObXGRi8YkK3qjJpvk6sfv7xEqCVc+070Ne6wmxTOQXchreMXq4YIw4FHNI40d jfvP8VkQyVvYBvhQDprJ8LBTKFN7TmRkU9AZt5sJrQgDTqTeJ25+7BawQLKQrQTn1Ijg QgiQ== X-Gm-Message-State: AOAM530AgE2tRzwQeaEAoILiWIoa8Gusou1FcbPERAYGGfmx4gGIEfaK oy2/2usgjqHKclNf4r3YK/HEpH3Giy4= X-Google-Smtp-Source: ABdhPJyKtC0wJOhgtiTvoxet/OL5QZmCmKn1SCgfRk4yVv2acdd/sty87VeYfZT4QYZc/tVGzzb8lQ== X-Received: by 2002:a17:902:b213:: with SMTP id t19mr4133411plr.100.1644443765304; Wed, 09 Feb 2022 13:56:05 -0800 (PST) Received: from localhost.localdomain (154.red-83-50-83.dynamicip.rima-tde.net. [83.50.83.154]) by smtp.gmail.com with ESMTPSA id v17sm19857363pfm.10.2022.02.09.13.56.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:05 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 09/15] target: Use forward declared type instead of structure type Date: Wed, 9 Feb 2022 22:54:40 +0100 Message-Id: <20220209215446.58402-10-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= The CPU / CPU state are forward declared. $ git grep -E 'struct [A-Za-z]+CPU\ \*' target/arm/hvf_arm.h:16:void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); target/openrisc/cpu.h:234: int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, target/openrisc/cpu.h:238: int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, $ git grep -E 'struct CPU[A-Za-z]+State\ \*' target/mips/internal.h:137: int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, target/mips/internal.h:139: void (*helper_tlbwi)(struct CPUMIPSState *env); target/mips/internal.h:140: void (*helper_tlbwr)(struct CPUMIPSState *env); target/mips/internal.h:141: void (*helper_tlbp)(struct CPUMIPSState *env); target/mips/internal.h:142: void (*helper_tlbr)(struct CPUMIPSState *env); target/mips/internal.h:143: void (*helper_tlbinv)(struct CPUMIPSState *env); target/mips/internal.h:144: void (*helper_tlbinvf)(struct CPUMIPSState *env); target/xtensa/cpu.h:347: struct CPUXtensaState *env; Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/hvf_arm.h | 2 +- target/mips/internal.h | 14 +++++++------- target/openrisc/cpu.h | 4 ++-- target/xtensa/cpu.h | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea238cff83..9a9d1a0bf5 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -13,6 +13,6 @@ #include "cpu.h" -void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); #endif diff --git a/target/mips/internal.h b/target/mips/internal.h index f705d6bfa6..ac6e03e2f2 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -134,14 +134,14 @@ struct r4k_tlb_t { struct CPUMIPSTLBContext { uint32_t nb_tlb; uint32_t tlb_in_use; - int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, + int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type); - void (*helper_tlbwi)(struct CPUMIPSState *env); - void (*helper_tlbwr)(struct CPUMIPSState *env); - void (*helper_tlbp)(struct CPUMIPSState *env); - void (*helper_tlbr)(struct CPUMIPSState *env); - void (*helper_tlbinv)(struct CPUMIPSState *env); - void (*helper_tlbinvf)(struct CPUMIPSState *env); + void (*helper_tlbwi)(CPUMIPSState *env); + void (*helper_tlbwr)(CPUMIPSState *env); + void (*helper_tlbp)(CPUMIPSState *env); + void (*helper_tlbr)(CPUMIPSState *env); + void (*helper_tlbinv)(CPUMIPSState *env); + void (*helper_tlbinvf)(CPUMIPSState *env); union { struct { r4k_tlb_t tlb[MIPS_TLB_MAX]; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index ee069b080c..5711591520 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -231,11 +231,11 @@ typedef struct CPUOpenRISCTLBContext { OpenRISCTLBEntry itlb[TLB_SIZE]; OpenRISCTLBEntry dtlb[TLB_SIZE]; - int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, + int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw); - int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, + int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 02143f2f77..f2165b17e2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -344,7 +344,7 @@ typedef struct XtensaGdbRegmap { } XtensaGdbRegmap; typedef struct XtensaCcompareTimer { - struct CPUXtensaState *env; + CPUXtensaState *env; QEMUTimer *timer; } XtensaCcompareTimer; From patchwork Wed Feb 9 21:54:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01CFAC433EF for ; Wed, 9 Feb 2022 22:24:53 +0000 (UTC) Received: from localhost ([::1]:59120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHvOO-00035e-OZ for qemu-devel@archiver.kernel.org; Wed, 09 Feb 2022 17:24:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHuwp-0006Az-LQ for qemu-devel@nongnu.org; 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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id h25sm19246470pfn.208.2022.02.09.13.56.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:13 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 10/15] target: Use CPUArchState as interface to target-specific CPU state Date: Wed, 9 Feb 2022 22:54:41 +0100 Message-Id: <20220209215446.58402-11-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/exec/poison.h | 2 -- include/hw/core/cpu.h | 2 +- include/qemu/typedefs.h | 1 + target/alpha/cpu.h | 7 ++----- target/arm/cpu.h | 3 +-- target/avr/cpu.h | 7 ++----- target/cris/cpu.h | 3 +-- target/hexagon/cpu.h | 8 ++------ target/hppa/cpu.h | 8 ++------ target/i386/cpu.h | 3 +-- target/m68k/cpu.h | 3 +-- target/microblaze/cpu.h | 5 ++--- target/mips/cpu.h | 6 ++---- target/nios2/cpu.h | 4 ++-- target/openrisc/cpu.h | 3 +-- target/ppc/cpu-qom.h | 2 +- target/ppc/cpu.h | 3 +-- target/riscv/cpu.h | 5 ++--- target/rx/cpu-qom.h | 2 -- target/rx/cpu.h | 2 +- target/s390x/cpu-qom.h | 4 ++-- target/s390x/cpu.h | 3 +-- target/sh4/cpu.h | 3 +-- target/sparc/cpu.h | 5 ++--- target/tricore/cpu.h | 6 ++---- target/xtensa/cpu.h | 7 +++---- 26 files changed, 37 insertions(+), 70 deletions(-) diff --git a/include/exec/poison.h b/include/exec/poison.h index 7ad4ad18e8..7c5c02f03f 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -51,8 +51,6 @@ #pragma GCC poison TARGET_PAGE_BITS #pragma GCC poison TARGET_PAGE_ALIGN -#pragma GCC poison CPUArchState - #pragma GCC poison CPU_INTERRUPT_HARD #pragma GCC poison CPU_INTERRUPT_EXITTB #pragma GCC poison CPU_INTERRUPT_HALT diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3f2b681281..c9d41e4ece 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -340,7 +340,7 @@ struct CPUState { AddressSpace *as; MemoryRegion *memory; - void *env_ptr; /* CPUArchState */ + CPUArchState *env_ptr; IcountDecr *icount_decr_ptr; /* Accessed in parallel; all accesses must be atomic */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index ee60eb3de4..c6f692b0dd 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -39,6 +39,7 @@ typedef struct CompatProperty CompatProperty; typedef struct CoMutex CoMutex; typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUAddressSpace CPUAddressSpace; +typedef struct CPUArchState CPUArchState; typedef struct CPUState CPUState; typedef struct DeviceListener DeviceListener; typedef struct DeviceState DeviceState; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e819211503..cfd17fd265 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -197,9 +197,7 @@ enum { #define MMU_USER_IDX 1 #define MMU_PHYS_IDX 2 -typedef struct CPUAlphaState CPUAlphaState; - -struct CPUAlphaState { +typedef struct CPUArchState { uint64_t ir[31]; float64 fir[31]; uint64_t pc; @@ -251,7 +249,7 @@ struct CPUAlphaState { uint32_t features; uint32_t amask; int implver; -}; +} CPUAlphaState; /** * AlphaCPU: @@ -285,7 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #define cpu_list alpha_cpu_list -typedef CPUAlphaState CPUArchState; typedef AlphaCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6a4d50e82..a95a070647 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -232,7 +232,7 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; -typedef struct CPUARMState { +typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -3410,7 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) } } -typedef CPUARMState CPUArchState; typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/avr/cpu.h b/target/avr/cpu.h index dceacf3cd7..e4a990556b 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -108,9 +108,7 @@ typedef enum AVRFeature { AVR_FEATURE_RAMPZ, } AVRFeature; -typedef struct CPUAVRState CPUAVRState; - -struct CPUAVRState { +typedef struct CPUArchState { uint32_t pc_w; /* 0x003fffff up to 22 bits */ uint32_t sregC; /* 0x00000001 1 bit */ @@ -137,7 +135,7 @@ struct CPUAVRState { bool fullacc; /* CPU/MEM if true MEM only otherwise */ uint64_t features; -}; +} CPUAVRState; /** * AVRCPU: @@ -247,7 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -typedef CPUAVRState CPUArchState; typedef AVRCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/cris/cpu.h b/target/cris/cpu.h index b445b194ea..763d4f882e 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -105,7 +105,7 @@ typedef struct { uint32_t lo; } TLBSet; -typedef struct CPUCRISState { +typedef struct CPUArchState { uint32_t regs[16]; /* P0 - P15 are referred to as special registers in the docs. */ uint32_t pregs[16]; @@ -265,7 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 -typedef CPUCRISState CPUArchState; typedef CRISCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 58a0d3870b..25c67e43a2 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -18,9 +18,6 @@ #ifndef HEXAGON_CPU_H #define HEXAGON_CPU_H -/* Forward declaration needed by some of the header files */ -typedef struct CPUHexagonState CPUHexagonState; - #include "fpu/softfloat-types.h" #include "exec/cpu-defs.h" @@ -75,7 +72,7 @@ typedef struct { /* Maximum number of vector temps in a packet */ #define VECTOR_TEMPS_MAX 4 -struct CPUHexagonState { +typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; target_ulong branch_taken; @@ -129,7 +126,7 @@ struct CPUHexagonState { target_ulong vstore_pending[VSTORES_MAX]; bool vtcm_pending; VTCMStoreLog vtcm_log; -}; +} CPUHexagonState; #define HEXAGON_CPU_CLASS(klass) \ OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU) @@ -180,7 +177,6 @@ static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) #endif } -typedef struct CPUHexagonState CPUArchState; typedef HexagonCPU ArchCPU; void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 93c119532a..d36e5c170c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -138,8 +138,6 @@ #define CR_IPSW 22 #define CR_EIRR 23 -typedef struct CPUHPPAState CPUHPPAState; - #if TARGET_REGISTER_BITS == 32 typedef uint32_t target_ureg; typedef int32_t target_sreg; @@ -168,7 +166,7 @@ typedef struct { unsigned access_id : 16; } hppa_tlb_entry; -struct CPUHPPAState { +typedef struct CPUArchState { target_ureg gr[32]; uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ @@ -207,7 +205,7 @@ struct CPUHPPAState { /* ??? We should use a more intelligent data structure. */ hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; uint32_t tlb_last; -}; +} CPUHPPAState; /** * HPPACPU: @@ -225,8 +223,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; - -typedef CPUHPPAState CPUArchState; typedef HPPACPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9911d7c871..31ae748570 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1429,7 +1429,7 @@ typedef struct HVFX86LazyFlags { target_ulong auxbits; } HVFX86LazyFlags; -typedef struct CPUX86State { +typedef struct CPUArchState { /* standard registers */ target_ulong regs[CPU_NB_REGS]; target_ulong eip; @@ -2072,7 +2072,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env) #define CC_SRC2 (env->cc_src2) #define CC_OP (env->cc_op) -typedef CPUX86State CPUArchState; typedef X86CPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index a3423729ef..0245398230 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -79,7 +79,7 @@ typedef CPU_LDoubleU FPReg; -typedef struct CPUM68KState { +typedef struct CPUArchState { uint32_t dregs[8]; uint32_t aregs[8]; uint32_t pc; @@ -574,7 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); -typedef CPUM68KState CPUArchState; typedef M68kCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e9cd0b88de..acfd35d3f7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -24,7 +24,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -typedef struct CPUMBState CPUMBState; +typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif @@ -239,7 +239,7 @@ typedef struct CPUMBState CPUMBState; #define USE_NON_SECURE_M_AXI_DC_MASK 0x4 #define USE_NON_SECURE_M_AXI_IC_MASK 0x8 -struct CPUMBState { +struct CPUArchState { uint32_t bvalue; /* TCG temporary, only valid during a TB */ uint32_t btarget; /* Full resolved branch destination */ @@ -394,7 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 56b1cbd091..d4f5d7099a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -524,8 +524,7 @@ struct TCState { }; struct MIPSITUState; -typedef struct CPUMIPSState CPUMIPSState; -struct CPUMIPSState { +typedef struct CPUArchState { TCState active_tc; CPUMIPSFPUContext active_fpu; @@ -1161,7 +1160,7 @@ struct CPUMIPSState { QEMUTimer *timer; /* Internal timer */ target_ulong exception_base; /* ExceptionBase input to the core */ uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ -}; +} CPUMIPSState; /** * MIPSCPU: @@ -1218,7 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) return hflags_mmu_index(env->hflags); } -typedef CPUMIPSState CPUArchState; typedef MIPSCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d2ba0c5bbd..629b9e2301 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -25,7 +25,7 @@ #include "hw/core/cpu.h" #include "qom/object.h" -typedef struct CPUNios2State CPUNios2State; +typedef struct CPUArchState CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif @@ -155,7 +155,7 @@ struct Nios2CPUClass { #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 -struct CPUNios2State { +struct CPUArchState { uint32_t regs[NUM_CORE_REGS]; #if !defined(CONFIG_USER_ONLY) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 5711591520..a218e49f0e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -242,7 +242,7 @@ typedef struct CPUOpenRISCTLBContext { } CPUOpenRISCTLBContext; #endif -typedef struct CPUOpenRISCState { +typedef struct CPUArchState { target_ulong shadow_gpr[16][32]; /* Shadow registers */ target_ulong pc; /* Program counter */ @@ -348,7 +348,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU -typedef CPUOpenRISCState CPUArchState; typedef OpenRISCCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 99a6b509af..87ea91ef9c 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -32,7 +32,7 @@ OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) -typedef struct CPUPPCState CPUPPCState; +typedef struct CPUArchState CPUPPCState; typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_dcr_t ppc_dcr_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index dcd83b503c..55ae99e1b8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1080,7 +1080,7 @@ struct ppc_radix_page_info { #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 -struct CPUPPCState { +struct CPUArchState { /* Most commonly used resources during translated code execution first */ target_ulong gpr[32]; /* general purpose registers */ target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */ @@ -1476,7 +1476,6 @@ void ppc_compat_add_property(Object *obj, const char *name, uint32_t *compat_pvr, const char *basedesc); #endif /* defined(TARGET_PPC64) */ -typedef CPUPPCState CPUArchState; typedef PowerPCCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 55635d68d5..79144ddc24 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,7 +97,7 @@ enum { #define MAX_RISCV_PMPS (16) -typedef struct CPURISCVState CPURISCVState; +typedef struct CPUArchState CPURISCVState; #if !defined(CONFIG_USER_ONLY) #include "pmp.h" @@ -112,7 +112,7 @@ FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) -struct CPURISCVState { +struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ uint64_t fpr[32]; /* assume both F and D extensions */ @@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_MSTATUS_FS MSTATUS_FS #define TB_FLAGS_MSTATUS_VS MSTATUS_VS -typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 7310558e0c..f918c46b00 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -45,6 +45,4 @@ struct RXCPUClass { DeviceReset parent_reset; }; -#define CPUArchState struct CPURXState - #endif diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 58adf9edf6..0f3d9d5bd9 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -65,7 +65,7 @@ enum { NUM_REGS = 16, }; -typedef struct CPURXState { +typedef struct CPUArchState { /* CPU registers */ uint32_t regs[NUM_REGS]; /* general registers */ uint32_t psw_o; /* O bit of status register */ diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 9f3a0d86c5..04d5b3012c 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -31,6 +31,8 @@ OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass, typedef struct S390CPUModel S390CPUModel; typedef struct S390CPUDef S390CPUDef; +typedef struct CPUArchState CPUS390XState; + typedef enum cpu_reset_type { S390_CPU_RESET_NORMAL, S390_CPU_RESET_INITIAL, @@ -63,6 +65,4 @@ struct S390CPUClass { void (*reset)(CPUState *cpu, cpu_reset_type type); }; -typedef struct CPUS390XState CPUS390XState; - #endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a75e559134..b668c1b0c7 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -51,7 +51,7 @@ typedef struct PSW { uint64_t addr; } PSW; -struct CPUS390XState { +struct CPUArchState { uint64_t regs[16]; /* GP registers */ /* * The floating point registers are part of the vector registers. @@ -840,7 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); -typedef CPUS390XState CPUArchState; typedef S390CPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index fb9dd9db2f..9a89d2d038 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -130,7 +130,7 @@ typedef struct memory_content { struct memory_content *next; } memory_content; -typedef struct CPUSH4State { +typedef struct CPUArchState { uint32_t flags; /* general execution flags */ uint32_t gregs[24]; /* general registers */ float32 fregs[32]; /* floating point registers */ @@ -264,7 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) } } -typedef CPUSH4State CPUArchState; typedef SuperHCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5a7f1ed5d6..938efb72bf 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -420,7 +420,7 @@ struct CPUTimer typedef struct CPUTimer CPUTimer; -typedef struct CPUSPARCState CPUSPARCState; +typedef struct CPUArchState CPUSPARCState; #if defined(TARGET_SPARC64) typedef union { uint64_t mmuregs[16]; @@ -439,7 +439,7 @@ typedef union { }; } SparcV9MMU; #endif -struct CPUSPARCState { +struct CPUArchState { target_ulong gregs[8]; /* general registers */ target_ulong *regwptr; /* pointer to current register window */ target_ulong pc; /* program counter */ @@ -743,7 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) #endif } -typedef CPUSPARCState CPUArchState; typedef SPARCCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c461387e71..398d5076be 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -28,8 +28,7 @@ struct tricore_boot_info; typedef struct tricore_def_t tricore_def_t; -typedef struct CPUTriCoreState CPUTriCoreState; -struct CPUTriCoreState { +typedef struct CPUArchState { /* GPR Register */ uint32_t gpr_a[16]; uint32_t gpr_d[16]; @@ -189,7 +188,7 @@ struct CPUTriCoreState { const tricore_def_t *cpu_model; void *irq[8]; struct QEMUTimer *timer; /* Internal timer */ -}; +} CPUTriCoreState; /** * TriCoreCPU: @@ -369,7 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) return 0; } -typedef CPUTriCoreState CPUArchState; typedef TriCoreCPU ArchCPU; #include "exec/cpu-all.h" diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f2165b17e2..4496325970 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -306,7 +306,7 @@ typedef enum { INTTYPE_MAX } interrupt_type; -struct CPUXtensaState; +typedef struct CPUArchState CPUXtensaState; typedef struct xtensa_tlb_entry { uint32_t vaddr; @@ -506,7 +506,7 @@ enum { }; #endif -typedef struct CPUXtensaState { +struct CPUArchState { const XtensaConfig *config; uint32_t regs[16]; uint32_t pc; @@ -545,7 +545,7 @@ typedef struct CPUXtensaState { /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; -} CPUXtensaState; +}; /** * XtensaCPU: @@ -722,7 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 -typedef CPUXtensaState CPUArchState; typedef XtensaCPU ArchCPU; #include "exec/cpu-all.h" From patchwork Wed Feb 9 21:54:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E4E4C433EF for ; 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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id mq3sm7630407pjb.4.2022.02.09.13.56.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:21 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 11/15] target: Use ArchCPU as interface to target CPU Date: Wed, 9 Feb 2022 22:54:42 +0100 Message-Id: <20220209215446.58402-12-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ArchCPU is our interface with target-specific code. Use it as a forward-declared opaque pointer (abstract type), having its structure defined by each target. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/typedefs.h | 1 + target/alpha/cpu-qom.h | 4 +++- target/alpha/cpu.h | 4 +--- target/arm/cpu-qom.h | 4 +++- target/arm/cpu.h | 2 -- target/avr/cpu-qom.h | 4 +++- target/avr/cpu.h | 6 ++---- target/cris/cpu-qom.h | 4 +++- target/cris/cpu.h | 4 +--- target/hexagon/cpu.h | 2 +- target/hppa/cpu-qom.h | 4 +++- target/hppa/cpu.h | 4 +--- target/i386/cpu-qom.h | 4 +++- target/i386/cpu.h | 4 +--- target/m68k/cpu-qom.h | 4 +++- target/m68k/cpu.h | 4 +--- target/microblaze/cpu-qom.h | 4 +++- target/microblaze/cpu.h | 6 +++--- target/mips/cpu-qom.h | 4 +++- target/mips/cpu.h | 4 +--- target/nios2/cpu.h | 4 ++-- target/openrisc/cpu.h | 11 ++++------- target/ppc/cpu-qom.h | 4 +++- target/ppc/cpu.h | 4 +--- target/riscv/cpu.h | 5 ++--- target/rx/cpu-qom.h | 4 +++- target/rx/cpu.h | 4 +--- target/s390x/cpu-qom.h | 4 +++- target/s390x/cpu.h | 4 +--- target/sh4/cpu-qom.h | 4 +++- target/sh4/cpu.h | 4 +--- target/sparc/cpu-qom.h | 4 +++- target/sparc/cpu.h | 4 +--- target/tricore/cpu-qom.h | 4 +++- target/tricore/cpu.h | 4 +--- target/xtensa/cpu-qom.h | 4 +++- target/xtensa/cpu.h | 4 +--- 37 files changed, 76 insertions(+), 77 deletions(-) diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index c6f692b0dd..c564f54c11 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -26,6 +26,7 @@ typedef struct AddressSpace AddressSpace; typedef struct AioContext AioContext; typedef struct Aml Aml; typedef struct AnnounceTimer AnnounceTimer; +typedef struct ArchCPU ArchCPU; typedef struct BdrvDirtyBitmap BdrvDirtyBitmap; typedef struct BdrvDirtyBitmapIter BdrvDirtyBitmapIter; typedef struct BlockBackend BlockBackend; diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index 7bb9173c57..6fd2dec1a7 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -25,7 +25,9 @@ #define TYPE_ALPHA_CPU "alpha-cpu" -OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass, +typedef struct ArchCPU AlphaCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, AlphaCPUClass, ALPHA_CPU) /** diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index cfd17fd265..58f00b7814 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -257,7 +257,7 @@ typedef struct CPUArchState { * * An Alpha CPU. */ -struct AlphaCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -283,8 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #define cpu_list alpha_cpu_list -typedef AlphaCPU ArchCPU; - #include "exec/cpu-all.h" enum { diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index a22bd506d0..b0a0724e8c 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -27,7 +27,9 @@ struct arm_boot_info; #define TYPE_ARM_CPU "arm-cpu" -OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass, +typedef struct ArchCPU ARMCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, ARMCPUClass, ARM_CPU) #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a95a070647..a137c564c4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) } } -typedef ARMCPU ArchCPU; - #include "exec/cpu-all.h" /* diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index 14e5b3ce72..e212cac0b5 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -26,7 +26,9 @@ #define TYPE_AVR_CPU "avr-cpu" -OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass, +typedef struct ArchCPU AVRCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, AVRCPUClass, AVR_CPU) /** diff --git a/target/avr/cpu.h b/target/avr/cpu.h index e4a990556b..55497f851d 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -143,14 +143,14 @@ typedef struct CPUArchState { * * A AVR CPU. */ -typedef struct AVRCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ CPUNegativeOffsetState neg; CPUAVRState env; -} AVRCPU; +}; extern const struct VMStateDescription vms_avr_cpu; @@ -245,8 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -typedef AVRCPU ArchCPU; - #include "exec/cpu-all.h" #endif /* !defined (QEMU_AVR_CPU_H) */ diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 2596edc7e3..89f1116020 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -25,7 +25,9 @@ #define TYPE_CRIS_CPU "cris-cpu" -OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass, +typedef struct ArchCPU CRISCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, CRISCPUClass, CRIS_CPU) /** diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 763d4f882e..e6776f25b1 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -173,7 +173,7 @@ typedef struct CPUArchState { * * A CRIS CPU. */ -struct CRISCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -265,8 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 -typedef CRISCPU ArchCPU; - #include "exec/cpu-all.h" static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc, diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 25c67e43a2..4dce40a360 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -143,7 +143,7 @@ typedef struct HexagonCPUClass { DeviceReset parent_reset; } HexagonCPUClass; -typedef struct HexagonCPU { +typedef struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index d424f88370..c846c18304 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -25,7 +25,9 @@ #define TYPE_HPPA_CPU "hppa-cpu" -OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass, +typedef struct ArchCPU HPPACPU; + +OBJECT_DECLARE_TYPE(ArchCPU, HPPACPUClass, HPPA_CPU) /** diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d36e5c170c..4cc936b6bf 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -213,7 +213,7 @@ typedef struct CPUArchState { * * An HPPA CPU. */ -struct HPPACPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -223,8 +223,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; -typedef HPPACPU ArchCPU; - #include "exec/cpu-all.h" static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index f9923cee04..db33cf6762 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -30,7 +30,9 @@ #define TYPE_X86_CPU "i386-cpu" #endif -OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass, +typedef struct ArchCPU X86CPU; + +OBJECT_DECLARE_TYPE(ArchCPU, X86CPUClass, X86_CPU) typedef struct X86CPUModel X86CPUModel; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 31ae748570..b5d1ff5956 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1705,7 +1705,7 @@ struct kvm_msrs; * * An x86 CPU. */ -struct X86CPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -2072,8 +2072,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env) #define CC_SRC2 (env->cc_src2) #define CC_OP (env->cc_op) -typedef X86CPU ArchCPU; - #include "exec/cpu-all.h" #include "svm.h" diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index 1ceb160ecb..c2c0736b3b 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -25,7 +25,9 @@ #define TYPE_M68K_CPU "m68k-cpu" -OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass, +typedef struct ArchCPU M68kCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, M68kCPUClass, M68K_CPU) /* diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 0245398230..872e8ce637 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -156,7 +156,7 @@ typedef struct CPUArchState { * * A Motorola 68k CPU. */ -struct M68kCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -574,8 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); -typedef M68kCPU ArchCPU; - #include "exec/cpu-all.h" /* TB flags */ diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index e520eefb12..8f11fe4d73 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -25,7 +25,9 @@ #define TYPE_MICROBLAZE_CPU "microblaze-cpu" -OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, +typedef struct ArchCPU MicroBlazeCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, MicroBlazeCPUClass, MICROBLAZE_CPU) /** diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index acfd35d3f7..d511b6b877 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -25,6 +25,8 @@ #include "fpu/softfloat-types.h" typedef struct CPUArchState CPUMBState; +typedef struct ArchCPU MicroBlazeCPU; + #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif @@ -339,7 +341,7 @@ typedef struct { * * A MicroBlaze CPU. */ -struct MicroBlazeCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; @@ -394,8 +396,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -typedef MicroBlazeCPU ArchCPU; - #include "exec/cpu-all.h" /* Ensure there is no overlap between the two masks. */ diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index dda0c911fa..41f3d01a80 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -29,7 +29,9 @@ #define TYPE_MIPS_CPU "mips-cpu" #endif -OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass, +typedef struct ArchCPU MIPSCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, MIPSCPUClass, MIPS_CPU) /** diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d4f5d7099a..09e98f64de 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1171,7 +1171,7 @@ typedef struct CPUArchState { * * A MIPS CPU. */ -struct MIPSCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -1217,8 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) return hflags_mmu_index(env->hflags); } -typedef MIPSCPU ArchCPU; - #include "exec/cpu-all.h" /* Exceptions */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 629b9e2301..05def159b1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -32,7 +32,7 @@ typedef struct CPUArchState CPUNios2State; #define TYPE_NIOS2_CPU "nios2-cpu" -OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass, +OBJECT_DECLARE_TYPE(ArchCPU, Nios2CPUClass, NIOS2_CPU) /** @@ -171,7 +171,7 @@ struct CPUArchState { * * A Nios2 CPU. */ -struct Nios2CPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index a218e49f0e..9111b050ad 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,12 +24,11 @@ #include "hw/core/cpu.h" #include "qom/object.h" -/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ -struct OpenRISCCPU; - #define TYPE_OPENRISC_CPU "or1k-cpu" -OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass, +typedef struct ArchCPU OpenRISCCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, OpenRISCCPUClass, OPENRISC_CPU) /** @@ -301,7 +300,7 @@ typedef struct CPUArchState { * * A OpenRISC CPU. */ -struct OpenRISCCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -348,8 +347,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU -typedef OpenRISCCPU ArchCPU; - #include "exec/cpu-all.h" #define TB_FLAGS_SM SR_SM diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 87ea91ef9c..48671b13ac 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -29,7 +29,9 @@ #define TYPE_POWERPC_CPU "powerpc-cpu" #endif -OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass, +typedef struct ArchCPU PowerPCCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, PowerPCCPUClass, POWERPC_CPU) typedef struct CPUArchState CPUPPCState; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 55ae99e1b8..86f021c45d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,7 +1278,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; * * A PowerPC CPU. */ -struct PowerPCCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -1476,8 +1476,6 @@ void ppc_compat_add_property(Object *obj, const char *name, uint32_t *compat_pvr, const char *basedesc); #endif /* defined(TARGET_PPC64) */ -typedef PowerPCCPU ArchCPU; - #include "exec/cpu-all.h" /*****************************************************************************/ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 79144ddc24..5981be47d9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,7 +285,7 @@ struct CPUArchState { uint64_t kvm_timer_frequency; }; -OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, +OBJECT_DECLARE_TYPE(ArchCPU, RISCVCPUClass, RISCV_CPU) /** @@ -309,7 +309,7 @@ struct RISCVCPUClass { * * A RISCV CPU. */ -struct RISCVCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_MSTATUS_FS MSTATUS_FS #define TB_FLAGS_MSTATUS_VS MSTATUS_VS -typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" FIELD(TB_FLAGS, MEM_IDX, 0, 3) diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index f918c46b00..09b59f8e1d 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -26,7 +26,9 @@ #define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n") -OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass, +typedef struct ArchCPU RXCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, RXCPUClass, RX_CPU) /* diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0f3d9d5bd9..b4abd90ccd 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -105,7 +105,7 @@ typedef struct CPUArchState { * * A RX CPU */ -struct RXCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -114,8 +114,6 @@ struct RXCPU { CPURXState env; }; -typedef RXCPU ArchCPU; - #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_RX_CPU diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 04d5b3012c..fe126e6b1d 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -25,7 +25,9 @@ #define TYPE_S390_CPU "s390x-cpu" -OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass, +typedef struct ArchCPU S390CPU; + +OBJECT_DECLARE_TYPE(ArchCPU, S390CPUClass, S390_CPU) typedef struct S390CPUModel S390CPUModel; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b668c1b0c7..c49c8466e7 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,7 +163,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr) * * An S/390 CPU. */ -struct S390CPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -840,8 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); -typedef S390CPU ArchCPU; - #include "exec/cpu-all.h" #endif diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 8903b4b9c7..64be55a924 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -29,7 +29,9 @@ #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r") #define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785") -OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass, +typedef struct ArchCPU SuperHCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, SuperHCPUClass, SUPERH_CPU) /** diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9a89d2d038..c72a30edfd 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -195,7 +195,7 @@ typedef struct CPUArchState { * * A SuperH CPU. */ -struct SuperHCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -264,8 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) } } -typedef SuperHCPU ArchCPU; - #include "exec/cpu-all.h" /* MMU control register */ diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index f33949aaee..d5f90cffd4 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -29,7 +29,9 @@ #define TYPE_SPARC_CPU "sparc-cpu" #endif -OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass, +typedef struct ArchCPU SPARCCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, SPARCCPUClass, SPARC_CPU) typedef struct sparc_def_t sparc_def_t; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 938efb72bf..abb38db674 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -556,7 +556,7 @@ struct CPUArchState { * * A SPARC CPU. */ -struct SPARCCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -743,8 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) #endif } -typedef SPARCCPU ArchCPU; - #include "exec/cpu-all.h" #ifdef TARGET_SPARC64 diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 59bfd01bbc..8259595fe5 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -24,7 +24,9 @@ #define TYPE_TRICORE_CPU "tricore-cpu" -OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass, +typedef struct ArchCPU TriCoreCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, TriCoreCPUClass, TRICORE_CPU) struct TriCoreCPUClass { diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 398d5076be..108d6b8288 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -196,7 +196,7 @@ typedef struct CPUArchState { * * A TriCore CPU. */ -struct TriCoreCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -368,8 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) return 0; } -typedef TriCoreCPU ArchCPU; - #include "exec/cpu-all.h" void cpu_state_reset(CPUTriCoreState *s); diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 41d9859673..c4ee073fc6 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -34,7 +34,9 @@ #define TYPE_XTENSA_CPU "xtensa-cpu" -OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass, +typedef struct ArchCPU XtensaCPU; + +OBJECT_DECLARE_TYPE(ArchCPU, XtensaCPUClass, XTENSA_CPU) typedef struct XtensaConfig XtensaConfig; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4496325970..4515f682aa 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -553,7 +553,7 @@ struct CPUArchState { * * An Xtensa CPU. */ -struct XtensaCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -722,8 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 -typedef XtensaCPU ArchCPU; - #include "exec/cpu-all.h" static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, From patchwork Wed Feb 9 21:54:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22643C433EF for ; Wed, 9 Feb 2022 22:01:18 +0000 (UTC) Received: from localhost ([::1]:49026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHv1Y-00015u-Um for qemu-devel@archiver.kernel.org; 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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id y190sm6703939pfg.212.2022.02.09.13.56.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:29 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [RFC PATCH 12/15] hw/m68k: Restrict M68kCPU type to target/ code Date: Wed, 9 Feb 2022 22:54:43 +0100 Message-Id: <20220209215446.58402-13-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé --- include/hw/m68k/mcf.h | 3 +-- target/m68k/cpu-qom.h | 2 -- target/m68k/cpu.h | 4 ++-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h index 8cbd587bbf..e84fcfb4ca 100644 --- a/include/hw/m68k/mcf.h +++ b/include/hw/m68k/mcf.h @@ -3,7 +3,6 @@ /* Motorola ColdFire device prototypes. */ #include "exec/hwaddr.h" -#include "target/m68k/cpu-qom.h" /* mcf_uart.c */ uint64_t mcf_uart_read(void *opaque, hwaddr addr, @@ -16,7 +15,7 @@ void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chr); 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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id s17sm19987467pfk.156.2022.02.09.13.56.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:37 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [RFC PATCH 13/15] hw/mips: Restrict MIPSCPU type to target/ code Date: Wed, 9 Feb 2022 22:54:44 +0100 Message-Id: <20220209215446.58402-14-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/cpudevs.h | 6 ++---- target/mips/cpu-qom.h | 2 -- target/mips/cpu.h | 4 ++-- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h index f7c9728fa9..6065932b0e 100644 --- a/include/hw/mips/cpudevs.h +++ b/include/hw/mips/cpudevs.h @@ -1,14 +1,12 @@ #ifndef HW_MIPS_CPUDEVS_H #define HW_MIPS_CPUDEVS_H -#include "target/mips/cpu-qom.h" - /* Definitions for MIPS CPU internal devices. */ /* mips_int.c */ -void cpu_mips_irq_init_cpu(MIPSCPU *cpu); +void cpu_mips_irq_init_cpu(ArchCPU *cpu); /* mips_timer.c */ -void cpu_mips_clock_init(MIPSCPU *cpu); +void cpu_mips_clock_init(ArchCPU *cpu); #endif diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 41f3d01a80..666084b09e 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -29,8 +29,6 @@ #define TYPE_MIPS_CPU "mips-cpu" #endif -typedef struct ArchCPU MIPSCPU; - OBJECT_DECLARE_TYPE(ArchCPU, MIPSCPUClass, MIPS_CPU) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 09e98f64de..4aa95d0ce1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1171,7 +1171,7 @@ typedef struct CPUArchState { * * A MIPS CPU. */ -struct ArchCPU { +typedef struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -1187,7 +1187,7 @@ struct ArchCPU { * pipeline clock of the processor, not the issue width of the processor. */ unsigned cp0_count_rate; -}; +} MIPSCPU; void mips_cpu_list(void); From patchwork Wed Feb 9 21:54:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30988C433EF for ; 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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id ot1sm7399170pjb.22.2022.02.09.13.56.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:45 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [RFC PATCH 14/15] hw/sparc: Restrict SPARCCPU type to target/ code Date: Wed, 9 Feb 2022 22:54:45 +0100 Message-Id: <20220209215446.58402-15-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sparc/sparc64.h | 4 +--- target/sparc/cpu-qom.h | 2 -- target/sparc/cpu.h | 4 ++-- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/include/hw/sparc/sparc64.h b/include/hw/sparc/sparc64.h index 4ced36fb5a..605ae4448c 100644 --- a/include/hw/sparc/sparc64.h +++ b/include/hw/sparc/sparc64.h @@ -1,11 +1,9 @@ #ifndef HW_SPARC_SPARC64_H #define HW_SPARC_SPARC64_H -#include "target/sparc/cpu-qom.h" - #define IVEC_MAX 0x40 -SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr); +ArchCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr); void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level); diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index d5f90cffd4..36ffffcadd 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -29,8 +29,6 @@ #define TYPE_SPARC_CPU "sparc-cpu" #endif -typedef struct ArchCPU SPARCCPU; - OBJECT_DECLARE_TYPE(ArchCPU, SPARCCPUClass, SPARC_CPU) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index abb38db674..8452a62ea8 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -556,14 +556,14 @@ struct CPUArchState { * * A SPARC CPU. */ -struct ArchCPU { +typedef struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ CPUNegativeOffsetState neg; CPUSPARCState env; -}; +} SPARCCPU; #ifndef CONFIG_USER_ONLY From patchwork Wed Feb 9 21:54:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12740977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5E7CC433EF for ; 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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id 30sm14716844pgq.39.2022.02.09.13.56.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:53 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [RFC PATCH 15/15] hw/sh4: Restrict SuperHCPU type to target/ code Date: Wed, 9 Feb 2022 22:54:46 +0100 Message-Id: <20220209215446.58402-16-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sh4/sh.h | 3 +-- target/sh4/cpu-qom.h | 2 -- target/sh4/cpu.h | 4 ++-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index ec716cdd45..a4245399d5 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -28,7 +28,6 @@ #define QEMU_HW_SH_H #include "hw/sh4/sh_intc.h" -#include "target/sh4/cpu-qom.h" #define A7ADDR(x) ((x) & 0x1fffffff) #define P4ADDR(x) ((x) | 0xe0000000) @@ -36,7 +35,7 @@ /* sh7750.c */ struct SH7750State; -struct SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem); +struct SH7750State *sh7750_init(ArchCPU *cpu, MemoryRegion *sysmem); typedef struct { /* The callback will be triggered if any of the designated lines change */ diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 64be55a924..d186ad40fa 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -29,8 +29,6 @@ #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r") #define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785") -typedef struct ArchCPU SuperHCPU; - OBJECT_DECLARE_TYPE(ArchCPU, SuperHCPUClass, SUPERH_CPU) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index c72a30edfd..8e49163fb3 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -195,14 +195,14 @@ typedef struct CPUArchState { * * A SuperH CPU. */ -struct ArchCPU { +typedef struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ CPUNegativeOffsetState neg; CPUSH4State env; -}; +} SuperHCPU; void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);