From patchwork Thu Feb 10 00:38:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C252C433FE for ; Thu, 10 Feb 2022 00:39:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A4A310E6DF; Thu, 10 Feb 2022 00:39:13 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D47710E172; Thu, 10 Feb 2022 00:39:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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09 Feb 2022 16:39:10 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 16:38:59 -0800 Message-Id: <20220210003904.1055898-2-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210003904.1055898-1-michael.cheng@intel.com> References: <20220210003904.1055898-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 1/6] drm: Add arch arm64 for drm_clflush_virt_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc performs a flush by first performing a clean, follow by an invalidation operation. v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h Signed-off-by: Michael Cheng --- drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index f19d9acbe959..f167bc19afb9 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -28,6 +28,7 @@ * Authors: Thomas Hellström */ +#include #include #include #include @@ -176,6 +177,10 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); #else pr_err("Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1); From patchwork Thu Feb 10 00:39:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09CE1C433FE for ; Thu, 10 Feb 2022 00:39:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8AF3910E17A; Thu, 10 Feb 2022 00:39:14 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F6F610E17A; Thu, 10 Feb 2022 00:39:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644453552; x=1675989552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0faIJeanSVg4TVsukZep2SH9zNSBXKIPlWiirFMZ1bw=; b=FhD4IfVSRjLYmCusLA77+MsgPDcGDeTum4zvxUDgrWw/Qyxil26HuxCL vD24mEp0QPneM8II2f8CUHrFellGOOH4MqW3KqYbvr6OmQupil2DLvL0I L5AT0yGS6D4i6lsPzKRzoPOt6lQg/fAoq/kqXA4GIzWzH+otDXzHjoAlZ NRP5G8VWQxIOeqDu4+juNfEgFnRdbLcuTkDyibmnMz0AXOWmI88gBGXUd vpZtER5Fb2XglTSLVZR+5Z8aG6UCkPQG2teanrwro9auJsT53XyHPHrQt gcSrfvEw7W6tB8BLKjm6gkpvQ7DvsZsWGgDZLRbj7DA/lkYXmnMVtt2Eb g==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="230023279" X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="230023279" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:11 -0800 X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="482544756" Received: from sroy1-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.85.186]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:11 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 16:39:00 -0800 Message-Id: <20220210003904.1055898-3-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210003904.1055898-1-michael.cheng@intel.com> References: <20220210003904.1055898-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 2/6] drm/i915/gt: Re-work intel_write_status_page X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures. Signed-off-by: Michael Cheng --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 0e353d8c2bc8..986777c2430d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * of extra paranoia to try and ensure that the HWS takes the value * we give and that it doesn't end up trapped inside the CPU! */ - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - mb(); - clflush(&engine->status_page.addr[reg]); - engine->status_page.addr[reg] = value; - clflush(&engine->status_page.addr[reg]); - mb(); - } else { - WRITE_ONCE(engine->status_page.addr[reg], value); - } + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); + WRITE_ONCE(engine->status_page.addr[reg], value); + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); } /* From patchwork Thu Feb 10 00:39:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4773C433EF for ; Thu, 10 Feb 2022 00:39:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 07F9810E6A2; Thu, 10 Feb 2022 00:39:14 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6717A10E6A2; Thu, 10 Feb 2022 00:39:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644453552; x=1675989552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xFYLaPepw2T34Ec0qGtoebNynt7IRfx+By6ZnIjAJe8=; b=SxR3Nwwd5ZOx4LECRHzLDQCAMvy9rytRKdeHmslSuRZYRfmuehGCbPZl wV7plMQcs+omK1/GiBN+l6IIzgZqNUMr36+KG/EGemcndhu/OUtkSt8Q7 oTpAw3/ibeZdA3jMk7cE6bpDEm8AqO9t3CXFCHTB/xIELS7bK2pOeutg+ YFnkDu7GVHO2m0efp//r/AnXxAFqMU9LduO39zuu8qbjdNtJ7NRGSTzQu LXRUMzriI02dH86DmXyCK7wqQOSXsa+YrjJIFcyZX7ACBXEf1TfsyEo6B 0BY7ylOHog8GAkz1P6JYHzAuxe+bkyCO75B0ss54GiRGQK39Ya7tOTkCb A==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="230023280" X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="230023280" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:11 -0800 X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="482544760" Received: from sroy1-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.85.186]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:11 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 16:39:01 -0800 Message-Id: <20220210003904.1055898-4-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210003904.1055898-1-michael.cheng@intel.com> References: <20220210003904.1055898-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 3/6] drm/i915/gt: Drop invalidate_csb_entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Drop invalidate_csb_entries and directly call drm_clflush_virt_range. This allows for one less function call, and prevent complier errors when building for non-x86 architectures. v2(Michael Cheng): Drop invalidate_csb_entries function and directly invoke drm_clflush_virt_range. Thanks to Tvrtko for the sugguestion. v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range. Thanks to Tvrtko for pointing this out. Signed-off-by: Michael Cheng --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 9bb7c863172f..28f2581d3046 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists, return inactive; } -static void invalidate_csb_entries(const u64 *first, const u64 *last) -{ - clflush((void *)first); - clflush((void *)last); -} - /* * Starting with Gen12, the status has a new format: * @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) * the wash as hardware, working or not, will need to do the * invalidation before. */ - invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); + drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0])); /* * We assume that any event reflects a change in context flow @@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine) /* Check that the GPU does indeed update the CSB entries! */ memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64)); - invalidate_csb_entries(&execlists->csb_status[0], - &execlists->csb_status[reset_value]); + drm_clflush_virt_range(&execlists->csb_status[0], + execlists->csb_size * sizeof(execlists->csb_status[0])); /* Once more for luck and our trusty paranoia */ ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR, From patchwork Thu Feb 10 00:39:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 399BBC433EF for ; Thu, 10 Feb 2022 00:39:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D80110E6AD; Thu, 10 Feb 2022 00:39:15 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7407E10E6AD; Thu, 10 Feb 2022 00:39:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644453552; x=1675989552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n5RKJcp81B88J6tTgVRUp4ooYKldFrNbNiKg6W8kZms=; b=cDMFOZP+YUOzR8r95sMJ0RRz2bHgRva+nflC2liDXAEORFlBcjvhcqQK FvSajTS9VZFUz4LGlSdlfaznhnbIK2E0Hm67eIRuzTDXFQ7hNlpy12F/J gdUA5j1eHJhCO2ba6sPxPyBrB9bBub0FspEwT539fk2/K+hngnrDtw5sz yd8u+oPjVovb9xacpgziBxc/hDg/Egc8ciMuu0AvgWpmzWqYqhWPb3quO 8Kgqehx58uPucomYIorISiPiT2JlKElH9C2mr9DQzgRZUDw2Xi9Mv5NH6 g4Wq5Itj516EbRhP0FY8rKC0SBCas7dFSd59zBOSo0LzArt1ydkIHWwNX w==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="312665908" X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="312665908" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:11 -0800 X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="482544763" Received: from sroy1-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.85.186]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:11 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 16:39:02 -0800 Message-Id: <20220210003904.1055898-5-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210003904.1055898-1-michael.cheng@intel.com> References: <20220210003904.1055898-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 4/6] drm/i915/gt: Re-work reset_csb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use drm_clflush_virt_range instead of directly invoking clflush. This will prevent compiler errors when building for non-x86 architectures. v2(Michael Cheng): Remove extra clflush v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range takes care of it. Signed-off-by: Michael Cheng --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 28f2581d3046..cc561cfae808 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive) { struct intel_engine_execlists * const execlists = &engine->execlists; - mb(); /* paranoia: read the CSB pointers from after the reset */ - clflush(execlists->csb_write); - mb(); + drm_clflush_virt_range(execlists->csb_write, + sizeof(execlists->csb_write)); inactive = process_csb(engine, inactive); /* drain preemption events */ From patchwork Thu Feb 10 00:39:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B7C2C433F5 for ; Thu, 10 Feb 2022 00:39:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A2BB10E6F1; Thu, 10 Feb 2022 00:39:15 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 99C9E10E17A; Thu, 10 Feb 2022 00:39:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644453552; x=1675989552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o6HuYlnP32PX1lqgHE1fsvZCwjUKZXMxGSqa7+v9E8k=; b=kobVVpMubmdODEnbfoJVzeT9wGN+HHm43xaJljlPtdd7s2ZgcSS3n63D BEwxsQJrMZzefbY6exhW2hDPHpKEkwiKPaQEhbpd5ObaMJXdaMSVN9H+2 4oSIvSaTX2xZQS5rFUW9jXz1MEAll9zxNU0/llCkqym+ZtytS4DAuF8lm Z/Voi3Cqjb1Sg3hkdtncI4tDr3GwY6g1UqbmtrMc3sTMaTf7aCA2mskKR HZ0MjR8kYqel7wQ+7pMhaJXsfgsGblo9cgMgdv446rVTqJbSNmWcSnSHu egtQyBWZXmqgvcEbeRPFRsYujZJ/O89A7V6gY9WIBiDiKfhlOb+fsO00X w==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="230023283" X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="230023283" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:12 -0800 X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="482544769" Received: from sroy1-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.85.186]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:12 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 16:39:03 -0800 Message-Id: <20220210003904.1055898-6-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210003904.1055898-1-michael.cheng@intel.com> References: <20220210003904.1055898-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 5/6] drm/i915/: Re-work clflush_write32 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use drm_clflush_virt_range instead of clflushopt and remove the memory barrier, since drm_clflush_virt_range takes care of that. Signed-off-by: Michael Cheng --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 498b458fd784..0854276ff7ba 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma, static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) { if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { - if (flushes & CLFLUSH_BEFORE) { - clflushopt(addr); - mb(); - } + if (flushes & CLFLUSH_BEFORE) + drm_clflush_virt_range(addr, sizeof(addr)); *addr = value; @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) * to ensure ordering of clflush wrt to the system. */ if (flushes & CLFLUSH_AFTER) - clflushopt(addr); + drm_clflush_virt_range(addr, sizeof(addr)); } else *addr = value; } From patchwork Thu Feb 10 00:39:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D9A1C433F5 for ; Thu, 10 Feb 2022 00:39:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A697C10E6C5; Thu, 10 Feb 2022 00:39:14 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id CF8BB10E6C5; Thu, 10 Feb 2022 00:39:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644453552; x=1675989552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dgLlbbEhY5qijXM7qOREhUoDQwP/TPT9aXOmmK5zR9k=; b=XCd7bhgacYHd9uKv9B2U83HblgGpalGYx5LkPynQx0lzuq7esjuuX5nu 4Hmg+iOJ+hVwo4XX9FDkulxU+FMwPw5JoT/j7wl8IEpW/GIAw+4p7tNq6 8+fBJu+qHcpVZkqK9mVRL3U02AOYfebkIAj4jxsqD0fLZEO/uEvGNgD+J W/Qag0RVHLjKmCbqiBX+KLoCTyWhAuog+nQlRT/Pyg8jozh2uZIJ0yZvf IiLTpyp4XeHiRco1oZiIQF3OZp4bClsrfFxaHIjt9nT42SBkM9E5gTETt 8Fm4yOImptnrOGib5TZEPdzuSsr43r6cQfCFEwy/o9EoisUVdmnXXy0mH g==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="230023284" X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="230023284" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:12 -0800 X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="482544774" Received: from sroy1-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.85.186]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 16:39:12 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 16:39:04 -0800 Message-Id: <20220210003904.1055898-7-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210003904.1055898-1-michael.cheng@intel.com> References: <20220210003904.1055898-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 6/6] drm/i915/gt: replace cache_clflush_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Replace all occurance of cache_clflush_range with drm_clflush_virt_range. This will prevent compile errors on non-x86 platforms. Signed-off-by: Michael Cheng --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------ drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index c43e724afa9f..d0999e92621b 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, pd = pdp->entry[gen8_pd_index(idx, 2)]; } - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1))); } } while (1); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); return idx; } @@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, } } while (rem >= page_size && index < I915_PDES); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); /* * Is it safe to mark the 2M block as 64K? -- Either we have @@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, I915_GTT_PAGE_SIZE_2M)))) { vaddr = px_vaddr(pd); vaddr[maybe_64K] |= GEN8_PDE_IPS_64K; - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); page_size = I915_GTT_PAGE_SIZE_64K; /* @@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, for (i = 1; i < index; i += 16) memset64(vaddr + i, encode, 15); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); } } @@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1))); vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags); - clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); + drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); } static int gen8_init_scratch(struct i915_address_space *vm) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index cc561cfae808..bbe33794b34d 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2822,7 +2822,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine); /* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); intel_engine_reset_pinned_contexts(engine); } diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 0d6bbc8c57f2..9b594be9102f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) void *vaddr = __px_vaddr(p); memset64(vaddr, val, count); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); } static void poison_scratch_page(struct drm_i915_gem_object *scratch) diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index 48e6e2f87700..bd474a5123cb 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma, u64 * const vaddr = __px_vaddr(pdma); vaddr[idx] = encoded_entry; - clflush_cache_range(&vaddr[idx], sizeof(u64)); + drm_clflush_virt_range(&vaddr[idx], sizeof(u64)); } void diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index b3a429a92c0d..89020706adc4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine); /* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); intel_engine_reset_pinned_contexts(engine); }