From patchwork Thu Feb 10 07:45:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12741522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC98EC433F5 for ; Thu, 10 Feb 2022 07:49:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7I6TEGQVhi3frc63vtTZdXNwd+8B3HGUeIF4N381uaw=; b=ICeeObA915E/J+ 0rPuQrokKuBk/bfhWqWrWLuItPlxFnoQ7BE7nEGPJZgU8vKxAlum7msNh09BdwqssBap8AUwYUujY +wYTBZOLOgThCtq39NCI0on68YQHEM4aNm9hFRbKLTkYJQyw/otj2oLR2EiI7oQ7FGjMVr/zCBT9n 01bj/zQspIgUYGbQCEriO4m9HcH3RCki/f3wgxn2yQdBC2ODPi1vNUsoMvHGhKdRs7LSkAsFSdOj+ xjQhGoe3+yauQYYQrxlu96z444YWVsl5HDvovbERskCNEGDsP8mBBxju6SnAC3mnZYCFN5D1otiXx o+d6G7c0bj0DJWjkZbJw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nI4Ay-002utP-7o; Thu, 10 Feb 2022 07:47:36 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nI4Av-002usP-Fp for linux-arm-kernel@lists.infradead.org; Thu, 10 Feb 2022 07:47:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644479253; x=1676015253; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=p5j3Riq4rZoEYGYuDL+O+9dYmiRcXLURQv7yhYMS5TU=; b=VmQIKYFGfOBcZlkyYxhIAgg2wwiyNmJV2NofAAblRqfJuelbs/xvVfKr MvJhWLSzNiFIezr4TyyIEszZYI4sPDrHpT37xczcLjj+D1omvenc6SiCi pDy6L/z7LasEry0XIvXPg0jAKpHBbLx2huhLim6IgnHnxaQcSl4Ubiz/n URWBXeUpkDTFskED3rYgCWQWWj+qixF89LJSCz10yGEGDa5XnTct1MW+q +fZCaaXECgefkSwyX+r992/czbiyDzhw6TRLHjS+/nxi/+rZFDoN8v7Xp CaFXmcfGM6xTeD9+eM4bFYjMlfoo86gXgv2CajkNtd7t7oKTQVqOsOy+J w==; IronPort-SDR: fCkB7qWlsJB1wyrTVx4IvHtQx9f+M62Ua5A8rFGAoHUNZW8m4omgDm7Z9Ho3IuJjrCVDSslfb6 WC6UUL5YzxUIOmwLxTuIdj0rcZNbdpOvH+MoNMOKx6fb2FUU3TQAq7yxUDTOxqJtszhcXWrUcl 8ofBh8dzksaznTRTX8w/026LR+gxwSHoTc4hwUsxJMBGqyzyuSTUemgphqw+wk5iFWp7ODOg+Q ERv3DkZmv5aCmdu2Iogzf4nYwqAq983usvHEsy+JZdNEz1m1eiM/heHcZ+eQGsq1NdPSH9HiA7 YE0hREDR8y5H54bQ9TmqWCIE X-IronPort-AV: E=Sophos;i="5.88,358,1635231600"; d="scan'208";a="85274949" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Feb 2022 00:47:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 10 Feb 2022 00:47:31 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 10 Feb 2022 00:47:27 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , Subject: [PATCH 1/2] mfd: dt-bindings: add bindings for lan966 flexcom shared configurations Date: Thu, 10 Feb 2022 13:15:45 +0530 Message-ID: <20220210074546.30669-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220210074546.30669-1-kavyasree.kotagiri@microchip.com> References: <20220210074546.30669-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220209_234733_614832_EE660EBD X-CRM114-Status: UNSURE ( 8.88 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds LAN966 SoC DT bindings documentation for Flexcom Shared and chip-select configurations. Signed-off-by: Kavyasree Kotagiri --- .../devicetree/bindings/mfd/atmel-flexcom.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt index 692300117c64..a76622082228 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt @@ -18,6 +18,15 @@ Required properties: - <2> for SPI - <3> for I2C +Optional properties: +- Flexcom shared configurations: Each flexcom of lan966 SoC has 2 chip selects. + For each chip select, there is a pin configuration register. + The width of the configuration register is 21 because there are 21 shared + pins on each of which the chip select can be mapped. Each bit of the + configuration register represents a different FLEXCOM_SHARED pin. + - lan966x-ss-pin: Should be a flexcom shared pin. + - lan966x-cs: Should be chip select 0 or 1. + Required child: A single available child device of type matching the "atmel,flexcom-mode" property. @@ -41,6 +50,9 @@ flexcom@f8034000 { #size-cells = <1>; ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; + /* Map chip-select index 0 of the flexcom to FLEXCOM_SHARED 9 */ + lan966x-ss-pin = <9>; + lan966x-cs = <0>; spi@400 { compatible = "atmel,at91rm9200-spi"; From patchwork Thu Feb 10 07:45:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12741523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCFEEC433F5 for ; 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d="scan'208";a="85274972" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Feb 2022 00:47:38 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 10 Feb 2022 00:47:37 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 10 Feb 2022 00:47:33 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , Subject: [PATCH 2/2] mfd: atmel-flexcom: Add support for lan966 flexcom shared configurations Date: Thu, 10 Feb 2022 13:15:46 +0530 Message-ID: <20220210074546.30669-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220210074546.30669-1-kavyasree.kotagiri@microchip.com> References: <20220210074546.30669-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220209_234738_769610_1A7F891D X-CRM114-Status: GOOD ( 14.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Each flexcom of LAN966 SoC has 2 chip selects. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri --- drivers/mfd/atmel-flexcom.c | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 559eb4d352b6..b8fc476e411d 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -27,6 +27,12 @@ #define FLEX_MR_OPMODE_MASK (0x3 << FLEX_MR_OPMODE_OFFSET) #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) +#ifdef CONFIG_SOC_LAN966 +/* LAN966 register offsets */ +#define FLEX_SHRD_SS_MASK_0 0x0 +#define FLEX_SHRD_SS_MASK_1 0x4 +#define FLEX_SHRD_MASK 0x1FFFFF +#endif struct atmel_flexcom { void __iomem *base; @@ -39,6 +45,10 @@ static int atmel_flexcom_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct resource *res; struct atmel_flexcom *ddata; +#ifdef CONFIG_SOC_LAN966 + u32 lan966x_ss_pin, lan966x_cs, val; + void __iomem *shared_base; +#endif int err; ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); @@ -76,6 +86,45 @@ static int atmel_flexcom_probe(struct platform_device *pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); +#ifdef CONFIG_SOC_LAN966 + /* + * Flexcom Shared Register Configurations: + * In order to map chip select index X of Flexcom Y to FLEXCOM_SHARED Z, + * write 0 to bit index Z of FLEXCOM_SHARED[Y]:SS_MASK[X]. + */ + if (of_property_read_bool(np, "lan966x-flx-shared-cfg")) { + /* Shared pin */ + err = of_property_read_u32(np, "lan966x-ss-pin", &lan966x_ss_pin); + if (err) + return err; + + if (lan966x_ss_pin > 20) + return -EINVAL; + + /* chip-select */ + err = of_property_read_u32(np, "lan966x-cs", &lan966x_cs); + if (err) + return err; + + if (lan966x_cs > 1) + return -EINVAL; + + shared_base = devm_ioremap_resource(&pdev->dev, + platform_get_resource(pdev, IORESOURCE_MEM, 1)); + if (IS_ERR(shared_base)) { + dev_dbg(&pdev->dev, "No Flexcom shared register config\n"); + return PTR_ERR(shared_base); + } + + val = ~(1 << lan966x_ss_pin) & FLEX_SHRD_MASK; + + if (lan966x_cs == 0) + writel(val, shared_base + FLEX_SHRD_SS_MASK_0); + else + writel(val, shared_base + FLEX_SHRD_SS_MASK_1); + } +#endif + clk_disable_unprepare(ddata->clk); return devm_of_platform_populate(&pdev->dev);