From patchwork Thu Feb 10 11:57:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12741819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36032C4332F for ; Thu, 10 Feb 2022 11:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237682AbiBJL6H (ORCPT ); Thu, 10 Feb 2022 06:58:07 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239078AbiBJL6F (ORCPT ); Thu, 10 Feb 2022 06:58:05 -0500 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68F70263E; Thu, 10 Feb 2022 03:58:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644494286; x=1676030286; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=fktSYkzEnQXH0HnpOaGy2qxNMZM49xcYl+O+kfLDVh8=; b=Lhy0E1UGFZ5C8Lg5nPa732z7Rmc13TPTFEhfkc1SWAxAaDEkHfF3ApOa douAyWH4EfEOBF33iuY+TK+pjJ5OU5jaYkuhSgT8tC4BaX7hr/C1t3hhu cRpVKivjI1wnQJldCZM8spn1Jz14UewJXWRqWj4pu9B1KQtwyy8zn2yvK Q=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 10 Feb 2022 03:58:06 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 03:58:03 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 03:58:02 -0800 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 03:57:55 -0800 From: Sankeerth Billakanti To: , , , , , , , , , , , , , , , , CC: Sankeerth Billakanti , , , , , Subject: [PATCH v4 1/5] dt-bindings: display: simple: Add sharp LQ140M1JW46 panel Date: Thu, 10 Feb 2022 17:27:31 +0530 Message-ID: <1644494255-6632-2-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> References: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for sharp LQ140M1JW46 display panel. It is a 14" eDP panel with 1920x1080 display resolution. Signed-off-by: Sankeerth Billakanti Acked-by: Rob Herring Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson --- Changes in v4: None Changes in v3: None Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 9cf5588..1eb9dd4 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -284,6 +284,8 @@ properties: - sharp,lq101k1ly04 # Sharp 12.3" (2400x1600 pixels) TFT LCD panel - sharp,lq123p1jx31 + # Sharp 14" (1920x1080 pixels) TFT LCD panel + - sharp,lq140m1jw46 # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel - sharp,ls020b1dd01d # Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel From patchwork Thu Feb 10 11:57:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12741820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8AC5C433FE for ; Thu, 10 Feb 2022 11:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238352AbiBJL6N (ORCPT ); Thu, 10 Feb 2022 06:58:13 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:52038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238545AbiBJL6K (ORCPT ); Thu, 10 Feb 2022 06:58:10 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A71E2620; Thu, 10 Feb 2022 03:58:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644494291; x=1676030291; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=NimGNzxyuv501FWg4UNKvO1dFkUp4SFl9IWlki6DaLI=; b=HVuHiAO2ZRvrsC7ebpINyPNycSQsrOYZXPFd8My2L4HJTROeDWJmylqz prSH0E8gG1NS2N3uXmsXP2kzjUEAn+Kj0JjU7Ctxjsmq3Fd206N4oU6a7 60qqr1jqkkL5SehImlxRNrzKGKvfnm5IF9Gm5zAnViqm+NyJgv2PwiIdN 0=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 10 Feb 2022 03:58:11 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 03:58:10 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 03:58:09 -0800 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 03:58:03 -0800 From: Sankeerth Billakanti To: , , , , , , , , , , , , , , , , CC: Sankeerth Billakanti , , , , , Subject: [PATCH v4 2/5] arm64: dts: qcom: sc7280: Add support for eDP panel on CRD Date: Thu, 10 Feb 2022 17:27:32 +0530 Message-ID: <1644494255-6632-3-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> References: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the eDP display panel support without HPD on sc7280 platform. Signed-off-by: Sankeerth Billakanti --- Changes in v4: - Create new patch for name changes - Remove output-low Changes in v3: - Sort the nodes alphabetically - Use - instead of _ as node names - Place the backlight and panel nodes under root - Change the name of edp_out to mdss_edp_out - Change the names of regulator nodes - Delete unused properties in the board file Changes in v2: - Sort node references alphabetically - Improve readability - Move the pwm pinctrl to pwm node - Move the regulators to root - Define backlight power - Remove dummy regulator node - Cleanup pinctrl definitions arch/arm64/boot/dts/qcom/sc7280-crd.dts | 120 ++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index e2efbdd..6dba5ac 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -21,6 +21,59 @@ chosen { stdout-path = "serial0:115200n8"; }; + + backlight_3v3_regulator: backlight-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight_3v3_regulator"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_power>; + }; + + edp_3v3_regulator: edp-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "edp_3v3_regulator"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_power>; + }; + + edp_backlight: edp-backlight { + compatible = "pwm-backlight"; + + power-supply = <&backlight_3v3_regulator>; + pwms = <&pm8350c_pwm 3 65535>; + }; + + edp_panel: edp-panel { + compatible = "sharp,lq140m1jw46"; + + power-supply = <&edp_3v3_regulator>; + backlight = <&edp_backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + edp_panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + }; }; &apps_rsc { @@ -76,6 +129,44 @@ ap_ts_pen_1v8: &i2c13 { }; }; +&edp_out { + remote-endpoint = <&edp_panel_in>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dp_hot_plug_det>; + data-lanes = <0 1>; + vdda-1p2-supply = <&vreg_l6b_1p2>; + vdda-0p9-supply = <&vreg_l1b_0p8>; +}; + +&mdss_edp { + status = "okay"; + + vdda-1p2-supply = <&vreg_l6b_1p2>; + vdda-0p9-supply = <&vreg_l10c_0p8>; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; + +&mdss_edp_phy { + status = "okay"; + + vdda-1p2-supply = <&vreg_l6b_1p2>; + vdda-0p9-supply = <&vreg_l10c_0p8>; +}; + +&mdss_mdp { + status = "okay"; +}; + &nvme_3v3_regulator { gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; }; @@ -84,7 +175,36 @@ ap_ts_pen_1v8: &i2c13 { pins = "gpio51"; }; +&pm8350c_gpios { + edp_bl_power: edp-bl-power { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = ; + bias-pull-down; + }; + + edp_bl_pwm: edp-bl-pwm { + pins = "gpio8"; + function = "func1"; + qcom,drive-strength = ; + bias-pull-down; + }; +}; + +&pm8350c_pwm { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_pwm>; +}; + &tlmm { + edp_panel_power: edp-panel-power { + pins = "gpio80"; + function = "gpio"; + bias-pull-down; + }; + tp_int_odl: tp-int-odl { pins = "gpio7"; function = "gpio"; From patchwork Thu Feb 10 11:57:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12741821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3BE9C433FE for ; Thu, 10 Feb 2022 11:58:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240214AbiBJL6S (ORCPT ); Thu, 10 Feb 2022 06:58:18 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:52324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241208AbiBJL6S (ORCPT ); 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Thu, 10 Feb 2022 03:58:18 -0800 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 03:58:11 -0800 From: Sankeerth Billakanti To: , , , , , , , , , , , , , , , , CC: Sankeerth Billakanti , , , , , Subject: [PATCH v4 3/5] arm64: dts: qcom: sc7280: rename edp_out label to mdss_edp_out Date: Thu, 10 Feb 2022 17:27:33 +0530 Message-ID: <1644494255-6632-4-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> References: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename the edp_out label in the sc7280 platform to mdss_edp_out. Signed-off-by: Sankeerth Billakanti --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 10 +++++----- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index 6dba5ac..af40e14 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -69,7 +69,7 @@ port@0 { reg = <0>; edp_panel_in: endpoint { - remote-endpoint = <&edp_out>; + remote-endpoint = <&mdss_edp_out>; }; }; }; @@ -129,10 +129,6 @@ ap_ts_pen_1v8: &i2c13 { }; }; -&edp_out { - remote-endpoint = <&edp_panel_in>; -}; - &mdss { status = "okay"; }; @@ -156,6 +152,10 @@ ap_ts_pen_1v8: &i2c13 { /delete-property/ pinctrl-0; }; +&mdss_edp_out { + remote-endpoint = <&edp_panel_in>; +}; + &mdss_edp_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3572399..eca403a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3066,7 +3066,7 @@ port@1 { reg = <1>; - edp_out: endpoint { }; + mdss_edp_out: endpoint { }; }; }; From patchwork Thu Feb 10 11:57:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12741822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D667C433EF for ; Thu, 10 Feb 2022 11:58:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241216AbiBJL6a (ORCPT ); Thu, 10 Feb 2022 06:58:30 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:52512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241218AbiBJL6Z (ORCPT ); Thu, 10 Feb 2022 06:58:25 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 664DE2616; Thu, 10 Feb 2022 03:58:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644494307; x=1676030307; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=byGm30trr+ftjZSNJVDV3jvraOo2jtOVZ2ftABvtjI4=; b=YoBMGl6x47zp/0EvRzflwa31YDPUE8+fOscM3cCu0RPDKcHvZVm1h4l2 6wppzSzV6F6x+UiYee8+VBCWCV8jzfx3viGCMaji9z5M43ti55ZFEFdnI 7RQvRxxFqJwUjyNbhrsIihTFiwl2pKVaucu6Oyny925Mawgy8nKNXxZ9N 4=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 10 Feb 2022 03:58:27 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 03:58:26 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 03:58:26 -0800 Received: from sbillaka-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 03:58:19 -0800 From: Sankeerth Billakanti To: , , , , , , , , , , , , , , , , CC: Sankeerth Billakanti , , , , , Subject: [PATCH v4 4/5] drm/panel-edp: Add eDP sharp panel support Date: Thu, 10 Feb 2022 17:27:34 +0530 Message-ID: <1644494255-6632-5-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> References: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the 14" sharp,lq140m1jw46 eDP panel. Signed-off-by: Sankeerth Billakanti Reviewed-by: Douglas Anderson --- 00 ff ff ff ff ff ff 00 4d 10 23 15 00 00 00 00 35 1e 01 04 a5 1f 11 78 07 de 50 a3 54 4c 99 26 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 5a 87 80 a0 70 38 4d 40 30 20 35 00 35 ae 10 00 00 18 65 38 80 a0 70 38 4d 40 30 20 35 00 35 ae 10 00 00 18 00 00 00 fd 00 30 90 a7 a7 23 01 00 00 00 00 00 00 00 00 00 00 fc 00 4c 51 31 34 30 4d 31 4a 57 34 39 0a 20 00 77 ---------------- Block 0, Base EDID: EDID Structure Version & Revision: 1.4 Vendor & Product Identification: Manufacturer: SHP Model: 5411 Made in: week 53 of 2020 Basic Display Parameters & Features: Digital display Bits per primary color channel: 8 DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 2.20 Supported color formats: RGB 4:4:4 Default (sRGB) color space is primary color space First detailed timing includes the native pixel format and preferred refresh rate Display is continuous frequency Color Characteristics: Red : 0.6396, 0.3291 Green: 0.2998, 0.5996 Blue : 0.1494, 0.0595 White: 0.3125, 0.3281 Established Timings I & II: none Standard Timings: none Detailed Timing Descriptors: DTD 1: 1920x1080 143.981 Hz 16:9 166.587 kHz 346.500 MHz (309 mm x 174 mm) Hfront 48 Hsync 32 Hback 80 Hpol N Vfront 3 Vsync 5 Vback 69 Vpol N DTD 2: 1920x1080 59.990 Hz 16:9 69.409 kHz 144.370 MHz (309 mm x 174 mm) Hfront 48 Hsync 32 Hback 80 Hpol N Vfront 3 Vsync 5 Vback 69 Vpol N Display Range Limits: Monitor ranges (Bare Limits): 48-144 Hz V, 167-167 kHz H, max dotclock 350 MHz Display Product Name: 'LQ140M1JW49' Checksum: 0x77 Changes in v4: -Add all modes from EDID -Provide EDID blob Changes in v3: None drivers/gpu/drm/panel/panel-edp.c | 44 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c index a394a15..f9355b2 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -1605,6 +1605,47 @@ static const struct panel_desc sharp_lq123p1jx31 = { }, }; +static const struct drm_display_mode sharp_lq140m1jw46_mode[] = { + { + .clock = 346500, + .hdisplay = 1920, + .hsync_start = 1920 + 48, + .hsync_end = 1920 + 48 + 32, + .htotal = 1920 + 48 + 32 + 80, + .vdisplay = 1080, + .vsync_start = 1080 + 3, + .vsync_end = 1080 + 3 + 5, + .vtotal = 1080 + 3 + 5 + 69, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, + }, { + .clock = 144370, + .hdisplay = 1920, + .hsync_start = 1920 + 48, + .hsync_end = 1920 + 48 + 32, + .htotal = 1920 + 48 + 32 + 80, + .vdisplay = 1080, + .vsync_start = 1080 + 3, + .vsync_end = 1080 + 3 + 5, + .vtotal = 1080 + 3 + 5 + 69, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, + }, +}; + +static const struct panel_desc sharp_lq140m1jw46 = { + .modes = sharp_lq140m1jw46_mode, + .num_modes = ARRAY_SIZE(sharp_lq140m1jw46_mode), + .bpc = 8, + .size = { + .width = 309, + .height = 174, + }, + .delay = { + .hpd_absent = 80, + .enable = 50, + .unprepare = 500, + }, +}; + static const struct drm_display_mode starry_kr122ea0sra_mode = { .clock = 147000, .hdisplay = 1920, @@ -1719,6 +1760,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "sharp,lq123p1jx31", .data = &sharp_lq123p1jx31, }, { + .compatible = "sharp,lq140m1jw46", + .data = &sharp_lq140m1jw46, + }, { .compatible = "starry,kr122ea0sra", .data = &starry_kr122ea0sra, }, { From patchwork Thu Feb 10 11:57:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sankeerth Billakanti (QUIC)" X-Patchwork-Id: 12741823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B86FC433F5 for ; Thu, 10 Feb 2022 11:58:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239725AbiBJL6g (ORCPT ); Thu, 10 Feb 2022 06:58:36 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:52512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241224AbiBJL6e (ORCPT ); Thu, 10 Feb 2022 06:58:34 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB2392634; Thu, 10 Feb 2022 03:58:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 10 Feb 2022 03:58:27 -0800 From: Sankeerth Billakanti To: , , , , , , , , , , , , , , , , CC: Sankeerth Billakanti , , , , , Subject: [PATCH v4 5/5] drm/msm/dp: Add driver support to utilize drm panel Date: Thu, 10 Feb 2022 17:27:35 +0530 Message-ID: <1644494255-6632-6-git-send-email-quic_sbillaka@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> References: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support in the DP driver to utilize the custom eDP panels from drm/panels. An eDP panel is always connected to the platform. So, the eDP connector can be reported as always connected. The display mode will be sourced from the panel. The panel mode will be set after the link training is completed. Signed-off-by: Sankeerth Billakanti --- Changes in v4: - Remove obvious comments - Define separate connector_ops for eDP - Remove unnecessary checks Changes in v3: None drivers/gpu/drm/msm/dp/dp_display.c | 6 ++++ drivers/gpu/drm/msm/dp/dp_drm.c | 62 +++++++++++++++++++++++++++++++------ drivers/gpu/drm/msm/dp/dp_parser.h | 3 ++ 3 files changed, 61 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 7cc4d21..5d314e6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1513,6 +1513,9 @@ int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder) return -EINVAL; } + if (dp->connector_type == DRM_MODE_CONNECTOR_eDP) + dp_hpd_plug_handle(dp_display, 0); + mutex_lock(&dp_display->event_mutex); /* stop sentinel checking */ @@ -1577,6 +1580,9 @@ int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder) dp_display = container_of(dp, struct dp_display_private, dp_display); + if (dp->connector_type == DRM_MODE_CONNECTOR_eDP) + dp_hpd_unplug_handle(dp_display, 0); + mutex_lock(&dp_display->event_mutex); /* stop sentinel checking */ diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index d4d360d..2436329 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -123,6 +123,25 @@ static enum drm_mode_status dp_connector_mode_valid( return dp_display_validate_mode(dp_disp, mode->clock); } +static int edp_connector_get_modes(struct drm_connector *connector) +{ + struct msm_dp *dp; + + dp = to_dp_connector(connector)->dp_display; + + return drm_bridge_get_modes(dp->panel_bridge, connector); +} + +static enum drm_mode_status edp_connector_mode_valid( + struct drm_connector *connector, + struct drm_display_mode *mode) +{ + if (mode->clock > EDP_MAX_PIXEL_CLK_KHZ) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static const struct drm_connector_funcs dp_connector_funcs = { .detect = dp_connector_detect, .fill_modes = drm_helper_probe_single_connector_modes, @@ -132,11 +151,24 @@ static const struct drm_connector_funcs dp_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, }; +static const struct drm_connector_funcs edp_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + static const struct drm_connector_helper_funcs dp_connector_helper_funcs = { .get_modes = dp_connector_get_modes, .mode_valid = dp_connector_mode_valid, }; +static const struct drm_connector_helper_funcs edp_connector_helper_funcs = { + .get_modes = edp_connector_get_modes, + .mode_valid = edp_connector_mode_valid, +}; + /* connector initialization */ struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display) { @@ -154,18 +186,28 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display) connector = &dp_connector->base; - ret = drm_connector_init(dp_display->drm_dev, connector, - &dp_connector_funcs, - dp_display->connector_type); - if (ret) - return ERR_PTR(ret); + if (dp_display->connector_type == DRM_MODE_CONNECTOR_eDP) { + ret = drm_connector_init(dp_display->drm_dev, connector, + &edp_connector_funcs, DRM_MODE_CONNECTOR_eDP); + if (ret) + return ERR_PTR(ret); + + drm_connector_helper_add(connector, + &edp_connector_helper_funcs); + } else { + ret = drm_connector_init(dp_display->drm_dev, connector, + &dp_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort); + if (ret) + return ERR_PTR(ret); - drm_connector_helper_add(connector, &dp_connector_helper_funcs); + drm_connector_helper_add(connector, &dp_connector_helper_funcs); - /* - * Enable HPD to let hpd event is handled when cable is connected. - */ - connector->polled = DRM_CONNECTOR_POLL_HPD; + /* + * Enable HPD to let hpd event is handled when cable is connected. + */ + connector->polled = DRM_CONNECTOR_POLL_HPD; + } drm_connector_attach_encoder(connector, dp_display->encoder); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 3172da0..58c4f27 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -17,6 +17,9 @@ #define DP_MAX_PIXEL_CLK_KHZ 675000 #define DP_MAX_NUM_DP_LANES 4 +/* Maximum validated clock */ +#define EDP_MAX_PIXEL_CLK_KHZ 285550 + enum dp_pm_type { DP_CORE_PM, DP_CTRL_PM,