From patchwork Thu Feb 10 18:36:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12742287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4680CC4332F for ; Thu, 10 Feb 2022 18:37:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E518110E94E; Thu, 10 Feb 2022 18:36:55 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94E5110E95E; Thu, 10 Feb 2022 18:36:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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10 Feb 2022 10:36:40 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Feb 2022 10:36:31 -0800 Message-Id: <20220210183636.1187973-2-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210183636.1187973-1-michael.cheng@intel.com> References: <20220210183636.1187973-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc performs a flush by first performing a clean, follow by an invalidation operation. v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h v4 (Michael Cheng): Rebase v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/drm_cache.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 66597e411764..2e233f53331e 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -28,6 +28,7 @@ * Authors: Thomas Hellström */ +#include #include #include #include @@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); + #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif From patchwork Thu Feb 10 18:36:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12742290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B071C433EF for ; Thu, 10 Feb 2022 18:37:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 18A5C10E956; Thu, 10 Feb 2022 18:36:57 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 034EB10E94F; Thu, 10 Feb 2022 18:36:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644518213; x=1676054213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0faIJeanSVg4TVsukZep2SH9zNSBXKIPlWiirFMZ1bw=; b=j2f+xEHnpp2/OE1GM24nSzdTsxeM4GRMMZBayp+izgnvHck3jAnrph/w 7ZPgWETjV26pkYIZMNJfgfH1pGumtJs1sLYmz98LTLF4qiDmXlOnkAAld ohZuWOOoX1hdMyAyxB0ZR+AiR6elSmM4lWptXXjMN0RXcAT8egIaTiuJF i6KU1N84fTRdV/KOk+xwRzWqtWCNPqkeEf0Gw4yFCVh07k6ZlW1pNetVz 4JNASZZzRVnwHKlVKesiQokyf5YBqMDBT7XOE9L68nGNpqJyY7XbZ3vl6 /0f7XF1CKSnKyjh8Yp5Su+ox+xqsne6u6QFIRqX/NXAsjoa9eBbxNxs0k g==; X-IronPort-AV: E=McAfee;i="6200,9189,10254"; a="229528163" X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="229528163" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:40 -0800 X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="526616761" Received: from lmoua-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.212.169.226]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:40 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Feb 2022 10:36:32 -0800 Message-Id: <20220210183636.1187973-3-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210183636.1187973-1-michael.cheng@intel.com> References: <20220210183636.1187973-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 2/6] drm/i915/gt: Re-work intel_write_status_page X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 0e353d8c2bc8..986777c2430d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * of extra paranoia to try and ensure that the HWS takes the value * we give and that it doesn't end up trapped inside the CPU! */ - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - mb(); - clflush(&engine->status_page.addr[reg]); - engine->status_page.addr[reg] = value; - clflush(&engine->status_page.addr[reg]); - mb(); - } else { - WRITE_ONCE(engine->status_page.addr[reg], value); - } + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); + WRITE_ONCE(engine->status_page.addr[reg], value); + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); } /* From patchwork Thu Feb 10 18:36:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12742288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9A60C433FE for ; Thu, 10 Feb 2022 18:37:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3353610E951; Thu, 10 Feb 2022 18:36:56 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4565510E951; Thu, 10 Feb 2022 18:36:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644518213; x=1676054213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1IX9wkoWsbtqy+bgG/GLAyffib2A3mrxbjpJxzK79Cs=; b=Ssmu+ER3Xc1YH2tKAeEjqf0RjPPDej6rKd+PgefYMEYXHvTmchcpHZWB KFeAICBI9DNDUK3rhzKonRb0vOp86qC94eVUjTmbUfUuVNJ4Jan+VMq8H nQbmVhc6w0D2Qq16r1cudWw+I7dz/GD/oVyIZkfuwC02qdIW/8i0d7L1j q1uMV3wizvjwrqldr3iYNre8uOBu+5yGFinkxZ4afqR9dA9Dbd19SjIec JQrvJCNQ6QG/1PsrrmYNiOYPMYOblqmu0/Fjji9Y4OeqTPWCFkybLvg7v j1pk1QjDsFc6r0ZRsX3kEMWFGpInQTBkDOgEPx3cE6xDlUM25b5lrxYQw Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10254"; a="229528167" X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="229528167" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:41 -0800 X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="526616766" Received: from lmoua-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.212.169.226]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:40 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Feb 2022 10:36:33 -0800 Message-Id: <20220210183636.1187973-4-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210183636.1187973-1-michael.cheng@intel.com> References: <20220210183636.1187973-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 3/6] drm/i915/gt: Drop invalidate_csb_entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Drop invalidate_csb_entries and directly call drm_clflush_virt_range. This allows for one less function call, and prevent complier errors when building for non-x86 architectures. v2(Michael Cheng): Drop invalidate_csb_entries function and directly invoke drm_clflush_virt_range. Thanks to Tvrtko for the sugguestion. v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range. Thanks to Tvrtko for pointing this out. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- .../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 9bb7c863172f..6186a5e4b191 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists, return inactive; } -static void invalidate_csb_entries(const u64 *first, const u64 *last) -{ - clflush((void *)first); - clflush((void *)last); -} - /* * Starting with Gen12, the status has a new format: * @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) * the wash as hardware, working or not, will need to do the * invalidation before. */ - invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); + drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0])); /* * We assume that any event reflects a change in context flow @@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine) /* Check that the GPU does indeed update the CSB entries! */ memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64)); - invalidate_csb_entries(&execlists->csb_status[0], - &execlists->csb_status[reset_value]); + drm_clflush_virt_range(&execlists->csb_status[0], + execlists->csb_size * + sizeof(execlists->csb_status[0])); /* Once more for luck and our trusty paranoia */ ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR, From patchwork Thu Feb 10 18:36:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12742284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CD5AC433F5 for ; Thu, 10 Feb 2022 18:36:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 723E710E93C; Thu, 10 Feb 2022 18:36:43 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 208C410E334; Thu, 10 Feb 2022 18:36:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644518202; x=1676054202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LyWhbupHNmIXjb6Pei3uI7laM6LGvM10gjUbm3K//NU=; b=TXqDS3HqE3egBuWDxsppskcJ2Psh87ZoSqTNzZQm2pNGhyGeBjSnCVbT W8pf/tDP893yN9fK2uAZJANyX1uTjI45KiAVeqMTwRc83Lf9if8iX039g nD1cEd3G3Dh1MgvLONmuPnL23GvK1Frtyfb9A4NTn3KCHfi55r0q7P//T izNgby/1/Obl4auJtGPNNZ2Rrc4D1P/dPvIFQLiqAK/XDTzw/T3lW/zI3 9n+hZMXhPJKRct5f9H5sIZJapVGh/Ti9UC+KrnWbeb3/SX/utArIfTScE g5Yiy+tX6nKf+2VwErIuqvuHVA4PmWgGmgNERyXNlWR6T2CUk7KTzRh1r g==; X-IronPort-AV: E=McAfee;i="6200,9189,10254"; a="248392697" X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="248392697" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:41 -0800 X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="526616772" Received: from lmoua-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.212.169.226]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:40 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Feb 2022 10:36:34 -0800 Message-Id: <20220210183636.1187973-5-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210183636.1187973-1-michael.cheng@intel.com> References: <20220210183636.1187973-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use drm_clflush_virt_range instead of directly invoking clflush. This will prevent compiler errors when building for non-x86 architectures. v2(Michael Cheng): Remove extra clflush v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range takes care of it. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 6186a5e4b191..11b864fd68a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive) { struct intel_engine_execlists * const execlists = &engine->execlists; - mb(); /* paranoia: read the CSB pointers from after the reset */ - clflush(execlists->csb_write); - mb(); + drm_clflush_virt_range(execlists->csb_write, + sizeof(execlists->csb_write)); inactive = process_csb(engine, inactive); /* drain preemption events */ From patchwork Thu Feb 10 18:36:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12742289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA6F2C43217 for ; Thu, 10 Feb 2022 18:37:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63A4A10E955; Thu, 10 Feb 2022 18:36:56 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 775F410E95E; Thu, 10 Feb 2022 18:36:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644518213; x=1676054213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o6HuYlnP32PX1lqgHE1fsvZCwjUKZXMxGSqa7+v9E8k=; b=JaDlcp4ZrMqoVnDXzO8h+1MtwXVg6bRvQ93ipenrnh/QJvOOUaypiiUw CFdEoHkI3dCMZcNSm8zPBIId9ho4bDKgUUn+tGwkaqqB6hMkY+lA1p5B8 4LM8aBgYI2xo+Iajg09/o/6zyShVJkmtq+KRYrWwG/AKJULa+DJO7k/lQ r8blpzEqyyoMnENyu8dCvFqsxprOaD4aKFvGIMNIKkKfXH6yQVa0pS9jf xJoeN8kk6ForpcdAi/3NC3YsWE6kRYqFR0h/w9GEEBIJHzeySoKxPlyTX tzk30MHN4yHWFpwf+SxNUbJMFuO3l6BQqzHG+CZ7fv37cb+NoG7xdb/j1 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10254"; a="229528171" X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="229528171" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:41 -0800 X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="526616781" Received: from lmoua-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.212.169.226]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:41 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Feb 2022 10:36:35 -0800 Message-Id: <20220210183636.1187973-6-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210183636.1187973-1-michael.cheng@intel.com> References: <20220210183636.1187973-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 5/6] drm/i915/: Re-work clflush_write32 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use drm_clflush_virt_range instead of clflushopt and remove the memory barrier, since drm_clflush_virt_range takes care of that. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 498b458fd784..0854276ff7ba 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma, static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) { if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { - if (flushes & CLFLUSH_BEFORE) { - clflushopt(addr); - mb(); - } + if (flushes & CLFLUSH_BEFORE) + drm_clflush_virt_range(addr, sizeof(addr)); *addr = value; @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) * to ensure ordering of clflush wrt to the system. */ if (flushes & CLFLUSH_AFTER) - clflushopt(addr); + drm_clflush_virt_range(addr, sizeof(addr)); } else *addr = value; } From patchwork Thu Feb 10 18:36:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12742285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2441C433EF for ; Thu, 10 Feb 2022 18:36:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC69710E947; Thu, 10 Feb 2022 18:36:44 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C87910E93C; Thu, 10 Feb 2022 18:36:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644518202; x=1676054202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ho6kpFZAscusI7nIrWDNnWHNjVK2wgi7j6D5m4YBDOw=; b=EMJJii84nkqBH5zHNcEkutZm9O3KZAQQdabx58xS1Fmd6rhP1Xznn9ed oVm1fhs2MjkME/FFYfvJ6+uGfx3+KOidcMtkP6M/vltmy+C16A2xcJAAV nNopJ8dgS7MvKBtUWs6v1mQqTKt3YUGdnSoidTk0qSrkWqbKkYwA4uAmf K+etfkczI6U2KN/tetUs9ubcY2+5fM2XXXOid4I1uM79v0Igq2vzqYiy8 ICCznsOfpeQUt/JxisQD2Q9SMwjwDH/RveMuytTtiDqe/JUSbB29uMrN1 fGo/CR8sgeCrikxAGsR6pLoCplNoyOnEi8C68aM75OK7Wli20DPc89Ny9 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10254"; a="248392700" X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="248392700" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:41 -0800 X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="526616786" Received: from lmoua-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.212.169.226]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:41 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Feb 2022 10:36:36 -0800 Message-Id: <20220210183636.1187973-7-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210183636.1187973-1-michael.cheng@intel.com> References: <20220210183636.1187973-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 6/6] drm/i915/gt: replace cache_clflush_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Replace all occurrence of cache_clflush_range with drm_clflush_virt_range. This will prevent compile errors on non-x86 platforms. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------ drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index c43e724afa9f..d0999e92621b 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, pd = pdp->entry[gen8_pd_index(idx, 2)]; } - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1))); } } while (1); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); return idx; } @@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, } } while (rem >= page_size && index < I915_PDES); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); /* * Is it safe to mark the 2M block as 64K? -- Either we have @@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, I915_GTT_PAGE_SIZE_2M)))) { vaddr = px_vaddr(pd); vaddr[maybe_64K] |= GEN8_PDE_IPS_64K; - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); page_size = I915_GTT_PAGE_SIZE_64K; /* @@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, for (i = 1; i < index; i += 16) memset64(vaddr + i, encode, 15); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); } } @@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1))); vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags); - clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); + drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); } static int gen8_init_scratch(struct i915_address_space *vm) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 11b864fd68a5..67dd4b1fc185 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine); /* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); intel_engine_reset_pinned_contexts(engine); } diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 0d6bbc8c57f2..9b594be9102f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) void *vaddr = __px_vaddr(p); memset64(vaddr, val, count); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); } static void poison_scratch_page(struct drm_i915_gem_object *scratch) diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index 48e6e2f87700..bd474a5123cb 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma, u64 * const vaddr = __px_vaddr(pdma); vaddr[idx] = encoded_entry; - clflush_cache_range(&vaddr[idx], sizeof(u64)); + drm_clflush_virt_range(&vaddr[idx], sizeof(u64)); } void diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index b3a429a92c0d..89020706adc4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine); /* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); intel_engine_reset_pinned_contexts(engine); }