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Wysocki" , , , CC: , Randy Dunlap , Stephen Rothwell , Giovanni Gherdovich , Alex Deucher , "Deepak Sharma" , Jinzhou Su , Perry Yuan , Jassmine Meng , Huang Rui Subject: [PATCH 1/4] x86/acpi: Expand the CPPC MSR file to cover the whole CPPC implementation Date: Mon, 14 Feb 2022 18:14:47 +0800 Message-ID: <20220214101450.356047-2-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214101450.356047-1-ray.huang@amd.com> References: <20220214101450.356047-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 869c178b-2ec3-470e-62ae-08d9efa2e4bc X-MS-TrafficTypeDiagnostic: BY5PR12MB4145:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FJQTZmikMe3o+nUNhi9AW+c4o8UU4H9fvILRFOcRWM8NWA/D1i+B7zPnfkvRkjbod9ucbu9yBeXOPO7hxP+SswuEGDvXB5OYkAygHzPWJBOctvadGc634XURwIbRofJrMzozx4nbkVkBIH/49PxTqlOSGFmhtzk2fDnsANxIhn36QatDM5ACDGhwLv2///Dj+rmn4nK5RMWLAyGc1fyk1riltMagfUX5g2tmzLQoumNTyNstxsD6iZmVNU05shiVcymJyngbtDEYlGvkE5G+uEpxs3cL2DWUopEwjC0Qr6t7nFwpzuxQdPOYMgSG61cwkiHOxi7RbnThlQYWkZ7ul+vTSRMXZ1DujDeSMrZZZ49sjIOjvhHkl4n0/BHVIM3hRIV9DXbKG5hdi7SinmOJBAy8G3EaVkEjDBf0kuV6XqA0I/NIZXq3aBR9dXemlPl4SO/8lJDj0PPWARkXHEg2qB5xhJUZq7s+z8xYg5auLfG+W7yjPHMawMaZWhk/HU0JYon8+WQHPYtvBAyecD07v8HmuMMNv6/PwoXyllB7li5NSNwg30RksdxKKgjwga0l86+7aKo0LPiYk1+Qp1vzWmylarrywfPGuKtYRfP32qp8n8WhFsN1e0O4xJRg5Dt/0pjjVReMbh8ZUMQkSi0zht+Koz+sT1SV8p1LtdBlolIMtOcuyws3Fdf5mKznk5vxQBvpII8JLRCP6nuR8FpL9g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(36860700001)(47076005)(508600001)(2616005)(7696005)(83380400001)(82310400004)(336012)(426003)(186003)(1076003)(26005)(16526019)(356005)(4326008)(8676002)(86362001)(70586007)(40460700003)(70206006)(8936002)(5660300002)(2906002)(36756003)(6666004)(110136005)(316002)(54906003)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 10:15:15.0146 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 869c178b-2ec3-470e-62ae-08d9efa2e4bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4145 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Rename the cppc_msr.c to cppc.c in x86 ACPI, that expects to use this file to cover more function implementation for ACPI CPPC beside MSR helpers. Naming as "cppc" is more straightforward as one of the functionalities under ACPI subsystem. Signed-off-by: Huang Rui --- arch/x86/kernel/acpi/Makefile | 2 +- arch/x86/kernel/acpi/{cppc_msr.c => cppc.c} | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/x86/kernel/acpi/{cppc_msr.c => cppc.c} (96%) diff --git a/arch/x86/kernel/acpi/Makefile b/arch/x86/kernel/acpi/Makefile index cf340d85946a..fc17b3f136fe 100644 --- a/arch/x86/kernel/acpi/Makefile +++ b/arch/x86/kernel/acpi/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_ACPI) += boot.o obj-$(CONFIG_ACPI_SLEEP) += sleep.o wakeup_$(BITS).o obj-$(CONFIG_ACPI_APEI) += apei.o -obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_msr.o +obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o ifneq ($(CONFIG_ACPI_PROCESSOR),) obj-y += cstate.o diff --git a/arch/x86/kernel/acpi/cppc_msr.c b/arch/x86/kernel/acpi/cppc.c similarity index 96% rename from arch/x86/kernel/acpi/cppc_msr.c rename to arch/x86/kernel/acpi/cppc.c index b961de569e7e..08d823d72586 100644 --- a/arch/x86/kernel/acpi/cppc_msr.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * cppc_msr.c: MSR Interface for CPPC + * cppc.c: CPPC Interface for x86 * Copyright (c) 2016, Intel Corporation. */ From patchwork Mon Feb 14 10:14:48 2022 Content-Type: text/plain; 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Wysocki" , , , CC: , Randy Dunlap , Stephen Rothwell , Giovanni Gherdovich , Alex Deucher , "Deepak Sharma" , Jinzhou Su , Perry Yuan , Jassmine Meng , Huang Rui Subject: [PATCH 2/4] x86, sched: Move AMD maximum frequency ratio setting function into x86 CPPC Date: Mon, 14 Feb 2022 18:14:48 +0800 Message-ID: <20220214101450.356047-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214101450.356047-1-ray.huang@amd.com> References: <20220214101450.356047-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7c4133ca-e670-4b48-78a6-08d9efa2e702 X-MS-TrafficTypeDiagnostic: MN2PR12MB2974:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LQ0opLGkJMYd3UibTSHFag4QSqObOriRfeERmq92exhqS9J2U3UsNCXTuDiIZB5Db5SFjfHOWk/lhrEa1GKD9/qKoHxT/zYP7QSuUtA3ppNe+N4/EuzwU08sSsk7NdvU2K5HL5GXHZd/bjMQ0E800M8OscFk8Upo0YP9wv7FcVWIxONQ56W/AqioEekhBM/p8qGw0k86HmwMGMUqUqouHviEY7hoHu7VQIffm3geQOtG4sKa9QdoJAJRuwkyZePxRT4hvxC0uOsHcljwyEYq+xwhEgbbcycOWm44mHLd/HIWPlaJ14N3psyOXmB28xi3owKKHj0lZ5bXpnFRjc0EWTOgH4bK14rdFJ6CCyS6zp0lpxgIuh55doKXmQkUTZLtF4yrVT4tW6uklrEZRjqJ5cTmML2+Utsf3T3FGm3f3WowDY/3IVSZ/IUMCa7XFHoK30wyK2exVizr4dCoSAL+F3czE/vfwhbAZPEO+NXNmrddWghuhL4jdnlWMwze59fN4GE2G9ekFQC1lbM06tlhV4Is2ykkAww7lxfMIsctVSlh+svm8iMioyOjrajBP+h7yvdfzUgTtwtGVcuV2gOOxArTdrYkzufodndrWpcYf3eSYcAVtgbqfa15r9O9ld66n8zdTFBSs31Q6Wr1fLjR1liivqnsLQqCzLDfbJ5thzjW+e7ZsAURcHID9NjI9LNeuow493wTOAveOhnJQLfT+w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(82310400004)(356005)(316002)(110136005)(81166007)(2906002)(54906003)(8936002)(4326008)(8676002)(6666004)(70586007)(70206006)(5660300002)(86362001)(26005)(186003)(1076003)(36756003)(2616005)(16526019)(336012)(426003)(47076005)(7696005)(83380400001)(36860700001)(508600001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 10:15:18.8293 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7c4133ca-e670-4b48-78a6-08d9efa2e702 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2974 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AMD maximum frequency ratio setting function depends on CPPC, so the x86 CPPC implementation file is better space for this function. Signed-off-by: Huang Rui --- arch/x86/include/asm/topology.h | 9 +++++++ arch/x86/kernel/acpi/cppc.c | 40 ++++++++++++++++++++++++++++++ arch/x86/kernel/smpboot.c | 44 +-------------------------------- 3 files changed, 50 insertions(+), 43 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 2f0b6be8eaab..168ade7d4007 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -226,4 +226,13 @@ void init_freq_invariance_cppc(void); #define init_freq_invariance_cppc init_freq_invariance_cppc #endif +#ifdef CONFIG_ACPI_CPPC_LIB +bool amd_set_max_freq_ratio(u64 *ratio); +#else +static inline bool amd_set_max_freq_ratio(u64 *ratio) +{ + return false; +} +#endif + #endif /* _ASM_X86_TOPOLOGY_H */ diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 08d823d72586..f0be5058e3e3 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -6,6 +6,8 @@ #include #include +#include +#include /* Refer to drivers/acpi/cppc_acpi.c for the description of functions */ @@ -47,3 +49,41 @@ int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) } return err; } + +bool amd_set_max_freq_ratio(u64 *ratio) +{ + struct cppc_perf_caps perf_caps; + u64 highest_perf, nominal_perf; + u64 perf_ratio; + int rc; + + if (!ratio) + return false; + + rc = cppc_get_perf_caps(0, &perf_caps); + if (rc) { + pr_debug("Could not retrieve perf counters (%d)\n", rc); + return false; + } + + highest_perf = amd_get_highest_perf(); + nominal_perf = perf_caps.nominal_perf; + + if (!highest_perf || !nominal_perf) { + pr_debug("Could not retrieve highest or nominal performance\n"); + return false; + } + + perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf); + /* midpoint between max_boost and max_P */ + perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1; + if (!perf_ratio) { + pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n"); + return false; + } + + *ratio = perf_ratio; + arch_set_max_freq_ratio(false); + + return true; +} diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 617012f4619f..0718cc7649a4 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -2097,48 +2097,6 @@ static bool intel_set_max_freq_ratio(void) return true; } -#ifdef CONFIG_ACPI_CPPC_LIB -static bool amd_set_max_freq_ratio(void) -{ - struct cppc_perf_caps perf_caps; - u64 highest_perf, nominal_perf; - u64 perf_ratio; - int rc; - - rc = cppc_get_perf_caps(0, &perf_caps); - if (rc) { - pr_debug("Could not retrieve perf counters (%d)\n", rc); - return false; - } - - highest_perf = amd_get_highest_perf(); - nominal_perf = perf_caps.nominal_perf; - - if (!highest_perf || !nominal_perf) { - pr_debug("Could not retrieve highest or nominal performance\n"); - return false; - } - - perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf); - /* midpoint between max_boost and max_P */ - perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1; - if (!perf_ratio) { - pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n"); - return false; - } - - arch_turbo_freq_ratio = perf_ratio; - arch_set_max_freq_ratio(false); - - return true; -} -#else -static bool amd_set_max_freq_ratio(void) -{ - return false; -} -#endif - static void init_counter_refs(void) { u64 aperf, mperf; @@ -2187,7 +2145,7 @@ static void init_freq_invariance(bool secondary, bool cppc_ready) if (!cppc_ready) { return; } - ret = amd_set_max_freq_ratio(); + ret = amd_set_max_freq_ratio(&arch_turbo_freq_ratio); } if (ret) { From patchwork Mon Feb 14 10:14:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12745380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A6F6C433FE for ; Mon, 14 Feb 2022 10:51:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349040AbiBNKv0 (ORCPT ); Mon, 14 Feb 2022 05:51:26 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350186AbiBNKvL (ORCPT ); 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Mon, 14 Feb 2022 04:15:18 -0600 From: Huang Rui To: Borislav Petkov , "Rafael J . Wysocki" , , , CC: , Randy Dunlap , Stephen Rothwell , Giovanni Gherdovich , Alex Deucher , "Deepak Sharma" , Jinzhou Su , Perry Yuan , Jassmine Meng , Huang Rui Subject: [PATCH 3/4] x86, sched: Expose init_freq_invariance to topology header Date: Mon, 14 Feb 2022 18:14:49 +0800 Message-ID: <20220214101450.356047-4-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214101450.356047-1-ray.huang@amd.com> References: <20220214101450.356047-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b775440e-79e0-4bb6-3ef1-08d9efa2e97a X-MS-TrafficTypeDiagnostic: PH7PR12MB5902:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g+Zir3AG3IoOOs2p42gAqbTQMgRvjd3TOZdsZCGukIIZ7liAvEMpNY6IlLorp+bM5DypO7zRJ/bNy08/zbr4wWGlubti9kEnkt3MwOE3gofbO3e9ihAiBRdIL9Cuqxn4XGsJ2lYRivMqZkBn8NUw296fxIttXGJ4K2Wt0ebi23Qy+8Wv+zMWBds9yEz5wIZ++cwwPsCbQT8cPsGd4BxtS6EhHIaIpAxzNWsjsXu2DMnTnSV/j88E2Cu6zDZc6Omh+ySUjtbX7pjHvYRm4IFuK+B2LFIuTWzZ2ZHa6fXaxocABBItRbtf+Owa3mDrDxHC6lFpFO+rEyy+deGYT+fVnBmbTfNFN15tAbgqlWDzx0TDXJtQsTTkvRnD8UkvJmlcFI+2UmowAR4QTquIgTTs8qtjMHGVWuIE8KphKqCfxMv7ZeZcUl8eRI6IQgdgc9tIey3soPRLERjQv8/zQdyb1sbLz32cJVKyX037KNAw69PvLo7EwNpIY3saSq6uOOjFHnaRpvCOp1z/7RWJgJOO0UQRZnT9jUf6M8cQvXFu5fWPMQdDrtLxsI7LIh4Lj/yh7F6q/yLRMGP0+qfi8brlogBgMXe2HFQEM9shg9QLqylNtbc9VACfEf6f2Vrc0JzLUuuAcMZQUtHG2alvmu2Z2xTItVAhMUcS3X/TAo/oUrIUxb1pjKf3C57KgGZkhHGW2hyYbUVt/y8byCdN05XZOw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(8936002)(4326008)(186003)(70206006)(2906002)(5660300002)(82310400004)(8676002)(70586007)(86362001)(36756003)(356005)(81166007)(16526019)(83380400001)(26005)(36860700001)(336012)(508600001)(40460700003)(2616005)(47076005)(1076003)(316002)(110136005)(54906003)(426003)(6666004)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 10:15:22.9541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b775440e-79e0-4bb6-3ef1-08d9efa2e97a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5902 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The function init_freq_invariance will be used on x86 CPPC, so expose it in the topology header. Signed-off-by: Huang Rui --- arch/x86/include/asm/topology.h | 4 ++++ arch/x86/kernel/smpboot.c | 8 +------- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 168ade7d4007..c35005a03768 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -215,10 +215,14 @@ extern void arch_scale_freq_tick(void); #define arch_scale_freq_tick arch_scale_freq_tick extern void arch_set_max_freq_ratio(bool turbo_disabled); +void init_freq_invariance(bool secondary, bool cppc_ready); #else static inline void arch_set_max_freq_ratio(bool turbo_disabled) { } +static inline void init_freq_invariance(bool secondary, bool cppc_ready) +{ +} #endif #if defined(CONFIG_ACPI_CPPC_LIB) && defined(CONFIG_SMP) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 0718cc7649a4..8f2ff9be0fcc 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -155,8 +155,6 @@ static inline void smpboot_restore_warm_reset_vector(void) *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; } -static void init_freq_invariance(bool secondary, bool cppc_ready); - /* * Report back to the Boot Processor during boot time or to the caller processor * during CPU online. @@ -2125,7 +2123,7 @@ static void register_freq_invariance_syscore_ops(void) static inline void register_freq_invariance_syscore_ops(void) {} #endif -static void init_freq_invariance(bool secondary, bool cppc_ready) +void init_freq_invariance(bool secondary, bool cppc_ready) { bool ret = false; @@ -2222,8 +2220,4 @@ void arch_scale_freq_tick(void) pr_warn("Scheduler frequency invariance went wobbly, disabling!\n"); schedule_work(&disable_freq_invariance_work); } -#else -static inline void init_freq_invariance(bool secondary, bool cppc_ready) -{ -} #endif /* CONFIG_X86_64 */ From patchwork Mon Feb 14 10:14:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 12745381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6858C433F5 for ; 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Wysocki" , , , CC: , Randy Dunlap , Stephen Rothwell , Giovanni Gherdovich , Alex Deucher , "Deepak Sharma" , Jinzhou Su , Perry Yuan , Jassmine Meng , Huang Rui Subject: [PATCH 4/4] x86/acpi: Move init_freq_invariance_cppc into x86 CPPC Date: Mon, 14 Feb 2022 18:14:50 +0800 Message-ID: <20220214101450.356047-5-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214101450.356047-1-ray.huang@amd.com> References: <20220214101450.356047-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d4bc049d-d84e-4457-9cc6-08d9efa2eb66 X-MS-TrafficTypeDiagnostic: DM6PR12MB4299:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ixNVc46Ycy0RI17lxDk01HNLxFQteUWguPCmVeahe0vq6DIvm1OGIIf73eFwCZu8fEwGFT6OdSsU9dgmvwSMH6HyG1jQfvsdnHbepG/x2azaSVEpSgIp15syHHC0I2QgQ5lIJjSEmvnsH8X2wkQ5AaRWheiVQhv1IhRmZP9jBopAJIZB+JIwWEpqZhGkXdCebRYQhMfnnvqB9j4Xx0nolS5V1uzMwd552JtNNK5xXzpIwUfGvbbUQy70s+kKjh09+gNeWr/2yKfSu9Q+C7BvMzjpRNf1NFQ9pE757MgMoePtkKrb24chtlj4dZSBcp74pKx4i6cJeSs8HgoLXo2PI7NZwywcZIALbxImyD8EwNKuZzchWhGjnFrZPFMlbad2/F6fsDJg1+45KwEERp5jqPMb8ZO4QRghyh3v3EA9JxdPShHl3ApgIJuU3a8I8t47h6HskqbBDwpp828EePWTcRXA1tmGCzmcg7fiNgYkV5GO8Z3+15fjwcQ6PLrONh69QsviAt0b0DF8ddohAzrf6synv5ch9tDWyz/junU46499quEIflLouQMeYNy2T4NlMHqUHnaJJWNFr5JvnKixfqd2oqixkQTuAHDKUgl2zweXjacMpe6qdhWFI+PavTKXp5dwsFkeBxWW9UQJH6MN2AmlPX0h4Gnq1HNhL8NnqXrblCFaZ6fWNBeeBhz32Fj1/dACMbZI6PdvZHvw2v9Z+Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(36756003)(2906002)(2616005)(83380400001)(82310400004)(356005)(81166007)(8936002)(5660300002)(86362001)(40460700003)(508600001)(70586007)(47076005)(6666004)(36860700001)(4326008)(26005)(186003)(7696005)(16526019)(316002)(54906003)(110136005)(8676002)(70206006)(1076003)(336012)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 10:15:26.1809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4bc049d-d84e-4457-9cc6-08d9efa2eb66 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4299 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The init_freq_invariance_cppc code actually doesn't need the SMP functionality. So setting the CONFIG_SMP as the check condition for init_freq_invariance_cppc may cause the confusion to misunderstand the CPPC. And the x86 CPPC file is better space to store the CPPC related functions, while the init_freq_invariance_cppc is out of smpboot, that means, the CONFIG_SMP won't be mandatory condition any more. And It's more clear than before. Signed-off-by: Huang Rui --- arch/x86/include/asm/topology.h | 4 +--- arch/x86/kernel/acpi/cppc.c | 14 ++++++++++++++ arch/x86/kernel/smpboot.c | 20 -------------------- 3 files changed, 15 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index c35005a03768..9c73d62f7276 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -225,12 +225,10 @@ static inline void init_freq_invariance(bool secondary, bool cppc_ready) } #endif -#if defined(CONFIG_ACPI_CPPC_LIB) && defined(CONFIG_SMP) +#ifdef CONFIG_ACPI_CPPC_LIB void init_freq_invariance_cppc(void); #define init_freq_invariance_cppc init_freq_invariance_cppc -#endif -#ifdef CONFIG_ACPI_CPPC_LIB bool amd_set_max_freq_ratio(u64 *ratio); #else static inline bool amd_set_max_freq_ratio(u64 *ratio) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index f0be5058e3e3..df1644d9b3b6 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -87,3 +87,17 @@ bool amd_set_max_freq_ratio(u64 *ratio) return true; } + +static DEFINE_MUTEX(freq_invariance_lock); + +void init_freq_invariance_cppc(void) +{ + static bool secondary; + + mutex_lock(&freq_invariance_lock); + + init_freq_invariance(secondary, true); + secondary = true; + + mutex_unlock(&freq_invariance_lock); +} diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 8f2ff9be0fcc..2ef14772dc04 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -83,10 +83,6 @@ #include #include -#ifdef CONFIG_ACPI_CPPC_LIB -#include -#endif - /* representing HT siblings of each logical CPU */ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); @@ -2156,22 +2152,6 @@ void init_freq_invariance(bool secondary, bool cppc_ready) } } -#ifdef CONFIG_ACPI_CPPC_LIB -static DEFINE_MUTEX(freq_invariance_lock); - -void init_freq_invariance_cppc(void) -{ - static bool secondary; - - mutex_lock(&freq_invariance_lock); - - init_freq_invariance(secondary, true); - secondary = true; - - mutex_unlock(&freq_invariance_lock); -} -#endif - static void disable_freq_invariance_workfn(struct work_struct *work) { static_branch_disable(&arch_scale_freq_key);