From patchwork Tue Feb 15 05:16:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12746524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0650BC433F5 for ; Tue, 15 Feb 2022 05:49:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=uAEzEENPusUMlyc+M5YLOanGlpD/cU5hjUrUEmQAE3U=; b=eQgN5g6Z72d0F4 u7MpBQNChoB1R2k06dTjQUG334zPfzF7xq2CQPwRvk/50QOO8HxkbksCt2TPyyo0GMrorOkStpscZ X6kaz7IftpEvuQ09GJ5bDAzupdGpOkvJj6hL0YaBY+uoI6+WhQYFQQg1hN7M0sVXCfmWsTXUanBGA SIB3oolAJTd8apF1Jv2NfA3c52Vi7ZPNCj8hN2FqU5ObjKxb6PvrJDov9eLsUxbzzrwjwD+fehRu8 NQFB2nmcbKWxPSqab82eifHTYAK6sawmAdFjHEDHPjWVJ9S6Q8JiwA/AjdvB5Z0nFNZF23kXT1gwS E0x+AmNW8ZeEsCgBYW9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJqhY-000MSi-LZ; Tue, 15 Feb 2022 05:48:36 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJqhL-000MLD-Hf for linux-arm-kernel@lists.infradead.org; Tue, 15 Feb 2022 05:48:25 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 79F351A22D7; Tue, 15 Feb 2022 06:48:19 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 4B08D1A004A; Tue, 15 Feb 2022 06:48:19 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id CD17B183AC8A; Tue, 15 Feb 2022 13:48:17 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, shawnguo@kernel.org Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v3 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support Date: Tue, 15 Feb 2022 13:16:31 +0800 Message-Id: <1644902192-12957-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220214_214823_747807_C3B5AA13 X-CRM114-Status: GOOD ( 10.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In the i.MX6QP sabresd board(sch-28857) design, one external oscillator is powered up by vgen3 and used as the PCIe reference clock source by the endpoint device. If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would has to be in bypass mode, and ENET clocks would be messed up. To keep things simple, let RC use the internal PLL as reference clock and set vgen3 always on to enable the external oscillator for endpoint device on i.MX6QP sabresd board. NOTE: This reference clock setup is used to pass the GEN2 TX compliance tests, and isn't recommended as a setup in the end-user design. Signed-off-by: Richard Zhu --- arch/arm/boot/dts/imx6qp-sabresd.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index 480e73183f6b..083cf90bcab5 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -50,8 +50,14 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 }; }; +&vgen3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +}; + &pcie { - status = "disabled"; + status = "okay"; }; &sata { From patchwork Tue Feb 15 05:16:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12746523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 127A7C433F5 for ; Tue, 15 Feb 2022 05:49:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GK72zkxCy3M2OpvQAXVwth6ZyhhF2Pp41HVTiaNvsPE=; b=H0JlZdoAbwbU7V IHu0494nP2JTwXslCUKsWBMZYKhkxl17iiBQsGU54gdTvYDgxufy05d1CsPJNuuTIQWqz/s/QIMpa rBiB+gliHgNEEqKm87NAbqemwNXEsALYMzNlRU45RYNE7aLSEm9MsZlMMHy8ivho+N8wuru9xp4Jq uAhdVNYLrM9o8ljmuvj8QjQyUnQtjxuhHnuWBd0JWY5Ieepwc3ovAI5+ytUxYCrQuqxRMp4nM/IVw UCU8p+JnS+IFq+AyVsIqtGFDGgbqPxqv5bFqPN9FVMpd7tjznIEvmoOsFdpfVzOCj64dkMNhyftRg QeP/aF84oPZZGPTEc9Tg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJqhO-000MN4-Kd; Tue, 15 Feb 2022 05:48:26 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJqhL-000MLC-He for linux-arm-kernel@lists.infradead.org; Tue, 15 Feb 2022 05:48:24 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 815B61A185A; Tue, 15 Feb 2022 06:48:20 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 49CF91A22DA; Tue, 15 Feb 2022 06:48:20 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id CA843183AD07; Tue, 15 Feb 2022 13:48:18 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, shawnguo@kernel.org Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v3 2/2] PCI: imx6: Enable i.MX6QP PCIe power management support Date: Tue, 15 Feb 2022 13:16:32 +0800 Message-Id: <1644902192-12957-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644902192-12957-1-git-send-email-hongxing.zhu@nxp.com> References: <1644902192-12957-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220214_214823_748185_C8901318 X-CRM114-Status: GOOD ( 11.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org i.MX6QP PCIe supports the reset logic, thus it can reset itself to the initialized state when exit from L2 or L3 states. Enable the i.MX6QP PCIe suspend/resume operations support. Signed-off-by: Richard Zhu Reviewed-by: Lucas Stach --- drivers/pci/controller/dwc/pci-imx6.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 784801f2f9e6..62262483470a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -995,6 +995,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) /* Others poke directly at IOMUXC registers */ switch (imx6_pcie->drvdata->variant) { case IMX6SX: + case IMX6QP: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, IMX6SX_GPR12_PCIE_PM_TURN_OFF); @@ -1307,7 +1308,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX6QP] = { .variant = IMX6QP, .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, + IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | + IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, }, [IMX7D] = {