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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o5sm690868qtp.48.2022.02.15.01.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:05:38 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH] target/riscv: Add isa extenstion strings to the device tree Date: Tue, 15 Feb 2022 01:05:30 -0800 Message-Id: <20220215090530.911828-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::731 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=atishp@rivosinc.com; helo=mail-qk1-x731.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.904, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Append the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b0a40b83e7a8..c70260d0df15 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,9 @@ /* RISC-V CPU definitions */ +/* This includes the null terminated character '\0' */ +#define MAX_ISA_EXT_LEN 256 + static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; const char * const riscv_int_regnames[] = { @@ -881,10 +884,26 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } +static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int max_str_len) +{ + int offset = strnlen(isa_str, max_str_len); + + if (cpu->cfg.ext_svpbmt) { + offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svpbmt"); + } + if ((offset < max_str_len) && cpu->cfg.ext_svinval) { + offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svinval"); + } + if ((offset < max_str_len) && (cpu->cfg.ext_svnapot)) { + offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svnapot"); + } +} + char *riscv_isa_string(RISCVCPU *cpu) { int i; - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; + const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + + MAX_ISA_EXT_LEN; char *isa_str = g_new(char, maxlen); char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); for (i = 0; i < sizeof(riscv_exts); i++) { @@ -893,6 +912,8 @@ char *riscv_isa_string(RISCVCPU *cpu) } } *p = '\0'; + riscv_isa_string_ext(cpu, isa_str, maxlen); + return isa_str; }