From patchwork Tue Feb 15 10:03:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12746829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93B9BC433EF for ; Tue, 15 Feb 2022 10:03:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234362AbiBOKDk (ORCPT ); Tue, 15 Feb 2022 05:03:40 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:40122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230356AbiBOKDk (ORCPT ); Tue, 15 Feb 2022 05:03:40 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B978196; Tue, 15 Feb 2022 02:03:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644919409; x=1676455409; h=from:to:cc:subject:date:message-id; bh=PX/WHKWbkuwa/EAALLC2/n7hI8uaF1SS9QQ5iBOgSbM=; b=PcLjoarUW1XyjC9AU5rdloqvXO9IU2yd2QPVtLlsUITldfE31w83M89g 0pPobVntkMyppuz+Fb+LJei3stl7IzQW4nxnGOpPnOxdzdYU8He1Tu0wJ bIYxIX2XAn9GShg9ywpy7mPKTY7GGci/8kH3ZO8tpkZQS8sEsZ1SitrUJ 8=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 15 Feb 2022 02:03:29 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Feb 2022 02:03:28 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 15 Feb 2022 15:33:26 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 256EE466C; Tue, 15 Feb 2022 15:33:25 +0530 (+0530) From: Rohit Agarwal To: manivannan.sadhasivam@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 2/7] mailbox: qcom: Add support for SDX65 APCS IPC Date: Tue, 15 Feb 2022 15:33:20 +0530 Message-Id: <1644919400-27487-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In SDX65, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Rohit Agarwal --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9325d2a..54d7659 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" }; +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); From patchwork Tue Feb 15 10:02:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12746828 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48C97C433FE for ; Tue, 15 Feb 2022 10:02:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230172AbiBOKCo (ORCPT ); Tue, 15 Feb 2022 05:02:44 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234175AbiBOKCg (ORCPT ); Tue, 15 Feb 2022 05:02:36 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 751A010F224; Tue, 15 Feb 2022 02:02:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644919344; x=1676455344; h=from:to:cc:subject:date:message-id; bh=qPVqXVUN2mGaNrVex8TfRvlY1eCUOH8rfs+vVpRk03Q=; b=Tzp0tX7tcwBQ8GnVZMJ/RaJWW0/saLX4+/xXNMIRc83q3V8Rxdqb5S2D 0I/JOA+0CQvi9AZQs+bkxgQxnmcyleqebxJofywP8szWcRvu5vtNmSbFA ksBcCkzViNwYk2+RPx8gZB0Jg6EXz4iJDKwOU7huDH7l4LMGXOc/LMgaB I=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 15 Feb 2022 02:02:24 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Feb 2022 02:02:23 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 15 Feb 2022 15:32:21 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id C735D466C; Tue, 15 Feb 2022 15:32:19 +0530 (+0530) From: Rohit Agarwal To: manivannan.sadhasivam@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 4/7] clk: qcom: Add A7 PLL support for SDX65 Date: Tue, 15 Feb 2022 15:32:18 +0530 Message-Id: <1644919338-27393-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for PLL found in Qualcomm SDX65 platforms which is used to provide clock to the Cortex A7 CPU via a mux. This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by: Rohit Agarwal Reviewed-by: Stephen Boyd --- drivers/clk/qcom/Kconfig | 6 +++--- drivers/clk/qcom/a7-pll.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6cd0634..10d75d3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -29,11 +29,11 @@ config QCOM_A53PLL devices. config QCOM_A7PLL - tristate "SDX55 A7 PLL" + tristate "A7 PLL driver for SDX55 and SDX65" help - Support for the A7 PLL on SDX55 devices. It provides the CPU with + Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with frequencies above 1GHz. - Say Y if you want to support higher CPU frequencies on SDX55 + Say Y if you want to support higher CPU frequencies on SDX55 and SDX65 devices. config QCOM_CLK_APCS_MSM8916 diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c index c4a53e5..adb2121 100644 --- a/drivers/clk/qcom/a7-pll.c +++ b/drivers/clk/qcom/a7-pll.c @@ -84,6 +84,7 @@ static int qcom_a7pll_probe(struct platform_device *pdev) static const struct of_device_id qcom_a7pll_match_table[] = { { .compatible = "qcom,sdx55-a7pll" }, + { .compatible = "qcom,sdx65-a7pll" }, { } }; MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table); From patchwork Tue Feb 15 10:09:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12746851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09929C433FE for ; Tue, 15 Feb 2022 10:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236315AbiBOKJk (ORCPT ); Tue, 15 Feb 2022 05:09:40 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233726AbiBOKJj (ORCPT ); Tue, 15 Feb 2022 05:09:39 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89A1B88B1D; Tue, 15 Feb 2022 02:09:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644919770; x=1676455770; h=from:to:cc:subject:date:message-id; bh=6AwSMXffc+ZIF68gcqh0h7X3F8Mo1HWIO+7WbtTu0i4=; b=RiIlFbl8L32mEk6Ub85kj8tMvE/5zyiUGuXS3Ighwpl2/DutdLK9r6yN s3l6IIgxbY4G+RaYUqfTsNUHyCnB96WX3i8GE4hbokz+k1Oee40zg60G5 0ZrgfKtAIBs9pouixgBo6/5Q9N1zGqmuAI8Ppd3BwK0PVoZMmZQkH3t6N E=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 15 Feb 2022 02:09:30 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Feb 2022 02:09:28 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 15 Feb 2022 15:39:16 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 2EC904665; Tue, 15 Feb 2022 15:39:16 +0530 (+0530) From: Rohit Agarwal To: manivannan.sadhasivam@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 7/7] clk: qcom: Add SDX65 APCS clock controller support Date: Tue, 15 Feb 2022 15:39:13 +0530 Message-Id: <1644919753-28855-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a driver config support for the SDX65 APCS clock controller. It is part of the APCS hardware block, which among other things implements a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL This is required for enabling CPU frequency scaling on SDX65-based platforms. Signed-off-by: Rohit Agarwal --- drivers/clk/qcom/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 10d75d3..05abf78 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996 drivers for dynamic power management. config QCOM_CLK_APCS_SDX55 - tristate "SDX55 APCS Clock Controller" + tristate "SDX55 and SDX65 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST help - Support for the APCS Clock Controller on SDX55 platform. The + Support for the APCS Clock Controller on SDX55, SDX65 platform. The APCS is managing the mux and divider which feeds the CPUs. Say Y if you want to support CPU frequency scaling on devices - such as SDX55. + such as SDX55, SDX65. config QCOM_CLK_RPM tristate "RPM based Clock Controller"