From patchwork Tue Feb 15 17:09:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA044C433F5 for ; Tue, 15 Feb 2022 17:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242243AbiBORKT (ORCPT ); Tue, 15 Feb 2022 12:10:19 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242242AbiBORKS (ORCPT ); Tue, 15 Feb 2022 12:10:18 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1385311ADDB for ; Tue, 15 Feb 2022 09:10:07 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id v12so33299404wrv.2 for ; Tue, 15 Feb 2022 09:10:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=46n4LaD4ZyMBoEv7QyqZkVx2QkFYWM4XtM2ZRYBTQAc=; b=H/pVHnep84f4SO5mEUh7ccuxHhCZBOhnjSDZOxD0osdtblLDsY94M3esKJn6TdtW07 us9EUXoRcIScwy8t4CVk8+2G3pLob+uD9g5HKJa/Jh/XP7V8kh5am3aqwXoIo/i2MoVo j3GhmQkVPGi2mz6EXqCxHJV+aPLhMzrDJcrVUqmrrcD7Iw9vE+CtF3SZhc/5imEdkmrL EPZNUWCuP+RYLTe3MMbqn9zwBP7yUyPJj2vAawjeYSpqgl7UzfiMgyT4JsVGAHEWWeXU FtDjDeHe6BeNKal560a9Axxd89ybP+tVXNkrMMp2nyqSAOpLszKiaG+YOEDhfG+b6e3O F+tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=46n4LaD4ZyMBoEv7QyqZkVx2QkFYWM4XtM2ZRYBTQAc=; b=anK/vCttAZMiCjrmG8chfbUZ3LuBzi73GG5b6RQ0Cnhpykvx0Kd2UyBtvg6axB5ILK Hetn4gm79HpTOuzmh3J77MJKz7Aza4W7q1x8CI8cy0rMNOhW2JTRMwB3ChqRNbF/vBA+ Tl7YeEYWg4888Rn81YT7YPoAw5+gjkaUO2oTsLTWyaKb8wM9OQ2XK1FudK1QS1KdHw0S FXbKW+ysyN0dRssxH5/slmgsVt7jaDQxinuDiCT0nEud1kXi8eK2BYyaOcZMV0v9K+FG YZjBQpZbemT7svevz060K1MjqVIdzHrkAnareM82WTfs1W34tXdGJMXHn2b68jyrZLsB DaZw== X-Gm-Message-State: AOAM532NiLt7Pyif8ns3cnEL7i42GS3HMUKg6ad8nMIACxwZ3Y5Cvz3V O2PiLDdntRKxYt0Gr4dQ64YgkQ== X-Google-Smtp-Source: ABdhPJz5pYDeTwmHDRpO+vYbnSvTuSh+CQZhIr3yipQ9zMZblDzDsedgRSWYZw/JHp+eFKWo6H5jLA== X-Received: by 2002:a5d:59a2:: with SMTP id p2mr4078620wrr.304.1644945004462; Tue, 15 Feb 2022 09:10:04 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:03 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 1/9] spmi: add a helper to look up an SPMI device from a device node Date: Tue, 15 Feb 2022 17:09:43 +0000 Message-Id: <20220215170951.1233375-2-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The helper function spmi_device_from_of() takes a device node and returns the SPMI device associated with it. This is like of_find_device_by_node but for SPMI devices. Signed-off-by: Caleb Connolly --- drivers/spmi/spmi.c | 17 +++++++++++++++++ include/linux/spmi.h | 2 ++ 2 files changed, 19 insertions(+) diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c index b37ead9e2fad..de550b777451 100644 --- a/drivers/spmi/spmi.c +++ b/drivers/spmi/spmi.c @@ -386,6 +386,23 @@ static struct bus_type spmi_bus_type = { .uevent = spmi_drv_uevent, }; +/** + * spmi_device_from_of() - get the associated SPMI device from a device node + * + * @np: device node + * + * Returns the struct spmi_device associated with a device node or NULL. + */ +inline struct spmi_device *spmi_device_from_of(struct device_node *np) +{ + struct device *dev = bus_find_device_by_of_node(&spmi_bus_type, np); + + if (dev) + return to_spmi_device(dev); + return NULL; +} +EXPORT_SYMBOL_GPL(spmi_device_from_of); + /** * spmi_controller_alloc() - Allocate a new SPMI device * @ctrl: associated controller diff --git a/include/linux/spmi.h b/include/linux/spmi.h index 729bcbf9f5ad..6ee476bc1cd6 100644 --- a/include/linux/spmi.h +++ b/include/linux/spmi.h @@ -7,6 +7,7 @@ #include #include #include +#include /* Maximum slave identifier */ #define SPMI_MAX_SLAVE_ID 16 @@ -164,6 +165,7 @@ static inline void spmi_driver_unregister(struct spmi_driver *sdrv) module_driver(__spmi_driver, spmi_driver_register, \ spmi_driver_unregister) +inline struct spmi_device *spmi_device_from_of(struct device_node *np); int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf); int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf, size_t len); From patchwork Tue Feb 15 17:09:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46D8EC433FE for ; Tue, 15 Feb 2022 17:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242253AbiBORKV (ORCPT ); Tue, 15 Feb 2022 12:10:21 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242242AbiBORKV (ORCPT ); Tue, 15 Feb 2022 12:10:21 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DFF911ADD1 for ; Tue, 15 Feb 2022 09:10:08 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id k127-20020a1ca185000000b0037bc4be8713so1945806wme.3 for ; Tue, 15 Feb 2022 09:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+0fKnwESxbyMOLhjEzw7OuPxJ00+TW/f1NZ6wRXKcHg=; b=y8evBfxxr06DmveFG5bkY5xtuBahVoxKB1Ar7y3r4czWv77FRJknvOBAi0RbRreaSO 108djHuiaPKrap3/4edZZB9aQjrcaDFVj6edJqC8H+w/TAvJG8HEb0yO19EAKuEog9Rp 41wlmvjBO2F/MZhBLKVgW+1M9nJIVzEyz3yTocv/T06lHdmW71AyApRvaI0M6M9DFVCB yhnwL95De4M7+QS6rfK9qM/gWtVxkpRHy77h7bg05OiRaczjbPTZBnhtP8P7UKtSQU5N DtMTN0M/Fl7o86gt5uYI+Bkaksj1F9qVYRNLSy9Q0PXs90Q3ziwLxTKOx7XGj5yHH/u+ QNiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+0fKnwESxbyMOLhjEzw7OuPxJ00+TW/f1NZ6wRXKcHg=; b=Jzx5HRRHlpUUs9+wTZG9mwS/3HPKzw+38k8AJgwFniL7vuFEwp/V18V9E/YetUDxoj +ih9j/YtQPGfyO1dzWVpKGz4x6F1m845YvADv4TjpzUTjDKQmwvgGVm4byNPAXJ+F0qW qYMo9SylciseUTjuDaVKzFrsB7yY0bQVXDmpo/SB0PgzBmiVHtGxmaZmMXLgHzUC1O5/ UHpA8pyPT2QxsjWgdApwa0FwP8M39lvdkllJulmz7rpYc+LcoL2cmHelBivKPXCLHPRh /ESvmjxMExAlKvO0hSh7D3rwobn5DJ07xD/zhE10YM+9DUlAtzLFKcPDsOCmu6bEFfy7 5S3Q== X-Gm-Message-State: AOAM533U1yKv5IL1u05CFOHgjxfXeT1d/hA9qhzt46ZjyG/D8JvpqkeF nxEr/SrgDii/EW5lq3HRV4bthw== X-Google-Smtp-Source: ABdhPJzl13GtD5wJDsDrbYBEmIF5AwmTP3jk7OQ82XRH6nJJMRjjnSwm1oTlS3duPhw36n1FhuNFdg== X-Received: by 2002:a1c:29c7:0:b0:37b:b72f:e26 with SMTP id p190-20020a1c29c7000000b0037bb72f0e26mr3922442wmp.23.1644945006962; Tue, 15 Feb 2022 09:10:06 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:06 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 2/9] mfd: qcom-spmi-pmic: expose the PMIC revid information to clients Date: Tue, 15 Feb 2022 17:09:44 +0000 Message-Id: <20220215170951.1233375-3-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some PMIC functions such as the RRADC need to be aware of the PMIC chip revision information to implement errata or otherwise adjust behaviour, export the PMIC information to enable this. This is specifically required to enable the RRADC to adjust coefficients based on which chip fab the PMIC was produced in, this can vary per unique device and therefore has to be read at runtime. Signed-off-by: Caleb Connolly --- drivers/mfd/qcom-spmi-pmic.c | 176 ++++++++++++++++++++---------- include/soc/qcom/qcom-spmi-pmic.h | 60 ++++++++++ 2 files changed, 179 insertions(+), 57 deletions(-) create mode 100644 include/soc/qcom/qcom-spmi-pmic.h diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 1cacc00aa6c9..5e656485cd55 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -3,51 +3,26 @@ * Copyright (c) 2014, The Linux Foundation. All rights reserved. */ +#include +#include +#include #include #include +#include +#include #include +#include #include #include +#include #define PMIC_REV2 0x101 #define PMIC_REV3 0x102 #define PMIC_REV4 0x103 #define PMIC_TYPE 0x104 #define PMIC_SUBTYPE 0x105 - #define PMIC_TYPE_VALUE 0x51 -#define COMMON_SUBTYPE 0x00 -#define PM8941_SUBTYPE 0x01 -#define PM8841_SUBTYPE 0x02 -#define PM8019_SUBTYPE 0x03 -#define PM8226_SUBTYPE 0x04 -#define PM8110_SUBTYPE 0x05 -#define PMA8084_SUBTYPE 0x06 -#define PMI8962_SUBTYPE 0x07 -#define PMD9635_SUBTYPE 0x08 -#define PM8994_SUBTYPE 0x09 -#define PMI8994_SUBTYPE 0x0a -#define PM8916_SUBTYPE 0x0b -#define PM8004_SUBTYPE 0x0c -#define PM8909_SUBTYPE 0x0d -#define PM8028_SUBTYPE 0x0e -#define PM8901_SUBTYPE 0x0f -#define PM8950_SUBTYPE 0x10 -#define PMI8950_SUBTYPE 0x11 -#define PM8998_SUBTYPE 0x14 -#define PMI8998_SUBTYPE 0x15 -#define PM8005_SUBTYPE 0x18 -#define PM660L_SUBTYPE 0x1A -#define PM660_SUBTYPE 0x1B -#define PM8150_SUBTYPE 0x1E -#define PM8150L_SUBTYPE 0x1f -#define PM8150B_SUBTYPE 0x20 -#define PMK8002_SUBTYPE 0x21 -#define PM8009_SUBTYPE 0x24 -#define PM8150C_SUBTYPE 0x26 -#define SMB2351_SUBTYPE 0x29 - static const struct of_device_id pmic_spmi_id_table[] = { { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE }, { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE }, @@ -81,42 +56,118 @@ static const struct of_device_id pmic_spmi_id_table[] = { { } }; -static void pmic_spmi_show_revid(struct regmap *map, struct device *dev) +/** + * @brief Get a pointer to the base PMIC device + * + * @param dev the pmic function device + * @return const struct qcom_spmi_pmic* + * + * A PMIC can be represented by multiple SPMI devices, but + * only the base PMIC device will contain a reference to + * the revision information. + * + * This function takes a pointer to a function device and + * returns a pointer to the base PMIC device. + */ +const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev) +{ + struct spmi_device *sdev; + struct device_node *spmi_bus; + struct device_node *other_usid; + int function_parent_usid, ret; + u32 reg[2]; + + if (!of_match_device(pmic_spmi_id_table, dev->parent)) + return ERR_PTR(-EINVAL); + + sdev = to_spmi_device(dev->parent); + if (!sdev) + return ERR_PTR(-EINVAL); + + /* + * Quick return if the function device is already in the right + * USID + */ + if (sdev->usid % 2 == 0) + return spmi_device_get_drvdata(sdev); + + function_parent_usid = sdev->usid; + + /* + * Walk through the list of PMICs until we find the sibling USID. + * The goal is the find to previous sibling. Assuming there is no + * PMIC with more than 2 USIDs. We know that function_parent_usid + * is one greater than the base USID. + */ + spmi_bus = of_get_parent(sdev->dev.parent->of_node); + do { + other_usid = of_get_next_child(spmi_bus, other_usid); + ret = of_property_read_u32_array(other_usid, "reg", reg, 2); + if (ret) + return ERR_PTR(ret); + sdev = spmi_device_from_of(other_usid); + if (sdev == NULL) { + /* + * If the base USID for this PMIC hasn't probed yet + * but the secondary USID has, then we need to defer + * the function driver so that it will attempt to + * probe again when the base USID is ready. + */ + if (reg[0] == function_parent_usid - 1) + return ERR_PTR(-EPROBE_DEFER); + + continue; + } + + if (reg[0] == function_parent_usid - 1) + return spmi_device_get_drvdata(sdev); + } while (other_usid->sibling); + + return ERR_PTR(-ENODATA); +} +EXPORT_SYMBOL(qcom_pmic_get); + +static inline void pmic_print_info(struct device *dev, struct qcom_spmi_pmic *pmic) +{ + dev_info(dev, "%x: %s v%d.%d\n", + pmic->subtype, pmic->name, pmic->major, pmic->minor); +} + +static int pmic_spmi_load_revid(struct regmap *map, struct device *dev, + struct qcom_spmi_pmic *pmic) { - unsigned int rev2, minor, major, type, subtype; - const char *name = "unknown"; int ret, i; - ret = regmap_read(map, PMIC_TYPE, &type); + ret = regmap_read(map, PMIC_TYPE, &pmic->type); if (ret < 0) - return; + return ret; - if (type != PMIC_TYPE_VALUE) - return; + if (pmic->type != PMIC_TYPE_VALUE) + return ret; - ret = regmap_read(map, PMIC_SUBTYPE, &subtype); + ret = regmap_read(map, PMIC_SUBTYPE, &pmic->subtype); if (ret < 0) - return; + return ret; for (i = 0; i < ARRAY_SIZE(pmic_spmi_id_table); i++) { - if (subtype == (unsigned long)pmic_spmi_id_table[i].data) + if (pmic->subtype == (unsigned long)pmic_spmi_id_table[i].data) break; } if (i != ARRAY_SIZE(pmic_spmi_id_table)) - name = pmic_spmi_id_table[i].compatible; + pmic->name = devm_kstrdup_const(dev, pmic_spmi_id_table[i].compatible, GFP_KERNEL); - ret = regmap_read(map, PMIC_REV2, &rev2); + ret = regmap_read(map, PMIC_REV2, &pmic->rev2); if (ret < 0) - return; + return ret; - ret = regmap_read(map, PMIC_REV3, &minor); + ret = regmap_read(map, PMIC_REV3, &pmic->minor); if (ret < 0) - return; + return ret; - ret = regmap_read(map, PMIC_REV4, &major); + ret = regmap_read(map, PMIC_REV4, &pmic->major); if (ret < 0) - return; + return ret; /* * In early versions of PM8941 and PM8226, the major revision number @@ -124,14 +175,14 @@ static void pmic_spmi_show_revid(struct regmap *map, struct device *dev) * Increment the major revision number here if the chip is an early * version of PM8941 or PM8226. */ - if ((subtype == PM8941_SUBTYPE || subtype == PM8226_SUBTYPE) && - major < 0x02) - major++; + if ((pmic->subtype == PM8941_SUBTYPE || pmic->subtype == PM8226_SUBTYPE) && + pmic->major < 0x02) + pmic->major++; - if (subtype == PM8110_SUBTYPE) - minor = rev2; + if (pmic->subtype == PM8110_SUBTYPE) + pmic->minor = pmic->rev2; - dev_dbg(dev, "%x: %s v%d.%d\n", subtype, name, major, minor); + return 0; } static const struct regmap_config spmi_regmap_config = { @@ -144,14 +195,25 @@ static const struct regmap_config spmi_regmap_config = { static int pmic_spmi_probe(struct spmi_device *sdev) { struct regmap *regmap; + struct qcom_spmi_pmic *pmic; + int ret; regmap = devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + pmic = devm_kzalloc(&sdev->dev, sizeof(*pmic), GFP_KERNEL); + if (!pmic) + return -ENOMEM; + /* Only the first slave id for a PMIC contains this information */ - if (sdev->usid % 2 == 0) - pmic_spmi_show_revid(regmap, &sdev->dev); + if (sdev->usid % 2 == 0) { + ret = pmic_spmi_load_revid(regmap, &sdev->dev, pmic); + if (ret < 0) + return ret; + spmi_device_set_drvdata(sdev, pmic); + pmic_print_info(&sdev->dev, pmic); + } return devm_of_platform_populate(&sdev->dev); } diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h new file mode 100644 index 000000000000..a8a77be22cfc --- /dev/null +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2021 Linaro. All rights reserved. + * Copyright (c) 2021 Caleb Connolly + */ + +#ifndef __QCOM_PMIC_H__ +#define __QCOM_PMIC_H__ + +#define COMMON_SUBTYPE 0x00 +#define PM8941_SUBTYPE 0x01 +#define PM8841_SUBTYPE 0x02 +#define PM8019_SUBTYPE 0x03 +#define PM8226_SUBTYPE 0x04 +#define PM8110_SUBTYPE 0x05 +#define PMA8084_SUBTYPE 0x06 +#define PMI8962_SUBTYPE 0x07 +#define PMD9635_SUBTYPE 0x08 +#define PM8994_SUBTYPE 0x09 +#define PMI8994_SUBTYPE 0x0a +#define PM8916_SUBTYPE 0x0b +#define PM8004_SUBTYPE 0x0c +#define PM8909_SUBTYPE 0x0d +#define PM8028_SUBTYPE 0x0e +#define PM8901_SUBTYPE 0x0f +#define PM8950_SUBTYPE 0x10 +#define PMI8950_SUBTYPE 0x11 +#define PM8998_SUBTYPE 0x14 +#define PMI8998_SUBTYPE 0x15 +#define PM8005_SUBTYPE 0x18 +#define PM660L_SUBTYPE 0x1A +#define PM660_SUBTYPE 0x1B +#define PM8150_SUBTYPE 0x1E +#define PM8150L_SUBTYPE 0x1f +#define PM8150B_SUBTYPE 0x20 +#define PMK8002_SUBTYPE 0x21 +#define PM8009_SUBTYPE 0x24 +#define PM8150C_SUBTYPE 0x26 +#define SMB2351_SUBTYPE 0x29 + +#define PMI8998_FAB_ID_SMIC 0x11 +#define PMI8998_FAB_ID_GF 0x30 + +#define PM660_FAB_ID_GF 0x0 +#define PM660_FAB_ID_TSMC 0x2 +#define PM660_FAB_ID_MX 0x3 + +struct qcom_spmi_pmic { + unsigned int type; + unsigned int subtype; + unsigned int major; + unsigned int minor; + unsigned int rev2; + const char *name; +}; + +struct device; + +const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev); + +#endif /* __QCOM_PMIC_H__ */ From patchwork Tue Feb 15 17:09:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F716C4332F for ; Tue, 15 Feb 2022 17:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242249AbiBORKW (ORCPT ); Tue, 15 Feb 2022 12:10:22 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242251AbiBORKV (ORCPT ); Tue, 15 Feb 2022 12:10:21 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B97811ADFE for ; Tue, 15 Feb 2022 09:10:09 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id l12-20020a7bc34c000000b003467c58cbdfso1955835wmj.2 for ; Tue, 15 Feb 2022 09:10:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FNxZnQWwG3AA+5zjZr6bjMk+OGB5iWm30KygedH2/Bk=; b=ep/4hCQb5RaC5Tzqem8/CIvIT7d+NpFQwghUrK3EO/iigYCWM8xeLNJ4LGlq3Wl9h8 SbG3kDysAoP6KObJWItaLyRd4WSLWbvff9+JpqG051klULWFJ2CgkYD4j+Cb6ON1/wHe eJRb93La+4bI2fheJcDis8uFMKHGndYm/vMq6SyFN/cYzcrKD6Weid4IZ3YZvpJMZW7C mD1+b0EfvRO4y8a0e+roRgLOGllQP1CubHCs6tUG+01pnB/a9LWr98k0Sjfhz3BW+Zg1 S3xhwXTMqeLNbLv2kf9JZeL6eIvBttaL9Tj3kkCYwTjYIWAn1Vv7fWOk/xwBGTNK+zkJ WXbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FNxZnQWwG3AA+5zjZr6bjMk+OGB5iWm30KygedH2/Bk=; b=WbCVa2FkPX0Lztuaffe2ugyHnnjjWTZBFH/dszXv4mAOzvcLLkdirmJ7FKIPYc33lW H8nJXOapAuWlrn5OJTFqboclVNr4yAhqzILbbtI1FycaJpUFLHFK6JTEi4F+GXX9w6jf qplygd7EPWlhqZx4ags7a2d/hhC4qjvPeUNhv1cci2+nkUFtoekgU7gnifj2oxpwZBJR uBRrXDsL397OX+NjQbFg8Arwe5F+XBu/TSB1Wkgh3DYoh76n4cKgICqMPne0ITT5RWce 1aS/+zKPPVQxYm9hDh/eZwk9ljS560YwZpGDitVpNKZ7iuuUvIFJJ8RsCUxKwF+cI0dV UkPQ== X-Gm-Message-State: AOAM531jO0PAKxvNDr/50QzgcCkS7fnRcu7q0UEXGe61W+lc5TGreG3r 7g/Q1Vcb8QrYmCAmIESxY+ca2Q== X-Google-Smtp-Source: ABdhPJzh02beNPLnx2/bbu9JSgtusNdhn9Ac1WPZCJdRDKqF3hzTT46GIqYZwarHI7jcA0+lk2bEQQ== X-Received: by 2002:a1c:f30b:0:b0:37b:b5de:c804 with SMTP id q11-20020a1cf30b000000b0037bb5dec804mr3920422wmq.166.1644945008187; Tue, 15 Feb 2022 09:10:08 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:07 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 3/9] mfd: qcom-spmi-pmic: read fab id on supported PMICs Date: Tue, 15 Feb 2022 17:09:45 +0000 Message-Id: <20220215170951.1233375-4-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The PMI8998 and PM660 expose the fab_id, this is needed by drivers like the RRADC to calibrate ADC values. Signed-off-by: Caleb Connolly --- drivers/mfd/qcom-spmi-pmic.c | 7 +++++++ include/soc/qcom/qcom-spmi-pmic.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 5e656485cd55..28600e5899bc 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -21,6 +21,7 @@ #define PMIC_REV4 0x103 #define PMIC_TYPE 0x104 #define PMIC_SUBTYPE 0x105 +#define PMIC_FAB_ID 0x1f2 #define PMIC_TYPE_VALUE 0x51 static const struct of_device_id pmic_spmi_id_table[] = { @@ -169,6 +170,12 @@ static int pmic_spmi_load_revid(struct regmap *map, struct device *dev, if (ret < 0) return ret; + if (pmic->subtype == PMI8998_SUBTYPE || pmic->subtype == PM660_SUBTYPE) { + ret = regmap_read(map, PMIC_FAB_ID, &pmic->fab_id); + if (ret < 0) + return ret; + } + /* * In early versions of PM8941 and PM8226, the major revision number * started incrementing from 0 (eg 0 = v1.0, 1 = v2.0). diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h index a8a77be22cfc..c821f6c6c8a8 100644 --- a/include/soc/qcom/qcom-spmi-pmic.h +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -50,6 +50,7 @@ struct qcom_spmi_pmic { unsigned int major; unsigned int minor; unsigned int rev2; + unsigned int fab_id; const char *name; }; From patchwork Tue Feb 15 17:09:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E95EC433EF for ; Tue, 15 Feb 2022 17:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242258AbiBORKY (ORCPT ); Tue, 15 Feb 2022 12:10:24 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242248AbiBORKY (ORCPT ); Tue, 15 Feb 2022 12:10:24 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8FBC11ADDB for ; Tue, 15 Feb 2022 09:10:10 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id q7so33142506wrc.13 for ; Tue, 15 Feb 2022 09:10:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BXhDDcjJdPDbZfpGFJmQRsA5lMP0BnPrEwgZzVXptZc=; b=q5K1OyvaYsOINgGfvSiQqSu6VbFtQjFkcNKc6vQ0TPyc6ylGrB7Z7szgzSS8aEBhOa k7+7r4zLNOaMBB8Ydscn9JDuTrQKFnmnVhVkD2+67vBodr2VySr8x1WGy2dQBGeh/lww znPHdyoP2oGTI6WSPWgtzdJSrUTo6KO7nOKoqNUl1Ew7jOxQKP8R8yQrCJzzjdUxmlot TH6e8uUBJ4/Yei2/GUzC4ICKHfW/j/g0EwXGQOWwLC0NVAfVIwFrFXUAp3flOhURZRTV Nju3uIVHkptaEZC0lxNRbip6Xwf6odDwETUOXGsbt5q8ulDpE/0KhGXM7ELE6fFxDl7Y nILg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BXhDDcjJdPDbZfpGFJmQRsA5lMP0BnPrEwgZzVXptZc=; b=pkMEHfe0kcAMwf1NgJ5Jn4o8I3mZdFASmAz/2E5qlxC6GlhIr39wr/RmC3H4IbapXM LiU49vuwfRgYAMxGuND5L27+IzLxvOWhpPLbujCvfioH4Y4yQdwNu2LebmY9qhIS8E8j dvaN0p2gMkX3+Wpu0qt1BAi2DFbXGyeEXiMmp3ai6MDW/r81W0HXORWwhpQ9NzImUfnS 3NY/RDPU7GFw9sEOUqRETGIv+y3eK9n8dPGUokKaWcwpki1b5Ush54WwwiXWAM2nqdwc BPUj/PEyfk/HwOOAtPU+v2zgCtusVD1vt//L/I9v/OtBJFKWvTfLXFCJf+ywZlkA6Mx2 cDQA== X-Gm-Message-State: AOAM5330H0rVkX9Kex8VmdmpTJl5s/9DkCd9nc0dwSFFYCcnScBUabE5 lnHqano0hrk3rVOLfc9ggSeoqA== X-Google-Smtp-Source: ABdhPJyV1Ikotpbp26m5NUUhQNx7DE9+PzwwpTxzHqmHkddhVMh0Ip1K8aekFgLxFWb5YzVHtkx1bQ== X-Received: by 2002:adf:ea0d:: with SMTP id q13mr3939589wrm.191.1644945009289; Tue, 15 Feb 2022 09:10:09 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:08 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org, Rob Herring Subject: [PATCH v6 4/9] dt-bindings: iio: adc: document qcom-spmi-rradc Date: Tue, 15 Feb 2022 17:09:46 +0000 Message-Id: <20220215170951.1233375-5-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dt-binding docs for the Qualcomm SPMI RRADC found in PMICs like PMI8998 and PMI8994 Signed-off-by: Caleb Connolly Reviewed-by: Rob Herring --- .../bindings/iio/adc/qcom,spmi-rradc.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml new file mode 100644 index 000000000000..11d47c46a48d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC Round Robin ADC + +maintainers: + - Caleb Connolly + +description: | + The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to read the + voltage, current and temperature for supported peripherals such as the battery thermistor + die temperature, charger temperature, USB and DC input voltage / current and battery ID + resistor. + +properties: + compatible: + enum: + - qcom,pmi8998-rradc + - qcom,pm660-rradc + + reg: + description: rradc base address and length in the SPMI PMIC register map + maxItems: 1 + + qcom,batt-id-delay-ms: + description: + Sets the hardware settling time for the battery ID resistor. + enum: [0, 1, 4, 12, 20, 40, 60, 80] + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + pmic_rradc: adc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + }; + }; +... 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[81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:09 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 5/9] iio: adc: qcom-spmi-rradc: introduce round robin adc Date: Tue, 15 Feb 2022 17:09:47 +0000 Message-Id: <20220215170951.1233375-6-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Round Robin ADC is responsible for reading data about the rate of charge from the USB or DC input ports, it can also read the battery ID (resistence), skin temperature and the die temperature of the pmic. It is found on the PMI8998 and PM660 Qualcomm PMICs. Signed-off-by: Caleb Connolly --- drivers/iio/adc/Kconfig | 12 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-rradc.c | 1016 +++++++++++++++++++++++++++++ 3 files changed, 1029 insertions(+) create mode 100644 drivers/iio/adc/qcom-spmi-rradc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 4fdc8bfbb407..66557b434fa8 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -812,6 +812,18 @@ config QCOM_PM8XXX_XOADC To compile this driver as a module, choose M here: the module will be called qcom-pm8xxx-xoadc. +config QCOM_SPMI_RRADC + tristate "Qualcomm SPMI RRADC" + depends on MFD_SPMI_PMIC + help + This is for the PMIC Round Robin ADC driver. + + This driver exposes the battery ID resistor, battery thermal, PMIC die + temperature, charger USB in and DC in voltage and current. + + To compile this driver as a module, choose M here: the module will + be called qcom-qpmi-rradc. + config QCOM_SPMI_IADC tristate "Qualcomm SPMI PMIC current ADC" depends on SPMI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 4a8f1833993b..b0dd7f142abd 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_NPCM_ADC) += npcm_adc.o obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o +obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-rradc.c new file mode 100644 index 000000000000..c2d19ddd5f3b --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-rradc.c @@ -0,0 +1,1016 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Linaro Limited. + * Author: Caleb Connolly + * + * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include + +#define DRIVER_NAME "qcom-spmi-rradc" + +#define RR_ADC_EN_CTL 0x46 +#define RR_ADC_SKIN_TEMP_LSB 0x50 +#define RR_ADC_SKIN_TEMP_MSB 0x51 +#define RR_ADC_CTL 0x52 +#define RR_ADC_CTL_CONTINUOUS_SEL BIT(3) +#define RR_ADC_LOG 0x53 +#define RR_ADC_LOG_CLR_CTRL BIT(0) + +#define RR_ADC_FAKE_BATT_LOW_LSB 0x58 +#define RR_ADC_FAKE_BATT_LOW_MSB 0x59 +#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A +#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B + +#define RR_ADC_BATT_ID_CTRL 0x60 +#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0) +#define RR_ADC_BATT_ID_TRIGGER 0x61 +#define RR_ADC_BATT_ID_STS 0x62 +#define RR_ADC_BATT_ID_CFG 0x63 +#define BATT_ID_SETTLE_MASK GENMASK(7, 5) +#define RR_ADC_BATT_ID_5_LSB 0x66 +#define RR_ADC_BATT_ID_5_MSB 0x67 +#define RR_ADC_BATT_ID_15_LSB 0x68 +#define RR_ADC_BATT_ID_15_MSB 0x69 +#define RR_ADC_BATT_ID_150_LSB 0x6A +#define RR_ADC_BATT_ID_150_MSB 0x6B + +#define RR_ADC_BATT_THERM_CTRL 0x70 +#define RR_ADC_BATT_THERM_TRIGGER 0x71 +#define RR_ADC_BATT_THERM_STS 0x72 +#define RR_ADC_BATT_THERM_CFG 0x73 +#define RR_ADC_BATT_THERM_LSB 0x74 +#define RR_ADC_BATT_THERM_MSB 0x75 +#define RR_ADC_BATT_THERM_FREQ 0x76 + +#define RR_ADC_AUX_THERM_CTRL 0x80 +#define RR_ADC_AUX_THERM_TRIGGER 0x81 +#define RR_ADC_AUX_THERM_STS 0x82 +#define RR_ADC_AUX_THERM_CFG 0x83 +#define RR_ADC_AUX_THERM_LSB 0x84 +#define RR_ADC_AUX_THERM_MSB 0x85 + +#define RR_ADC_SKIN_HOT 0x86 +#define RR_ADC_SKIN_TOO_HOT 0x87 + +#define RR_ADC_AUX_THERM_C1 0x88 +#define RR_ADC_AUX_THERM_C2 0x89 +#define RR_ADC_AUX_THERM_C3 0x8A +#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B + +#define RR_ADC_USB_IN_V_CTRL 0x90 +#define RR_ADC_USB_IN_V_TRIGGER 0x91 +#define RR_ADC_USB_IN_V_STS 0x92 +#define RR_ADC_USB_IN_V_LSB 0x94 +#define RR_ADC_USB_IN_V_MSB 0x95 +#define RR_ADC_USB_IN_I_CTRL 0x98 +#define RR_ADC_USB_IN_I_TRIGGER 0x99 +#define RR_ADC_USB_IN_I_STS 0x9A +#define RR_ADC_USB_IN_I_LSB 0x9C +#define RR_ADC_USB_IN_I_MSB 0x9D + +#define RR_ADC_DC_IN_V_CTRL 0xA0 +#define RR_ADC_DC_IN_V_TRIGGER 0xA1 +#define RR_ADC_DC_IN_V_STS 0xA2 +#define RR_ADC_DC_IN_V_LSB 0xA4 +#define RR_ADC_DC_IN_V_MSB 0xA5 +#define RR_ADC_DC_IN_I_CTRL 0xA8 +#define RR_ADC_DC_IN_I_TRIGGER 0xA9 +#define RR_ADC_DC_IN_I_STS 0xAA +#define RR_ADC_DC_IN_I_LSB 0xAC +#define RR_ADC_DC_IN_I_MSB 0xAD + +#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0 +#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1 +#define RR_ADC_PMI_DIE_TEMP_STS 0xB2 +#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3 +#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4 +#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5 + +#define RR_ADC_CHARGER_TEMP_CTRL 0xB8 +#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9 +#define RR_ADC_CHARGER_TEMP_STS 0xBA +#define RR_ADC_CHARGER_TEMP_CFG 0xBB +#define RR_ADC_CHARGER_TEMP_LSB 0xBC +#define RR_ADC_CHARGER_TEMP_MSB 0xBD +#define RR_ADC_CHARGER_HOT 0xBE +#define RR_ADC_CHARGER_TOO_HOT 0xBF + +#define RR_ADC_GPIO_CTRL 0xC0 +#define RR_ADC_GPIO_TRIGGER 0xC1 +#define RR_ADC_GPIO_STS 0xC2 +#define RR_ADC_GPIO_LSB 0xC4 +#define RR_ADC_GPIO_MSB 0xC5 + +#define RR_ADC_ATEST_CTRL 0xC8 +#define RR_ADC_ATEST_TRIGGER 0xC9 +#define RR_ADC_ATEST_STS 0xCA +#define RR_ADC_ATEST_LSB 0xCC +#define RR_ADC_ATEST_MSB 0xCD +#define RR_ADC_SEC_ACCESS 0xD0 + +#define RR_ADC_PERPH_RESET_CTL2 0xD9 +#define RR_ADC_PERPH_RESET_CTL3 0xDA +#define RR_ADC_PERPH_RESET_CTL4 0xDB +#define RR_ADC_INT_TEST1 0xE0 +#define RR_ADC_INT_TEST_VAL 0xE1 + +#define RR_ADC_TM_TRIGGER_CTRLS 0xE2 +#define RR_ADC_TM_ADC_CTRLS 0xE3 +#define RR_ADC_TM_CNL_CTRL 0xE4 +#define RR_ADC_TM_BATT_ID_CTRL 0xE5 +#define RR_ADC_TM_THERM_CTRL 0xE6 +#define RR_ADC_TM_CONV_STS 0xE7 +#define RR_ADC_TM_ADC_READ_LSB 0xE8 +#define RR_ADC_TM_ADC_READ_MSB 0xE9 +#define RR_ADC_TM_ATEST_MUX_1 0xEA +#define RR_ADC_TM_ATEST_MUX_2 0xEB +#define RR_ADC_TM_REFERENCES 0xED +#define RR_ADC_TM_MISC_CTL 0xEE +#define RR_ADC_TM_RR_CTRL 0xEF + +#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7) +#define RR_ADC_TRIGGER_CTL BIT(0) + +#define RR_ADC_BATT_ID_RANGE 820 + +#define RR_ADC_BITS 10 +#define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS) +#define RR_ADC_FS_VOLTAGE_MV 2500 + +/* BATT_THERM 0.25K/LSB */ +#define RR_ADC_BATT_THERM_LSB_K 4 + +#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000 +#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3 +#define RR_ADC_DIE_TEMP_OFFSET 601400 +#define RR_ADC_DIE_TEMP_SLOPE 2 +#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000 + +#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168 +#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784 +#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433 +#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655 +#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001 +#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403 +#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898 +#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596 +#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779 +#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496 +#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000 +#define RR_ADC_CHG_THRESHOLD_SCALE 4 + +#define RR_ADC_VOLT_INPUT_FACTOR 8 +#define RR_ADC_CURR_INPUT_FACTOR 2000 +#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886 +#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9 +#define RR_ADC_CURR_USBIN_660_UV_VAL 579500 + +#define RR_ADC_GPIO_FS_RANGE 5000 +#define RR_ADC_COHERENT_CHECK_RETRY 5 +#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16 + +#define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0) // 0x03 +#define RR_ADC_STS_CHANNEL_STS BIT(1) + +#define RR_ADC_TP_REV_VERSION1 21 +#define RR_ADC_TP_REV_VERSION2 29 +#define RR_ADC_TP_REV_VERSION3 32 + +#define RRADC_BATT_ID_DELAY_MAX 8 + +enum rradc_channel_id { + RR_ADC_BATT_ID = 0, + RR_ADC_BATT_THERM, + RR_ADC_SKIN_TEMP, + RR_ADC_USBIN_I, + RR_ADC_USBIN_V, + RR_ADC_DCIN_I, + RR_ADC_DCIN_V, + RR_ADC_DIE_TEMP, + RR_ADC_CHG_TEMP, + RR_ADC_GPIO, + RR_ADC_CHAN_MAX +}; + +struct rradc_chip; + +/** + * struct rradc_channel - rradc channel data + * @label: channel label + * @lsb: Channel least significant byte + * @status: Channel status address + * @size: number of bytes to read + * @trigger_addr: Trigger address, trigger is only used on some channels + * @trigger_mask: Trigger mask + * @scale_fn: Post process callback for channels which can't be exposed + * as offset + scale. + */ +struct rradc_channel { + const char *label; + u8 lsb; + u8 status; + int size; + int trigger_addr; + int trigger_mask; + int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result); +}; + +struct rradc_chip { + struct device *dev; + const struct qcom_spmi_pmic *pmic; + /* Lock held while doing channel conversion + * involving multiple register read/writes + */ + struct mutex conversion_lock; + struct regmap *regmap; + u32 base; + int batt_id_delay; + u16 batt_id_data; +}; + +static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 }; +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX]; +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX]; + +static int rradc_read(struct rradc_chip *chip, u16 addr, u8 *data, int len) +{ + int ret, retry_cnt = 0; + u8 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN]; + + if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) { + dev_err(chip->dev, + "Can't read more than %d bytes, but asked to read %d bytes.\n", + RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len); + return -EINVAL; + } + + while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) { + ret = regmap_bulk_read(chip->regmap, chip->base + addr, data, + len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + ret = regmap_bulk_read(chip->regmap, chip->base + addr, + data_check, len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + if (memcmp(data, data_check, len) != 0) { + retry_cnt++; + dev_dbg(chip->dev, + "coherent read error, retry_cnt:%d\n", + retry_cnt); + continue; + } + + break; + } + + if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY) + dev_err(chip->dev, "Retry exceeded for coherrency check\n"); + + return ret; +} + +static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset, + int64_t *slope) +{ + if (chip->pmic->subtype == PM660_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PM660_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C; + break; + case PM660_FAB_ID_TSMC: + *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C; + break; + default: + *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C; + } + } else if (chip->pmic->subtype == PMI8998_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PMI8998_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C; + break; + case PMI8998_FAB_ID_SMIC: + *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C; + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + + return 0; +} + +/* + * These functions explicitly cast int64_t to int. + * They will never overflow, as the values are small enough. + */ +static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code, + int *result_ohms) +{ + uint32_t current_value; + int64_t r_id; + + current_value = chip->batt_id_data; + r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV); + r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value)); + *result_ohms = (int)(r_id * MILLI); + + return 0; +} + +static int rradc_enable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Clear channel log */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret); + return ret; + } + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, 0); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to not clear failed:%d\n", + ret); + return ret; + } + + /* Switch to continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, + RR_ADC_CTL_CONTINUOUS_SEL); + if (ret < 0) + dev_err(chip->dev, "Update to continuous mode failed:%d\n", + ret); + + return ret; +} + +static int rradc_disable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Switch to non continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, 0); + if (ret < 0) + dev_err(chip->dev, "Update to non-continuous mode failed:%d\n", + ret); + + return ret; +} + +static bool rradc_is_ready(struct rradc_chip *chip, + enum rradc_channel_id chan_address) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + int ret; + unsigned int status, mask; + + /* BATT_ID STS bit does not get set initially */ + switch (chan_address) { + case RR_ADC_BATT_ID: + mask = RR_ADC_STS_CHANNEL_STS; + break; + default: + mask = RR_ADC_STS_CHANNEL_READING_MASK; + break; + } + + ret = regmap_read(chip->regmap, chip->base + chan->status, &status); + if (ret < 0 || !(status & mask)) + return false; + + return true; +} + +static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, + enum rradc_channel_id chan_address) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; + int ret, i; + + if (chan->trigger_mask == 0) { + dev_err(chip->dev, "Channel doesn't have a trigger mask\n"); + return -EINVAL; + } + + ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, chan->trigger_mask); + if (ret < 0) { + dev_err(chip->dev, + "Failed to apply trigger for channel '%s' ret=%d\n", + iio_chan->extend_name, ret); + return ret; + } + + ret = rradc_enable_continuous_mode(chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to switch to continuous mode\n"); + goto disable_trigger; + } + + /* + * The wait/sleep values were found through trial and error, + * this is mostly for the battery ID channel which takes some + * time to settle. + */ + for (i = 0; i < 5; i++) { + if (rradc_is_ready(chip, chan_address)) + break; + usleep_range(50000, 50000 + 500); + } + + if (i == 5) { + dev_err(chip->dev, "Channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -EINVAL; + } + + rradc_disable_continuous_mode(chip); + +disable_trigger: + regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, 0); + + return ret; +} + +static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_address, + u16 *data) +{ + int ret; + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); + if (ret < 0) { + dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret); + return ret; + } + + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL); + if (ret < 0) { + dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret); + goto out_disable_batt_id; + } + + ret = rradc_read_status_in_cont_mode(chip, chan_address); + + /* + * Reset registers back to default values + */ + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, 0); + +out_disable_batt_id: + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0); + + return ret; +} + +static int rradc_do_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_address, u16 *data) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; + int ret; + u8 buf[6]; + + mutex_lock(&chip->conversion_lock); + + switch (chan_address) { + case RR_ADC_BATT_ID: + ret = rradc_prepare_batt_id_conversion(chip, chan_address, data); + if (ret < 0) { + dev_err(chip->dev, "Battery ID conversion failed:%d\n", + ret); + goto unlock_out; + } + break; + + case RR_ADC_USBIN_V: + case RR_ADC_DIE_TEMP: + ret = rradc_read_status_in_cont_mode(chip, chan_address); + if (ret < 0) { + dev_err(chip->dev, + "Error reading in continuous mode:%d\n", ret); + goto unlock_out; + } + break; + default: + if (!rradc_is_ready(chip, chan_address)) { + /* + * Usually this means the channel isn't attached, for example + * the in_voltage_usbin_v_input channel will not be ready if + * no USB cable is attached + */ + dev_dbg(chip->dev, "channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -ENODATA; + goto unlock_out; + } + break; + } + + ret = rradc_read(chip, chan->lsb, buf, chan->size); + if (ret) { + dev_err(chip->dev, "read data failed\n"); + goto unlock_out; + } + + /* + * For the battery ID we read the register for every ID ADC and then + * see which one is actually connected. + */ + if (chan_address == RR_ADC_BATT_ID) { + u16 batt_id_150 = get_unaligned_le16(buf + 4); + u16 batt_id_15 = get_unaligned_le16(buf + 2); + u16 batt_id_5 = get_unaligned_le16(buf); + + if (!batt_id_150 && !batt_id_15 && !batt_id_5) { + dev_err(chip->dev, + "Invalid batt_id values with all zeros\n"); + ret = -EINVAL; + goto unlock_out; + } + + if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_150; + chip->batt_id_data = 150; + } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_15; + chip->batt_id_data = 15; + } else { + *data = batt_id_5; + chip->batt_id_data = 5; + } + } else { + /* + * All of the other channels are either 1 or 2 bytes. + * We can rely on the second byte being 0 for 1-byte channels. + */ + *data = get_unaligned_le16(buf); + } + +unlock_out: + mutex_unlock(&chip->conversion_lock); + + return ret; +} + +static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val, + int *val2) +{ + int64_t fab_offset, fab_slope; + int ret; + + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, "Unable to get fab id coefficients\n"); + return -EINVAL; + } + + switch (chan_address) { + case RR_ADC_SKIN_TEMP: + *val = MILLI; + *val2 = RR_ADC_BATT_THERM_LSB_K; + return IIO_VAL_FRACTIONAL; + case RR_ADC_USBIN_I: + *val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL * + RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_DCIN_I: + *val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_USBIN_V: + case RR_ADC_DCIN_V: + *val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_GPIO: + *val = RR_ADC_GPIO_FS_RANGE; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_CHG_TEMP: + /* + * We divide val2 by MILLI instead of multiplying val + * to avoid an integer overflow. + */ + *val = -RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + fab_slope, + MILLI); + + return IIO_VAL_FRACTIONAL; + case RR_ADC_DIE_TEMP: + *val = RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + + return IIO_VAL_FRACTIONAL; + default: + break; + } + + return -EINVAL; +} + +static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val) +{ + int64_t fab_offset, fab_slope; + int64_t offset1, offset2; + int ret; + + switch (chan_address) { + case RR_ADC_SKIN_TEMP: + /* + * Offset from kelvin to degC, divided by the + * scale factor (250). We lose some precision here. + * 273150 / 250 = 1092.6 + */ + *val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS, + (MILLI / RR_ADC_BATT_THERM_LSB_K)); + return IIO_VAL_INT; + case RR_ADC_CHG_TEMP: + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, + "Unable to get fab id coefficients\n"); + return -EINVAL; + } + offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN * + RR_ADC_CHAN_MSB); + offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL; + offset1 = div64_s64(offset1, + (int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + (int64_t)fab_slope; + offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2; + offset2 = div64_s64( + offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The -1 is to compensate for lost precision. + * It should actually be -0.7906976744186046. + * This works out to every value being off + * by about +0.091 degrees C after applying offset and scale. + */ + *val = (int)(offset1 - offset2 - 1); + return IIO_VAL_INT; + case RR_ADC_DIE_TEMP: + offset1 = -RR_ADC_DIE_TEMP_OFFSET * + (int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN * + (int64_t)RR_ADC_CHAN_MSB; + offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM); + + offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + offset2 = div64_s64(offset2, + ((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The result is -339, it should be -338.69789, this results + * in the calculated die temp being off by + * -0.004 - -0.0175 degrees C + */ + *val = (int)(offset1 - offset2); + return IIO_VAL_INT; + default: + break; + } + return -EINVAL; +} + +static int rradc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan_spec, int *val, + int *val2, long mask) +{ + struct rradc_chip *chip = iio_priv(indio_dev); + const struct rradc_channel *chan; + int ret; + u16 adc_code; + + if (chan_spec->address >= RR_ADC_CHAN_MAX) { + dev_err(chip->dev, "Invalid channel index:%d\n", + chan_spec->address); + return -EINVAL; + } + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return rradc_read_scale(chip, chan_spec->address, val, val2); + case IIO_CHAN_INFO_OFFSET: + return rradc_read_offset(chip, chan_spec->address, val); + case IIO_CHAN_INFO_RAW: + chan = &rradc_chans[chan_spec->address]; + ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); + if (ret < 0) + return ret; + + *val = adc_code; + return IIO_VAL_INT; + case IIO_CHAN_INFO_PROCESSED: + chan = &rradc_chans[chan_spec->address]; + if (!chan->scale_fn) + return -EINVAL; + ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); + if (ret < 0) + return ret; + + *val = chan->scale_fn(chip, adc_code, val); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int rradc_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, char *label) +{ + return snprintf(label, PAGE_SIZE, "%s\n", + rradc_chans[chan->address].label); +} + +static const struct iio_info rradc_info = { + .read_raw = rradc_read_raw, + .read_label = rradc_read_label, +}; + +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = { + { + .label = "batt_id", + .scale_fn = rradc_post_process_batt_id, + .lsb = RR_ADC_BATT_ID_5_LSB, + .status = RR_ADC_BATT_ID_STS, + .size = 6, + .trigger_addr = RR_ADC_BATT_ID_TRIGGER, + .trigger_mask = BIT(0), + }, { + .label = "batt", + .lsb = RR_ADC_BATT_THERM_LSB, + .status = RR_ADC_BATT_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_BATT_THERM_TRIGGER, + }, { + .label = "pmi8998_skin", + .lsb = RR_ADC_SKIN_TEMP_LSB, + .status = RR_ADC_AUX_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_AUX_THERM_TRIGGER, + }, { + .label = "usbin_i", + .lsb = RR_ADC_USB_IN_I_LSB, + .status = RR_ADC_USB_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_I_TRIGGER, + }, { + .label = "usbin_v", + .lsb = RR_ADC_USB_IN_V_LSB, + .status = RR_ADC_USB_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_V_TRIGGER, + .trigger_mask = BIT(7), + }, { + .label = "dcin_i", + .lsb = RR_ADC_DC_IN_I_LSB, + .status = RR_ADC_DC_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_I_TRIGGER, + }, { + .label = "dcin_v", + .lsb = RR_ADC_DC_IN_V_LSB, + .status = RR_ADC_DC_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_V_TRIGGER, + }, { + .label = "pmi8998_die", + .lsb = RR_ADC_PMI_DIE_TEMP_LSB, + .status = RR_ADC_PMI_DIE_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER, + .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE, + }, { + .label = "chg", + .lsb = RR_ADC_CHARGER_TEMP_LSB, + .status = RR_ADC_CHARGER_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER, + }, { + .label = "gpio", + .lsb = RR_ADC_GPIO_LSB, + .status = RR_ADC_GPIO_STS, + .size = 2, + .trigger_addr = RR_ADC_GPIO_TRIGGER, + }, +}; + +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = { + { + .type = IIO_RESISTANCE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .address = RR_ADC_BATT_ID, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .address = RR_ADC_BATT_THERM, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .address = RR_ADC_SKIN_TEMP, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_CURRENT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_USBIN_I, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_USBIN_V, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_CURRENT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_DCIN_I, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_DCIN_V, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .address = RR_ADC_DIE_TEMP, + .channel = 2, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_CHG_TEMP, + .channel = 3, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_GPIO, + .channel = 2, + .indexed = 1, + }, +}; + +static int rradc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct rradc_chip *chip; + int ret, i, batt_id_delay; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*chip)); + if (!indio_dev) + return -ENOMEM; + + chip = iio_priv(indio_dev); + chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->regmap) { + dev_err(dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + chip->dev = dev; + mutex_init(&chip->conversion_lock); + + ret = device_property_read_u32(dev, "reg", &chip->base); + if (ret < 0) { + dev_err(chip->dev, "Couldn't find reg address, ret = %d\n", + ret); + return ret; + } + + batt_id_delay = -1; + ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms", + &batt_id_delay); + if (!ret) { + for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) { + if (batt_id_delay == batt_id_delays[i]) + break; + } + if (i == RRADC_BATT_ID_DELAY_MAX) + batt_id_delay = -1; + } + + if (batt_id_delay >= 0) { + batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay); + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_CFG, + batt_id_delay, batt_id_delay); + if (ret < 0) { + dev_err(chip->dev, + "BATT_ID settling time config failed:%d\n", + ret); + } + } + + /* Get the PMIC revision ID, we need to handle some varying coefficients */ + chip->pmic = qcom_pmic_get(chip->dev); + if (IS_ERR_VALUE(chip->pmic)) { + dev_err(chip->dev, "Unable to get reference to PMIC device\n"); + return PTR_ERR(chip->pmic); + } + + indio_dev->name = DRIVER_NAME; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &rradc_info; + indio_dev->channels = rradc_iio_chans; + indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rradc_match_table[] = { + { .compatible = "qcom,pm660-rradc" }, + { .compatible = "qcom,pmi8998-rradc" }, + {} +}; +MODULE_DEVICE_TABLE(of, rradc_match_table); + +static struct platform_driver rradc_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = rradc_match_table, + }, + .probe = rradc_probe, +}; +module_platform_driver(rradc_driver); + +MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver"); +MODULE_AUTHOR("Caleb Connolly "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Feb 15 17:09:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 403A1C43217 for ; Tue, 15 Feb 2022 17:10:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242242AbiBORK2 (ORCPT ); Tue, 15 Feb 2022 12:10:28 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242261AbiBORK1 (ORCPT ); Tue, 15 Feb 2022 12:10:27 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7420611ADFE for ; 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[81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:11 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 6/9] arm64: dts: qcom: pmi8998: add rradc node Date: Tue, 15 Feb 2022 17:09:48 +0000 Message-Id: <20220215170951.1233375-7-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a DT node for the Round Robin ADC found in the PMI8998 PMIC. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 0fef5f113f05..da10668c361d 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -18,6 +18,14 @@ pmi8998_gpio: gpios@c000 { interrupt-controller; #interrupt-cells = <2>; }; + + pmi8998_rradc: rradc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + + status = "disabled"; + }; }; pmi8998_lsid1: pmic@3 { From patchwork Tue Feb 15 17:09:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D614C35274 for ; Tue, 15 Feb 2022 17:10:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242275AbiBORK3 (ORCPT ); Tue, 15 Feb 2022 12:10:29 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242272AbiBORK2 (ORCPT ); Tue, 15 Feb 2022 12:10:28 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD0AC11B33E for ; Tue, 15 Feb 2022 09:10:14 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id j26so22408122wrb.7 for ; Tue, 15 Feb 2022 09:10:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qImSYxU2i/y/qV71r8EFW+LTWk9ZfhM4KeM2jcTcklQ=; b=s0rSuUU6Vkr6353bMzfVha57JotEXp85WajSwF4FyFCjtniTreNTPck4uMqeP+U5Bc cK5IF4sEr7ey4Tif3CtRu+ufJFbbmN+5PGNXfXhhdMywo7TxYZsuZr4U70LSEEtAFTap aWPJ7HYVe8WP1t+hkwfLtARUt564rrltxFQOPHGwNbOpFqsJJaA1nC2mA7dfAjp4APp7 uKoyBzSeHItBL0X3WRJTYxzy5Uwyx8Zk7zcIHy2WyQyIXiR0ZgOwRjEe2LNte7sPS7Fi scE99X3YjKTAceTW6XrMx20vQ7qTLihPkggsJ9bokjKCEozuehOi8eyMTQ2thhdbG0yb VX+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qImSYxU2i/y/qV71r8EFW+LTWk9ZfhM4KeM2jcTcklQ=; b=XK30Q1T/C0ztpCNfRtR3S175efK86C3qY3J31Aycb09eZbhpFxWNqRaIsZgwzgUbnR KaMLHRVLhkVXCwmCy1bkMckitLbjSlBiQT2V2ABdLVecYl1oeuylogKrgJ9aeNwBDwkn EbBYBzMOEOu9nYDB98i+XRu2Eo0MPnOPgj1uSZPgiZnDcZWjn7Ov6Mvz42+PNwPTAyST 4joQEG70hCqXuVtOIUlRBG1ywhzd0voJSq53Kp7jDrZKdAq6laWCoOmEuER7YcF4TffD qCJRZGl7dPVCt+NGziudif8F8voTjr8uKcoL5D7uWLUXzf4n73sY7SX/tfB/eVqCc6sV jqLg== X-Gm-Message-State: AOAM53352ccirAfHnCbuhjuLY1+PqyDanYlYqu9+XvfCHMicAtjeQaDd aPGCXXajMoGh/7Odp+vDaZfVfg== X-Google-Smtp-Source: ABdhPJzbxWlkLcv4dByszHQRrPpY/zwFZJP9TYlpUX/myYapLODWX3QwYfFYLzGTIWfXXlAJ38uSYw== X-Received: by 2002:a05:6000:18a2:: with SMTP id b2mr4034851wri.645.1644945013380; Tue, 15 Feb 2022 09:10:13 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:12 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 7/9] arm64: dts: qcom: sdm845-oneplus: enable rradc Date: Tue, 15 Feb 2022 17:09:49 +0000 Message-Id: <20220215170951.1233375-8-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the RRADC for the OnePlus 6. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 7f42e5315ecb..e8287cf02511 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -450,6 +450,10 @@ pinconf { }; }; +&pmi8998_rradc { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; From patchwork Tue Feb 15 17:09:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80F46C4167D for ; Tue, 15 Feb 2022 17:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242266AbiBORK3 (ORCPT ); Tue, 15 Feb 2022 12:10:29 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242277AbiBORK2 (ORCPT ); Tue, 15 Feb 2022 12:10:28 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D76611ADD9 for ; Tue, 15 Feb 2022 09:10:15 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id o24so30607649wro.3 for ; Tue, 15 Feb 2022 09:10:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o/d166yo9TtkM4+c7x0I89HNNMPO2K1Na/pBqagV1Y0=; b=QoFM+JEJRo1n40Gs+30ZhFnhZ809XZ1cgbfP+82WqnCj4zoq8y+4OhcRl87QDpBAu4 ZwXQtIBqFDw8mKER1ZR5t0Rfo5mQWALPCOCxUhYKTdwhIQV44EXFGgObYG097WN6R+sq s6IqwSfuEdDkEvwECoXAR//SX7OOW16igt07XU8K/lMrsI2Muf6btKNGYuWNvMfP8/KN TKI/NKo3QE0O5gUzrB1O3s0+Mad42MXyIBKgTarVV+7qrvbWAe6bWo0M0iCFUETfDsuB ELNcpFtTEb/AK/hRfB+h4NyILMYBIRS2mZAI9kLELKka1rcop0prUjXA4AWqHqbDik59 P/og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o/d166yo9TtkM4+c7x0I89HNNMPO2K1Na/pBqagV1Y0=; b=ir9oDZsYrkrPk1XY1Crhomdpi3KJx5fQupTx/w4/ufDLuK5SmjaGTfObS6GJJdtVfc 0UpsniQftPO8MooyQVAMz3gDB0jW2bGG0ZoUhlE5Gndvo4VV+DyyR7XHQK/BqGzmBszt C2KXh2d9p4m67MfytIVOyJAVugXTd5yNQXjn5zqatN+ryJQYlxnLYoJ5DHVDkKMzAmyd ooSaZpLgGOWcT4YGxVac/zHMZUb36B2KM91LW0TFZxAtTgxL4K9ewcFOCLX2jNXfOZmp LX0DGhyh1f0PbiFlBb73kkOb2VjEI9h2QumfckVp7s847alyUozypkHNaYN3Wn1i5GlK qZDw== X-Gm-Message-State: AOAM533aFy/lxatuQ5KrsWdSkCnw2PRMx/NnIBHrteDs25BA8RX7wUTU PoUt9BAavSvrYB1c+/cM8J/ZlQ== X-Google-Smtp-Source: ABdhPJxpimJ06Abn5eYnoOzxEfhvXTIC4eKQeyyYzzqyti1G1VXk2/31zNMjP7CnPaCeY4nZsFTNUg== X-Received: by 2002:adf:ea50:: with SMTP id j16mr4017342wrn.213.1644945014592; Tue, 15 Feb 2022 09:10:14 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:14 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 8/9] arm64: dts: qcom: sdm845-db845c: enable rradc Date: Tue, 15 Feb 2022 17:09:50 +0000 Message-Id: <20220215170951.1233375-9-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the Round Robin ADC for the db845c. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 13f80a0b6faa..1c452b458121 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -595,6 +595,10 @@ resin { }; }; +&pmi8998_rradc { + status = "okay"; +}; + /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@22 { From patchwork Tue Feb 15 17:09:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12747392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BFF1C41535 for ; Tue, 15 Feb 2022 17:10:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242269AbiBORKb (ORCPT ); Tue, 15 Feb 2022 12:10:31 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242267AbiBORK3 (ORCPT ); Tue, 15 Feb 2022 12:10:29 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FEDD11ADDC for ; Tue, 15 Feb 2022 09:10:17 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id k127-20020a1ca185000000b0037bc4be8713so1946123wme.3 for ; Tue, 15 Feb 2022 09:10:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=60je+LDflCDSpm+PbhIAk73PJa9MombVHWRyiPaaQWE=; b=e95A44tpHIjq1YsdKuKzU5OONEu/+yXCT8kuOp2UiKbTHYKRM+skWvxv3kT6tlQHi9 kuAkvUo6I8mngxLzdV8aD0WTym4+cnEDeGOr8rm379aJHXW+OsbXpcZGxlmRRsonaeYQ UP+qOTQ30HOWhwgisLlBU3j0+2ZF0q2MkYC61AfUlHJ8/5+IEc61vkm+X78YHa49P2Bm jB6R+qZ5bMMAv6BV8HDvvXyiBnCig0k9n7N96HGKQ91cLjYNjrD99g8zEWz01bex8eXn HzviMayuNMZ3ZpNneZpsJ0lmKMaQqY8YZjrMOLjVKlCfGHoGm5jXoqQBPSXqylZ+MS6v At3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=60je+LDflCDSpm+PbhIAk73PJa9MombVHWRyiPaaQWE=; b=SR4fRo/y0Pve2cxQn+hvoTGcXF4G3E+EsbDbPEm6WdUlgBfzStev1mp7659U0ErMOH TDn43iPY1DEYhsQ+04Tpo5BvLjXToEhm7AYshoOIhzgtZNJHlE7CGCg2N25f03Yomapq ec6PNu9qS6HkwsG4GOcgr7xwZNiulm6c1u3PGWdPi1xp0U4gws3dsUYeYGF3aGgcDEpL S58uQaKuJUbKL8NPGDRm6ae0e2KuTfIG5U2bwud/OgEq2fprdlRNXsZNzrZq5+uWKpeQ CB0xmXwYSAjNQrhW3SvdKklthH7SNAjLcWDO6woYXFKWMxb89SNtfep8g96bkRWQq+oA eE3g== X-Gm-Message-State: AOAM530dwKrigFBsPAPeEbiQP9QfFnQGKD539YiuzQkH/OzPuOPANbU+ zz1QPHLAfCKAyx4P8MZP5DjegA== X-Google-Smtp-Source: ABdhPJw0YbHf61twQt8zIjpAB6CwQlGiDquDN/ZzgdBbTGfVK01KJvsAZyMdB3byIr6GGeUOd7b30Q== X-Received: by 2002:a05:600c:2e53:: with SMTP id q19mr6132wmf.189.1644945015688; Tue, 15 Feb 2022 09:10:15 -0800 (PST) Received: from localhost.localdomain (cpc78119-cwma10-2-0-cust590.7-3.cable.virginm.net. [81.96.50.79]) by smtp.gmail.com with ESMTPSA id g5sm15558474wmk.38.2022.02.15.09.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 09:10:15 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , Stephen Boyd , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v6 9/9] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable rradc Date: Tue, 15 Feb 2022 17:09:51 +0000 Message-Id: <20220215170951.1233375-10-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220215170951.1233375-1-caleb.connolly@linaro.org> References: <20220215170951.1233375-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the PMI8998 RRADC. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 367389526b41..b3b6aa4e0fa3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -312,6 +312,10 @@ resin { }; }; +&pmi8998_rradc { + status = "okay"; +}; + /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { qi2s@22 {