From patchwork Mon Feb 21 05:22:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12753047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C09ECC433FE for ; Mon, 21 Feb 2022 05:23:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344404AbiBUFXe (ORCPT ); Mon, 21 Feb 2022 00:23:34 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344394AbiBUFXc (ORCPT ); Mon, 21 Feb 2022 00:23:32 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1000EB7; Sun, 20 Feb 2022 21:23:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645420990; x=1676956990; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=fMeakxJfvIFXrpp7I77SKHM3vjQmBLuSF3EbkTZcV6w=; b=hiwREC+U4GJ7DYCrEhsmRp/7ssTY6t0XhTP1V9YAdEpn1G6BJ0McdjAl 8lanb43pDpd1qupQS80j88HSuMFibkMIUGapmCwDQQfDVuG3CspVTwPwy y+CVS4mcXgGHZ+5ZFGd4THd2uz8j3rO35APLx7fvHYWKMYzzqbVQFVWwW s=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 20 Feb 2022 21:23:09 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Feb 2022 21:23:06 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 21 Feb 2022 10:52:52 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 225E646C3; Mon, 21 Feb 2022 10:52:51 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v3 1/7] dt-bindings: mailbox: Add binding for SDX65 APCS Date: Mon, 21 Feb 2022 10:52:27 +0530 Message-Id: <1645420953-21176-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree YAML binding for SDX65 APCS GCC block. The APCS block acts as the mailbox controller and also provides a clock output and takes 3 clock sources (pll, aux, ref) as input. Signed-off-by: Rohit Agarwal --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 01e9d91..688ae8b 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -91,6 +91,7 @@ allOf: compatible: enum: - qcom,sdx55-apcs-gcc + - qcom,sdx65-apcs-gcc then: properties: clocks: From patchwork Mon Feb 21 05:22:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12753051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EACDC3527A for ; Mon, 21 Feb 2022 05:23:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344429AbiBUFXh (ORCPT ); Mon, 21 Feb 2022 00:23:37 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344419AbiBUFXg (ORCPT ); Mon, 21 Feb 2022 00:23:36 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA1BD109C; Sun, 20 Feb 2022 21:23:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645420994; x=1676956994; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=PX/WHKWbkuwa/EAALLC2/n7hI8uaF1SS9QQ5iBOgSbM=; b=FIEVwUIaBQlH/gcA2nNoDS6SX5x0Eu4kpwt4ET+SDughv1THb+rfuAK1 v853DsjgxNE0vxXNLpePaxh8SaGYJgYrnKhR5bc9mCUdzLa+Xx2yYNQdd 3axU0/wJrHo2BMER+heqPzzEv62bYjgWZMV11XLSYds1+0ZYgMU52HKl1 s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 20 Feb 2022 21:23:13 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Feb 2022 21:23:11 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 21 Feb 2022 10:52:53 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 1A6CE46C2; Mon, 21 Feb 2022 10:52:52 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v3 2/7] mailbox: qcom: Add support for SDX65 APCS IPC Date: Mon, 21 Feb 2022 10:52:28 +0530 Message-Id: <1645420953-21176-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In SDX65, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Rohit Agarwal --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9325d2a..54d7659 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" }; +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); From patchwork Mon Feb 21 05:22:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12753044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A20F1C4332F for ; Mon, 21 Feb 2022 05:23:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344327AbiBUFX2 (ORCPT ); Mon, 21 Feb 2022 00:23:28 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:48742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233837AbiBUFX1 (ORCPT ); Mon, 21 Feb 2022 00:23:27 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8C42E2D; Sun, 20 Feb 2022 21:23:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645420986; x=1676956986; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=k/SrkmNO3uWYgzq06IwevJ6gIjLamufvr/U1/0YEWR4=; b=ICfIgMqTSzIQNTCZmYutEFecmAHb1QYZP3RZlp9EfMSAZZU0Eq+UE7a/ CpcQ3jFOPPoo2V7kGLaB/hmSH/TkkyRACaPaiuttErwvxJt8EjuNUVPIs f5Ojn6L5zpaOVTxbfW/ORGv/pE3KFehLiYTwpu3hJKxPAPqvG/Y0iMu9g c=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 20 Feb 2022 21:23:05 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Feb 2022 21:23:02 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 21 Feb 2022 10:52:53 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 1DAB546C3; Mon, 21 Feb 2022 10:52:53 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v3 3/7] dt-bindings: clock: Add A7 PLL binding for SDX65 Date: Mon, 21 Feb 2022 10:52:29 +0530 Message-Id: <1645420953-21176-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add YAML binding for Cortex A7 PLL clock in Qualcomm platforms like SDX65. Signed-off-by: Rohit Agarwal --- Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml index 8666e99..b8889dc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml @@ -10,13 +10,14 @@ maintainers: - Manivannan Sadhasivam description: - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high frequency clock to the CPU. properties: compatible: enum: - qcom,sdx55-a7pll + - qcom,sdx65-a7pll reg: maxItems: 1 From patchwork Mon Feb 21 05:22:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12753050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87CDFC3525A for ; Mon, 21 Feb 2022 05:23:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344425AbiBUFXh (ORCPT ); Mon, 21 Feb 2022 00:23:37 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344414AbiBUFXf (ORCPT ); Mon, 21 Feb 2022 00:23:35 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A17ECEB7; Sun, 20 Feb 2022 21:23:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645420993; x=1676956993; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=TGPshyGLQVn+XUcTmwqZz7StC7gbCPyK/DutjTq1Skw=; b=YK8li8a3qR7IllQzEaIteBgO+0g2lHUFZhJxo5V8I2obXO4wknlsAg0e 0naLa2293gdTJrc0d7fYiWzAQjSTbGSx2EGwlJt0KqPTQqRwKwdjABkwT JFCybB5d9NuJiqZjYfF37urFKFuVwlXYJZgmvwgMLGfx4jX/5qyJvc7p/ s=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 20 Feb 2022 21:23:11 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Feb 2022 21:23:08 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 21 Feb 2022 10:52:54 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id D94DD46C2; Mon, 21 Feb 2022 10:52:53 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v3 4/7] clk: qcom: Add A7 PLL support for SDX65 Date: Mon, 21 Feb 2022 10:52:30 +0530 Message-Id: <1645420953-21176-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for PLL found in Qualcomm SDX65 platforms which is used to provide clock to the Cortex A7 CPU via a mux. This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by: Rohit Agarwal --- drivers/clk/qcom/Kconfig | 6 +++--- drivers/clk/qcom/a7-pll.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 42c8741..5159a1d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -29,11 +29,11 @@ config QCOM_A53PLL devices. config QCOM_A7PLL - tristate "SDX55 A7 PLL" + tristate "A7 PLL driver for SDX55 and SDX65" help - Support for the A7 PLL on SDX55 devices. It provides the CPU with + Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with frequencies above 1GHz. - Say Y if you want to support higher CPU frequencies on SDX55 + Say Y if you want to support higher CPU frequencies on SDX55 and SDX65 devices. config QCOM_CLK_APCS_MSM8916 diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c index c4a53e5..adb2121 100644 --- a/drivers/clk/qcom/a7-pll.c +++ b/drivers/clk/qcom/a7-pll.c @@ -84,6 +84,7 @@ static int qcom_a7pll_probe(struct platform_device *pdev) static const struct of_device_id qcom_a7pll_match_table[] = { { .compatible = "qcom,sdx55-a7pll" }, + { .compatible = "qcom,sdx65-a7pll" }, { } }; MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table); From patchwork Mon Feb 21 05:22:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12753046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EDA1C43217 for ; Mon, 21 Feb 2022 05:23:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344387AbiBUFXb (ORCPT ); Mon, 21 Feb 2022 00:23:31 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344377AbiBUFXb (ORCPT ); Mon, 21 Feb 2022 00:23:31 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6057BEA5; Sun, 20 Feb 2022 21:23:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645420989; x=1676956989; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=qTdBqK/wk3XPj6YIH+4a3yNFkD3UU5gHt0you21im4M=; b=n3EmGSx3MQmcU0+5Ti3Ymkkr+WU2Wy02eEWeiof0ezCFWs6OQ9k6eSzW DTv5B3ToBeAFhFW/A3DQ/y2a4THxpYH94qSXhvtE7s/5PaudKlQS6SpY0 XxzYCXC2O9ZAhGAPldGiSHOOYVK7KanvV73/jFEnYCni/90WHRbow7UlJ w=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 20 Feb 2022 21:23:09 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Feb 2022 21:23:07 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 21 Feb 2022 10:52:55 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id B1FF746C2; Mon, 21 Feb 2022 10:52:54 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v3 5/7] ARM: dts: qcom: sdx65: Add support for A7 PLL clock Date: Mon, 21 Feb 2022 10:52:31 +0530 Message-Id: <1645420953-21176-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SDX65 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 653df15..0219445 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -125,6 +125,14 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx65-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; From patchwork Mon Feb 21 05:22:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12753048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECBC9C4321E for ; Mon, 21 Feb 2022 05:23:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344409AbiBUFXe (ORCPT ); Mon, 21 Feb 2022 00:23:34 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344401AbiBUFXe (ORCPT ); Mon, 21 Feb 2022 00:23:34 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A49FF7B; Sun, 20 Feb 2022 21:23:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645420992; x=1676956992; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=/upK0A0rflnjDZY7Ohlb4ns1NlD1J1g8hyys+JiFpCk=; b=Ut5uVQnqdR008kZeeb44eIuM49yvNSapMdUcaDODBOij+Lyvc2eJOMtZ dh5CWIMxQQrZovzgQr7U3S/1DYS4qb8ZrZtcmRvNVYahTIdgynxO4ueTj uRxt0RBNxE5IjF2t1fUMqSA/aDSxruDf4XmNyNCkhdXbaRI2JClKf7xGT w=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 20 Feb 2022 21:23:11 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Feb 2022 21:23:08 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 21 Feb 2022 10:52:56 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 593E546C3; Mon, 21 Feb 2022 10:52:55 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v3 6/7] ARM: dts: qcom: sdx65: Add support for APCS block Date: Mon, 21 Feb 2022 10:52:32 +0530 Message-Id: <1645420953-21176-7-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The APCS block on SDX65 acts as a mailbox controller and also provides clock output for the Cortex A7 CPU. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 0219445..b02d598 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -133,6 +133,15 @@ #clock-cells = <0>; }; + apcs: mailbox@17810000 { + compatible = "qcom,sdx65-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; From patchwork Mon Feb 21 05:22:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12753049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D7DFC433EF for ; Mon, 21 Feb 2022 05:23:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344418AbiBUFXf (ORCPT ); Mon, 21 Feb 2022 00:23:35 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344396AbiBUFXd (ORCPT ); Mon, 21 Feb 2022 00:23:33 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77EEEF32; Sun, 20 Feb 2022 21:23:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645420992; x=1676956992; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=uNp4RSZh2KVJ+kj1Q/Nraz3VZq+QnhRWTwAGyobmdwE=; b=KDBo8ROVyAycSL9pvLgA0NBZiUxLd9j17l0zKmk2jBwtj7kXTXX4nUvF /voptS0QPgFoSSl5Cj9Xy9d8hoSCFVF8Enm/8KpL9M3fEsu53WgSkJhtf OdeK7QMpsT5wGV2VShFyP37EWg0utHuZoSjfPnAj93bIh49XfuLEh5kre s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 20 Feb 2022 21:23:11 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Feb 2022 21:23:09 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 21 Feb 2022 10:52:57 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 333FB46C2; Mon, 21 Feb 2022 10:52:56 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v3 7/7] clk: qcom: Add SDX65 APCS clock controller support Date: Mon, 21 Feb 2022 10:52:33 +0530 Message-Id: <1645420953-21176-8-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update APCS Kconfig to reflect support for SDX65 APCS clock controller. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam --- drivers/clk/qcom/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 5159a1d..a2fa9af 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996 drivers for dynamic power management. config QCOM_CLK_APCS_SDX55 - tristate "SDX55 APCS Clock Controller" + tristate "SDX55 and SDX65 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST help - Support for the APCS Clock Controller on SDX55 platform. The + Support for the APCS Clock Controller on SDX55, SDX65 platform. The APCS is managing the mux and divider which feeds the CPUs. Say Y if you want to support CPU frequency scaling on devices - such as SDX55. + such as SDX55, SDX65. config QCOM_CLK_RPM tristate "RPM based Clock Controller"