From patchwork Mon Feb 21 14:55:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 12753750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0411C433EF for ; Mon, 21 Feb 2022 14:55:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378500AbiBUO4P (ORCPT ); Mon, 21 Feb 2022 09:56:15 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:47254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378499AbiBUO4P (ORCPT ); Mon, 21 Feb 2022 09:56:15 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E15217AAD; Mon, 21 Feb 2022 06:55:51 -0800 (PST) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 92E875C0211; Mon, 21 Feb 2022 09:55:50 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Mon, 21 Feb 2022 09:55:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; bh=CGhvsw+LhTgD6aZuUFtqqU1Kc3kIvE iqCXe0yRe6810=; b=e4gBrijTOZhpcNy+jnhFPC0M3cR5xv/xVK+BSjrnefBwqq SFusBz1p7/d22M8zErvkzVUZuhZL/Kn4aVsObOPAckG9arsvxG9OH9fxJkDGJ/mh Aae4VRiKLfJgF7GgqDbFtk6CiHUCUnLx3wwquqWWUgl77vxYj1b8TncUXHXPLXEe twShpKTlddijxWNBNPlRiBo3sU76wKQIrUh3WombyMvL1YnrmtQ7bgAldd5dH/Mt GuIjzBIDrHX9GFjvGXwnt9VIU7vn9aBBh1rXvXUxs5dLEmTeHqwN76fiDiq7KQ+c fALbazbPEhzJ229TsG19hQ14L9ekm2CX/ThSwwCg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=CGhvsw +LhTgD6aZuUFtqqU1Kc3kIvEiqCXe0yRe6810=; b=C1toCK7qAAJFyiRrFibt9+ 57z9FhqcL4Xvbg/sQ7+RAz/Ed895TTNAh3ZAEhu0bylS4xyNpTB0hf+1VLi4XNzk Wn2cq2QB1sNAY+VbegcQ2F3VfusZ7f9O00Dbtng61dNk/9xAu9X9KIU1twshDgWT u61YULPepO6EGCl9jHJkt+T1w35l14Gys4Jvel4sQRa1mBXK1ssQaB4tDDmrv+MQ w1Uhb5qygqANjNTX0N635wNgK/8lIwRpZRqNX6vLcBIJsCDPvwGXORwQ48jnnEnF Q6Wk8gMmzTItyY5+BYEwrc6jYM9LOOHUaB10RDe2kRPz6i6n9RZSVaDDp2LeD4pA == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrkeeigdeikecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecuvehluhhsthgvrhfuihiivgep tdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgoh grthdrtghomh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 21 Feb 2022 09:55:49 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, chenhuacai@kernel.org, tsbogend@alpha.franken.de, macro@orcam.me.uk, Jiaxun Yang Subject: [RFC PATCH 1/3] MIPS: Loongson64: Clearify IO barriers Date: Mon, 21 Feb 2022 14:55:29 +0000 Message-Id: <20220221145531.10479-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220221145531.10479-1-jiaxun.yang@flygoat.com> References: <20220221145531.10479-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Remove CPU_HAS_WB from Kconfig as all Loongson64 processors don't have R3000 style write buffer. This is likely to be a legacy of Loongson 2E's Bonito64. Remove Loongson64 from war_io_reorder_wmb. Loongson64 never reorders uncached memory access as per user manual of GS464, LS3A2000 and LS3A3000. It was intruduced due to a misunderstanding of Store Fill Buffer. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 1 - arch/mips/include/asm/io.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 058446f01487..6d2e97342723 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -487,7 +487,6 @@ config MACH_LOONGSON64 select BOARD_SCACHE select CSRC_R4K select CEVT_R4K - select CPU_HAS_WB select FORCE_PCI select ISA select I8259 diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 6f5c86d2bab4..065e1ab6401a 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -219,7 +219,7 @@ void iounmap(const volatile void __iomem *addr); #define ioremap_wc(offset, size) \ ioremap_prot((offset), (size), boot_cpu_data.writecombine) -#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) +#if defined(CONFIG_CPU_CAVIUM_OCTEON) #define war_io_reorder_wmb() wmb() #else #define war_io_reorder_wmb() barrier() From patchwork Mon Feb 21 14:55:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 12753752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 989BFC433FE for ; Mon, 21 Feb 2022 14:55:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378566AbiBUO4R (ORCPT ); Mon, 21 Feb 2022 09:56:17 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:47262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378549AbiBUO4P (ORCPT ); Mon, 21 Feb 2022 09:56:15 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A743320F4A; Mon, 21 Feb 2022 06:55:52 -0800 (PST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id E83C15C0070; Mon, 21 Feb 2022 09:55:51 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 21 Feb 2022 09:55:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; bh=gzFf99qWVEJAvowt98L5HAVVoHw9Oh Hz4nNsoMnI/oU=; b=aOdz//ubr9AE2TpwwVLpL9yKeKAHz7ro1nWiU5HU5bQBdM V6mvqJDLhQXePYukX6XF8K1/2MMBpUSdnFfjKE2UMtrVEyDq8TDD7p9/7CVX6N9p Q2OuI6UWDnwb9cZ7g4WSQhP9C+E2mGc6EK5ZUUQWP8VsuNCEiJQei67NerXZ1UgC pIfRJNIVtesJAxrWJqUGv+tsbCak3vnHdih4pXmYRvBYNCPqkwhWBkYYOZtu5fA4 pp1HmYsL1DfYvJLJGNPLWZ+Me35gfrzrc1hnzizVwh8aNjkH9Y80B6YL3BWiKkPV uCtqJua/YRie/6w8iLNZ5+NLZfGMx/qduSBE3ccA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=gzFf99 qWVEJAvowt98L5HAVVoHw9OhHz4nNsoMnI/oU=; b=aTIKPYkZtIvnNPgBVcJkam pwzAzDTJEn0pJauR3q1cjZWYNxn+kxyfHrxjt713Px3uHpDDZdfk6Qq3jwQvG4mu oNw/GJxB6OyxrtTLRH/1AK+cSt+MFUC6fiR4nMl7tDsq7FcG+agHdvYpdloAS8rZ 6+6BAnJuErFmxtFUpl+zfQWMEHtGaJF4slUuG2zmAoVW38wgYqcLfF8XzxGl1fWM tQGZQvewN9DtFJOpj77NvaQCm9J3BRe0OFwndbv7HJeUJRiZy5IzLgzu7veUvBHS tkEm2PyOMKldV3BoilDsFvPWR570koCxA7XcSigiSnidVWiP0Iv7KqlCoMz2zKmg == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrkeeigdeikecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecuvehluhhsthgvrhfuihiivgep tdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgoh grthdrtghomh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 21 Feb 2022 09:55:50 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, chenhuacai@kernel.org, tsbogend@alpha.franken.de, macro@orcam.me.uk, Jiaxun Yang Subject: [RFC PATCH 2/3] MIPS: io.h use barrier terminology from asm-generic Date: Mon, 21 Feb 2022 14:55:30 +0000 Message-Id: <20220221145531.10479-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220221145531.10479-1-jiaxun.yang@flygoat.com> References: <20220221145531.10479-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org So we can share understanding of those barriers with other archs and hopefully one day we will be able to switch asm-generic. As mmiowb_set_pending is unimplemented on MIPS, __io_aw currently does nothing, but it need to be implemented later. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/io.h | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 065e1ab6401a..8a148277d9e6 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -225,6 +225,17 @@ void iounmap(const volatile void __iomem *addr); #define war_io_reorder_wmb() barrier() #endif +#define __io_br() mb() + +/* prevent prefetching of coherent DMA data ahead of a dma-complete */ +#define __io_ar(v) rmb() + +/* flush writes to coherent DMA data before possibly triggering a DMA read */ +#define __io_bw() wmb() + +/* serialize device access against a spin_unlock, usually handled there. */ +#define __io_aw() do { } while (0) + #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \ \ static inline void pfx##write##bwlq(type val, \ @@ -234,7 +245,7 @@ static inline void pfx##write##bwlq(type val, \ type __val; \ \ if (barrier) \ - iobarrier_rw(); \ + __io_bw(); \ else \ war_io_reorder_wmb(); \ \ @@ -265,6 +276,7 @@ static inline void pfx##write##bwlq(type val, \ local_irq_restore(__flags); \ } else \ BUG(); \ + __io_aw(); \ } \ \ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ @@ -275,7 +287,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ if (barrier) \ - iobarrier_rw(); \ + __io_br(); \ \ if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ __val = *__mem; \ @@ -300,9 +312,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ BUG(); \ } \ \ - /* prevent prefetching of coherent DMA data prematurely */ \ if (!relax) \ - rmb(); \ + io_ar(__val); \ return pfx##ioswab##bwlq(__mem, __val); \ } From patchwork Mon Feb 21 14:55:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 12753753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D95BC433F5 for ; Mon, 21 Feb 2022 14:55:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378569AbiBUO4S (ORCPT ); Mon, 21 Feb 2022 09:56:18 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:47274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378564AbiBUO4R (ORCPT ); Mon, 21 Feb 2022 09:56:17 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25A8517AAD; Mon, 21 Feb 2022 06:55:54 -0800 (PST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 6CA415C01D2; Mon, 21 Feb 2022 09:55:53 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Mon, 21 Feb 2022 09:55:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; bh=W33SNp0pR4K0oD6ddMKKEdiqs40zlf kBnS8Whij6EHQ=; b=STDBM/4rJQczYtG1aRaRKTVE1Y71ArnL/zaUAKliicNNPz Uaat6kUFekckbBN+po74oIfigvIBiqH2rNBNkg7qq2i4ogbUaII0Q56hrVYp5Soa Cx8e3fAIpGzlo8UKmYgoX3qVdgxHkaYguLS76d2mnInD9Vv/hwVrbFR+1IXFjWdz HZ7lGP5xBbThgXMXMQc4dZvX32D/UZcpeO3YPmN4hWSBjrPFwtnY1GxxDVdPSFEF C6MDVWeAhcK41jZ2NG6OohmaR39lqfB60cilicD+4GI1zlvFaMu2Ef73SNW4jqip jYJ9jamzw3B/crI3+W2beF3ndbJ6Qd2RizXQazCg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=W33SNp 0pR4K0oD6ddMKKEdiqs40zlfkBnS8Whij6EHQ=; b=Nh573dM6Tpq4drfLuT0j7Y 1f1Pp1wR2vDj829htrMOSI0m3RB4WZF8ptKiKpDKY+Gt+vSkLDNOfsaAEdeSMjQI KGUuDoaBcqzUdP/N1rlajXlg+jrOGB+h86+NY8SpdhvNqMeJBhiw+iCbj/YKEv7b e9qzjAKCB+XKSZT2pppjFs+uvoLjKJSUWoZN4CbCTNuOLcnR/F0gA/O7DwpKR2MP FhlVRclO7iZoKfZFnn2Vun2J2Qa85X6zPnDwTpXutoRMIkKWxQP/v7OpBmWHwhBu NewrrPaQZ7wTnmFZu3QjFMpb6PSa3Ef9psCs5y+k8dadGxLzbfVTQihdtnmksuzA == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrkeeigdeilecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecuvehluhhsthgvrhfuihiivgep tdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgoh grthdrtghomh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 21 Feb 2022 09:55:52 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, chenhuacai@kernel.org, tsbogend@alpha.franken.de, macro@orcam.me.uk, Jiaxun Yang Subject: [RFC PATCH 3/3] MIPS: io.h: Remove barriers before MMIO accessors for CPU without WB Date: Mon, 21 Feb 2022 14:55:31 +0000 Message-Id: <20220221145531.10479-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220221145531.10479-1-jiaxun.yang@flygoat.com> References: <20220221145531.10479-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Commit 3d474da ("MIPS: Enforce strong ordering for MMIO accessors") intruduced this barrier to ensure the correctness of IO access ordering with following reasons: 1. DECstation systems with hardware write barrier can reorder IO writes. 2. Cavium and Loongson have errata which reorders MMIO. 3. MIPS Spec didn't enforce ordering of MMIO access. For reason 1, the concern is still valid, so the barrier is kept when CONFIG_CPU_HAS_WB. For reason 2, we had confirmed that Loongson doesn't have such errata, Cavium's issue is workarounded by war_io_reorder_wmb. For reason 3, I had got confirmation from CIP United that all cores by MTI (MIPS Techonologies) won't do this. Given that other platform had live without these barriers for a long peroid, removing this barrier is unlikely to bring any problem. SYNC based barrier is very heavy on Loongson and MTI cores as it will issue a SYNC command on their bus and invalidate all present instrutions in pipeline. We should generally avoid that. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/io.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 8a148277d9e6..faa38049412f 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -225,7 +225,11 @@ void iounmap(const volatile void __iomem *addr); #define war_io_reorder_wmb() barrier() #endif +#if defined(CONFIG_CPU_HAS_WB) #define __io_br() mb() +#else +#define __io_br() barrier() +#endif /* prevent prefetching of coherent DMA data ahead of a dma-complete */ #define __io_ar(v) rmb()