From patchwork Mon Feb 21 16:04:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 12753845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F6A8C433F5 for ; Mon, 21 Feb 2022 16:06:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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bh=qVfsUtEKp+x8O41F2tW67FgG0Ziy8k7baERGbcFiYng=; b=N4Ss68+meapreRsfr2OpwPHTx72F8kys+0jFnWVa2WMV4ROwZZE3cNtO qivyCmNLdjkE6gtJ537ukIIqowk4XRhvrzCHQPRv5pF0LyRLDJmTSA6oK S6gV4LEmFeQISaVAAbtAxJUJBUOnBWOWNaIToWprYr1oDY9d9HZYmlD0I 2ATxACFOlmwUoL5s7XlBaSxTSCNkDbRM1J8Cbd7iTPY1Cr/GxSecrUBLZ Ef41reXv3s4wBvhzssjL+TXnGi+kk4kkal3pTO0pTBYSlKZ+BimqE+NqB XPMkiH9xpk987OrXdaN8CbBtADGMm0zx9xlwHFKY/EoXo3gcl2H02SM/X w==; X-IronPort-AV: E=Sophos;i="5.88,386,1635199200"; d="scan'208";a="22216138" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 21 Feb 2022 17:04:37 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id DE696280075; Mon, 21 Feb 2022 17:04:36 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Matthias Schiffer , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rob Herring , Alexander Stein Subject: [PATCH v2 1/5] dt-bindings: arm: fsl: add TQ Systems boards based on i.MX6UL(L) Date: Mon, 21 Feb 2022 17:04:15 +0100 Message-Id: <20220221160419.550640-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> References: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220221_080440_181572_56DD9961 X-CRM114-Status: GOOD ( 12.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Matthias Schiffer TQMa6ULx is a SOM family using NXP i.MX6UL CPU family. TQMa6ULLx is a SOM family using NXP i.MX6ULL CPU family. Both are available as a socket type as well as an LGA type. For both variants there are the mainboards MBa6ULx and MBa6ULxL, trailing 'L' is LGA version. Finally there is the possibility to use the socket module with an LGA adapter on the MBa6ULxL. The SOM needs a mainboard, therefore we provide compatibles using this naming schema: "tq,imx6ul-" for the module and "tq,imx6ul--" for when mounted on the mainboard. The i.MX6ULL version is done similar. Signed-off-by: Matthias Schiffer Acked-by: Rob Herring Signed-off-by: Alexander Stein Reviewed-by: Krzysztof Kozlowski --- Changes in v2: * Acked-by: Rob Herring .../devicetree/bindings/arm/fsl.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 23e678232451..9343b64ce55e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -613,6 +613,28 @@ properties: - const: kontron,imx6ul-n6310-som - const: fsl,imx6ul + - description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul1-mba6ulx + - const: tq,imx6ul-tqma6ul1 # MCIMX6G1 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul2-mba6ulx + - const: tq,imx6ul-tqma6ul2 # MCIMX6G2 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter + - tq,imx6ul-tqma6ul2l-mba6ulxl + - const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant + - const: fsl,imx6ul + - description: i.MX6ULL based Boards items: - enum: @@ -667,6 +689,21 @@ properties: - const: kontron,imx6ull-n6411-som - const: fsl,imx6ull + - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board + items: + - enum: + - tq,imx6ull-tqma6ull2-mba6ulx + - const: tq,imx6ull-tqma6ull2 # MCIMX6Y2 + - const: fsl,imx6ull + + - description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter + - tq,imx6ull-tqma6ull2l-mba6ulxl + - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant + - const: fsl,imx6ull + - description: i.MX6ULZ based Boards items: - enum: From patchwork Mon Feb 21 16:04:16 2022 Content-Type: text/plain; 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+ reg = <0x80000000 0x10000000>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + reg_sw1a: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-ramp-delay = <6250>; + /* not used */ + }; + + reg_sw1b_core: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + reg_sw2: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sw3_ddr: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_swbst: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + /* not used */ + }; + + reg_snvs_3v0: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vccsd: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + + reg_v33_3v3: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vldo1_3v3: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo2: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vldo3: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo4: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + jc42_1a: eeprom-temperature-sensor@1a { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + m24c02_52: eeprom@52 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + read-only; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + /* + * PMIC & temperature sensor IRQ + * Both do currently not use IRQ + * potentially dangerous if used on baseboard + */ + pmic-int-hog { + gpio-hog; + gpios = <24 0>; + input; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <33000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz" , "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + + bus-width = <8>; + disable-wp; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_recovery: i2c4recoverygrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0 + >; + }; + + pinctrl_pmic: pmic { + fsl,pins = < + /* PMIC irq */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts new file mode 100644 index 000000000000..f2a5f17f312e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul1.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) + * and need to be disabled here again + */ +&can2 { + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&fec2 { + /delete-property/ phy-handle; + /delete-node/ mdio; +}; + +&iomuxc { + pinctrl_enet1_mdc: enet1mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi new file mode 100644 index 000000000000..24192d012ef7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul-tqma6ul2.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM"; + compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * There are no module specific differences compared to TQMa6UL2, + * only external interfaces differ + */ + +/* + * Devices not available on i.MX6ULG1 and should not be enabled on + * mainboard level (again) + */ +&can2 { + status = "disabled"; +}; + +&csi { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts new file mode 100644 index 000000000000..0757df2b8f48 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi new file mode 100644 index 000000000000..e2e95dd92263 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2 SoM"; + compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi new file mode 100644 index 000000000000..5afb9046c202 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULLx + */ + +&m24c64_50 { + vcc-supply = <®_sw2>; +}; + +&m24c02_52 { + vcc-supply = <®_sw2>; +}; + +®_sw2 { + regulator-boot-on; + regulator-always-on; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_sw2>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi new file mode 100644 index 000000000000..941f8725032c --- /dev/null +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + model = "TQ-Systems MBA6ULx Baseboard"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + rtc0 = &rtc0; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <®_mba6ul_3v3>; + enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + beeper: beeper { + compatible = "gpio-beeper"; + gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buttons>; + + button { + label = "s14"; + linux,code = ; + gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; + }; + + button { + label = "s6"; + linux,code = ; + gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; + }; + + button { + label = "s7"; + linux,code = ; + gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; + }; + + button { + label = "POWER"; + linux,code = ; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + led1 { + label = "led1"; + gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "lcd-pwr"; + gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_mba6ul_3v3: regulator-mba6ul-3v3 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_mba6ul_5v0: regulator-mba6ul-5v0 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_mpcie: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mpcie-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <500000>; + vin-supply = <®_mba6ul_3v3>; + }; + + reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { + compatible = "regulator-fixed"; + gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "otg2-vbus-supply-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_mpcie>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <768000000>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + reg = <0>; + max-speed = <100>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + reg = <1>; + max-speed = <100>; + }; + }; +}; + +&i2c4 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + ldoin-supply = <®_mba6ul_3v3>; + iov-supply = <®_mba6ul_3v3>; + }; + + jc42: temperature-sensor@19 { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander_out0: gpio-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + expander_in0: gpio-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander_in0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + enet1_int-hog { + gpio-hog; + gpios = <6 0>; + input; + }; + + enet2_int-hog { + gpio-hog; + gpios = <7 0>; + input; + }; + }; + + expander_out1: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + analog_touch: touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio4>; + interrupt-controller; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,ave-ctrl = <3>; /* 8 sample average control */ + st,fraction-z = <7>; /* 7 length fractional part in z */ + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + st,settling = <3>; /* 1 ms panel driver settling time */ + st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24000000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart6dte>; */ + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* otg-port */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + power-active-high; + over-current-active-low; + /* we implement only dual role but not a fully featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* 7-port usb hub */ +/* id, pwr, oc pins not connected */ +&usbotg2 { + disable-over-current; + vbus-supply = <®_otg2vbus_5v0>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_mba6ul_3v3>; + vqmmc-supply = <®_vccsd>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_buttons: buttonsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 + MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + >; + }; + + pinctrl_enet2_mdc: enet2mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_expander_in0: expanderin0grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6dte: uart6dte { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 + MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 + >; + }; +}; From patchwork Mon Feb 21 16:04:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 12753847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC0F0C433F5 for ; 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21 Feb 2022 17:04:37 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 726B5280075; Mon, 21 Feb 2022 17:04:37 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/5] ARM: dts: imx6ul: add TQ-Systems MBa6ULxL device trees Date: Mon, 21 Feb 2022 17:04:17 +0100 Message-Id: <20220221160419.550640-4-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> References: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220221_080442_329375_19D65E8A X-CRM114-Status: GOOD ( 17.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device trees for the MBa6ULx mainboard with TQMa6ULxL SoMs. Signed-off-by: Alexander Stein --- Changes in v2: * None arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi | 71 +++++++++++++++++++ .../arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi | 48 +++++++++++++ 4 files changed, 135 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce4673e270a2..4112b618a539 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -688,6 +688,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-tqma6ul1-mba6ulx.dtb \ imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 000000000000..9d9b6b744a1c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi new file mode 100644 index 000000000000..caf2c5d03f7e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2L SoM"; + compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi new file mode 100644 index 000000000000..ba84a4f70ebd --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULxL + * - TQMa6ULLxL + */ + +/ { + reg_vin: reg-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&m24c64_50 { + vcc-supply = <®_vin>; +}; + +&m24c02_52 { + vcc-supply = <®_vin>; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_vin>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; From patchwork Mon Feb 21 16:04:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 12753846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E6EFC433EF for ; Mon, 21 Feb 2022 16:06:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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bh=Gp05FQuMMtqmQ8ZU85DxD5yJk7dMIe1Er0E8gBFpu/c=; b=GrYGx7G1Yc+vTYIxgzEIJp1f+y5oU+5umkSfsKlG4k3o6j3gtv++J8i/ XdVT7isaXmfqKJQZE1NDf3daByG6GphAhtX17Lp913O9cwlNJrk93+0ec Lw5oWAl/YxqWUtYpDg8SeV0seRqJuRklT90aFwIkupmo4NI4i4gLeTRgv Aj0bLsFRtStaGQyAoxo9jSdXXpcNcfSdkNhs3V79XQrdJh66eaK4jQGSG T/OJk5HI6c6tussANQbcj7N5dPKmBs2+5rJmE/O70T42BJHRTrX6mgMsj wPsyqEUY6o1FiYhpycD9VB/AAt6ffFRwGmpqw9wNlv64SEPTi3CQZqc0J Q==; X-IronPort-AV: E=Sophos;i="5.88,386,1635199200"; d="scan'208";a="22216145" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 21 Feb 2022 17:04:37 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id AA7E4280065; Mon, 21 Feb 2022 17:04:37 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/5] ARM: dts: imx6ull: add TQ-Systems MBa6ULLx device trees Date: Mon, 21 Feb 2022 17:04:18 +0100 Message-Id: <20220221160419.550640-5-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> References: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220221_080443_100129_80B6FDB2 X-CRM114-Status: GOOD ( 16.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device trees for the MBa6ULx mainboard with TQMa6ULLx SoMs. Signed-off-by: Alexander Stein --- Changes in v2: * None arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4112b618a539..3a6eccb6371a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -709,6 +709,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 000000000000..e593b7036fc7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi new file mode 100644 index 000000000000..326e6da91ed4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM"; + compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; From patchwork Mon Feb 21 16:04:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 12753849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFD44C433EF for ; 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21 Feb 2022 17:04:38 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id E52F0280075; Mon, 21 Feb 2022 17:04:37 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/5] ARM: dts: imx6ull: add TQ-Systems MBa6ULLxL device trees Date: Mon, 21 Feb 2022 17:04:19 +0100 Message-Id: <20220221160419.550640-6-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> References: <20220221160419.550640-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220221_080447_415104_18C4C3FE X-CRM114-Status: GOOD ( 16.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device trees for the MBa6ULx mainboard with TQMa6ULLxL SoMs. Signed-off-by: Alexander Stein --- Changes in v2: * None arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3a6eccb6371a..9bf89273ae71 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -710,6 +710,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 000000000000..33437aae9822 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi new file mode 100644 index 000000000000..8e4d5cd18614 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM"; + compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +};