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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:23 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Anup Patel , Heiko Stuebner , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 1/6] RISC-V: Correctly print supported extensions Date: Tue, 22 Feb 2022 12:48:06 -0800 Message-Id: <20220222204811.2281949-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_124825_867280_68AE0128 X-CRM114-Status: GOOD ( 13.39 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Tsukasa OI This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel Tested-by: Heiko Stuebner Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); From patchwork Tue Feb 22 20:48:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 12755961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 849E8C43219 for ; Tue, 22 Feb 2022 20:48:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qnk5/VOFWF4Mz4wHWovse1JNnuzarUggXOK9EITAsc8=; b=soIoKdR6DmLAx4 XsPp3ErCe0m+f1DEKhK9xS2qdOV+7c2wdf2uHQqtTPNA5siesgKNq6FtJiYZXO9vUTWdyFY9De5AD BlgMKHMIgKDQE4z8c15dbQC+4SP8FsRbGO+mvYGp/K/mQ0l21pXXx+HgeKiXHpJxf2TPO9z9Edkxe VUl0JY2v0zWsl1Dn2VtktZU0AvGI4KbKI5zQmgb2Ix03YI1sLribSG6yCdhPmBUD0jjxuC3VeV8mb QVF89+8HB6+dXUltTDLVqjGUjphE6k3TV/RapsGE7zWKSmA5hys6wkSeXPKl7DzI5kDtUbK0Ir+aC i97zQTGP27Ke7IXkFZPw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMc5H-00BZao-PX; Tue, 22 Feb 2022 20:48:31 +0000 Received: from mail-oo1-xc2b.google.com ([2607:f8b0:4864:20::c2b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMc5D-00BZYW-Cj for linux-riscv@lists.infradead.org; Tue, 22 Feb 2022 20:48:28 +0000 Received: by mail-oo1-xc2b.google.com with SMTP id x6-20020a4a4106000000b003193022319cso19395020ooa.4 for ; Tue, 22 Feb 2022 12:48:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4FsTSrbVAURtuc7icXoc7CnjlReAr0UpIVXQMIlDTc4=; b=6a+eX7j3LCyMn7OaC5yvtENFql8mK7SDDMa4RtV1aQ93fAn5DduP6Fgc7zUxkNDPTK 2f5BEhyv8QBUUnYojgoP9I+MJqoziATEH1PvK8x/8t7oxNPO0/tcxhlAJGfxpsv2ELxp nfu2dWei93dbF37AOXHaYScoVk4bCNOoDm8lnsSjeyt2iYjkkidiwnvv/dGi5PNu1x2R 68xEWUesACbG6mjSkozJilU0wLtHje/Ch7BosK/ew81mgyEbv8fsSfyEZnHa/tvVCuWn NihWa3DT/You12J90LfMjxx/hnQY9P/qyn3SO5SeuXy/X83tM5KGyBCAF4sPu+G1sY0j nLbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4FsTSrbVAURtuc7icXoc7CnjlReAr0UpIVXQMIlDTc4=; b=rOx/wl3bVRbFIaAjCyL1PdwD37NZ+4zLK0l/NaYbO082d3b9riTkwNZhiPqVPfY3nI wv6otVE3GdGo+lMv093t1mejf/cRWaVhfkljH/fKDAcYk3kgR/21Dw302cBnMY+CXPEU GAXfEj7joMU8qMYbg7jZu+fcczfUSDQl2ICFq7/ABNX+5uBwuzrCgW2DyQeIkXLVWoHa eMh5MMRdFgxn1E26lGF2Kvf415+pW5KkReR+pTLm65uE0eFBxxIrLnb0c2vzrpzy0bm8 iA5msvSDGdQj3NDneM0jIZTdbiVOp20eMYJemTrk4wCa55oi8y9rxxnBXdcUt3Gch8Nc 1NsQ== X-Gm-Message-State: AOAM5320ZxAQmce1bZVYdwimzfuj00LQpEOaULF8xdparbVtvv2cv33e Y2KxrpJjyjppDmbKN/Ltkd4lNg== X-Google-Smtp-Source: ABdhPJwVNKQnkJZdZ0jgSou92auChtzBu1r7KPJtir+JSZM/M01cC0DkREbbPZe7LjE4CO/652m/yQ== X-Received: by 2002:a05:6870:d88e:b0:d1:359a:29f with SMTP id dv14-20020a056870d88e00b000d1359a029fmr2644172oab.232.1645562906164; Tue, 22 Feb 2022 12:48:26 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:25 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 2/6] RISC-V: Minimal parser for "riscv, isa" strings Date: Tue, 22 Feb 2022 12:48:07 -0800 Message-Id: <20220222204811.2281949-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_124827_459348_B0D1874C X-CRM114-Status: GOOD ( 18.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Tsukasa OI Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: Atish Patra [Fixed workaround for QEMU] Signed-off-by: Tsukasa OI Tested-by: Heiko Stuebner Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 72 ++++++++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dd3d57eb4eea..72c5f6ef56b5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; + int i, j; static unsigned long isa2hwcap[256] = {0}; isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; @@ -92,23 +93,72 @@ void __init riscv_fill_hwcap(void) continue; } - i = 0; - isa_len = strlen(isa); #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) - i += 4; + isa += 4; #elif IS_ENABLED(CONFIG_64BIT) if (!strncmp(isa, "rv64", 4)) - i += 4; + isa += 4; #endif - for (; i < isa_len; ++i) { - this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; + for (; *isa; ++isa) { + const char *ext = isa++; + const char *ext_end = isa; + bool ext_long = false, ext_err = false; + + switch (*ext) { + case 's': + /** + * Workaround for invalid single-letter 's' & 'u'(QEMU). + * No need to set the bit in riscv_isa as 's' & 'u' are + * not valid ISA extensions. It works until multi-letter + * extension starting with "Su" appears. + */ + if (ext[-1] != '_' && ext[1] == 'u') { + ++isa; + ext_err = true; + break; + } + fallthrough; + case 'x': + case 'z': + ext_long = true; + /* Multi-letter extension must be delimited */ + for (; *isa && *isa != '_'; ++isa) + if (!islower(*isa) && !isdigit(*isa)) + ext_err = true; + break; + default: + if (unlikely(!islower(*ext))) { + ext_err = true; + break; + } + /* Find next extension */ + if (!isdigit(*isa)) + break; + /* Skip the minor version */ + while (isdigit(*++isa)) + ; + if (*isa != 'p') + break; + if (!isdigit(*++isa)) { + --isa; + break; + } + /* Skip the major version */ + while (isdigit(*++isa)) + ; + break; + } + if (*isa != '_') + --isa; /* - * TODO: X, Y and Z extension parsing for Host ISA - * bitmap will be added in-future. + * TODO: Full version-aware handling including + * multi-letter extensions will be added in-future. */ - if ('a' <= isa[i] && isa[i] < 'x') - this_isa |= (1UL << (isa[i] - 'a')); + if (ext_err || ext_long) + continue; + this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; + this_isa |= (1UL << (*ext - 'a')); } /* From patchwork Tue Feb 22 20:48:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 12755959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5ADB4C433F5 for ; Tue, 22 Feb 2022 20:48:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KOKdZFGr1j2EkrTXjBruVmD+ww7aTBgibrdcSHv/ypw=; b=lbxWcKlXMpRhNi v2dnAPmglIj//mzGbi9I0xYqa2KWFfp74g5pu/cN/UvXGs6LVgVeM7X+tWmHueevNudYFTvMgeSVU oMUblZ1pyMiDN7NXFU3Og82hFHbINxXz2m6NDuRl5iOXAKseLCAdEzSmmdt4HuY52ybrm85rDUnom fbcvbfLazl1Jn5AP7wJ7sQTmbKIN1Pw2dP94wmmgBjJskvghUcTrzK3ZcFk7aQzErKlbLVd//Ix0Z N5Xojo3UByDgc5yzImjcf1zUTrXSF97/ZLGRitHDmc4Rv75moSxA0TnYaH3s8ZJK+Sf3ZH/Mmzn/w cY4fgMflULhgtoYtdvMQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMc5K-00BZcC-2x; Tue, 22 Feb 2022 20:48:34 +0000 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMc5F-00BZZ5-49 for linux-riscv@lists.infradead.org; Tue, 22 Feb 2022 20:48:30 +0000 Received: by mail-oi1-x22b.google.com with SMTP id i5so15977822oih.1 for ; Tue, 22 Feb 2022 12:48:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c80lDSr4/XrHo4HXuUiUdwW2N5759X0Jr8s3r01G4uw=; b=qi2CLkoTpNf+/7KRpxJWRKKedV3ySUp6Hi5CiH/Rl69V/1ZYKrlbplu5LuSaHdhRIr U3qvvNSC3b8wbwX2/jLQsKii0fmBsrukVOjWCg8MHzVUm8SSVTFJXjwemeX/p3d7bn6Q +m87Kf9FB60c/CB+MHLc7aTiHvLqierIr4BTAMkPS7FbbukSEVFc7B/wbjSfrQvOn2Jk E8yxCnUIUCRB+eJ5tkE7gfAvVChYIkBzF1uoQFj7V7qm3IKD0Nr14+iqzwFSYX/sG6p8 N4+OOxN8twd0yzhKVeF35CuuEGVtvYulguhNHU0z+MdnBFRUedC9fBtzQri9+gdN6jNK 01IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c80lDSr4/XrHo4HXuUiUdwW2N5759X0Jr8s3r01G4uw=; b=CZLmvPKbmCeuXGL8NnOEqwXXw8TZiPFldi3SvEWYz9GuhYylkGczkhFnczkG0hsnT6 wcwioKgS5Oh/bSEzAaq/Xk4a3ozVkPoLaRhGfps9USmgLTUsuc55SsgMdgh4FOSfgu/c P/hC11zlkqCldx2qA9fg7Gm3ymX8nf8Xzgj6VTRvCQa9b3oLWVoJ7VMz2c15v8vOozug GLpLvF3PxTuHbyFcAkGNV9gytgf2xZItrvqJFkvtz9wFoFTmWhd27AICQpgcy3i6f7zX ByEB6Fadp0ovBOvm873TIDbEJxgNqX4VIlCJ3PqJFTIcj7rDXos8lkVYk0pIE54mY1MR BmmQ== X-Gm-Message-State: AOAM533ATeL41jWjSyd53SQEylcbrsrNPBkR3M8SxIYzPIXUwHlqhqew fjUlI7nTwg0lKYju5KWGb1jfsw== X-Google-Smtp-Source: ABdhPJz2U8KLjdjNRUB//gea/ufjet3hLSc2A6nlzGRCQGTmGSKt0aTPN50GrrZNsqro3BBTDjNyuQ== X-Received: by 2002:a05:6808:2106:b0:2d5:3244:ca43 with SMTP id r6-20020a056808210600b002d53244ca43mr2968470oiw.263.1645562907949; Tue, 22 Feb 2022 12:48:27 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:27 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Heiko Stuebner , Anup Patel , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Date: Tue, 22 Feb 2022 12:48:08 -0800 Message-Id: <20220222204811.2281949-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_124829_213247_23698E8E X-CRM114-Status: GOOD ( 11.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Tsukasa OI Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Tested-by: Heiko Stuebner Reviewed-by: Anup Patel Signed-off-by: Tsukasa OI [Improved commit text and comments] Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 35 ++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 72c5f6ef56b5..b0df7eff47f7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -124,8 +124,28 @@ void __init riscv_fill_hwcap(void) ext_long = true; /* Multi-letter extension must be delimited */ for (; *isa && *isa != '_'; ++isa) - if (!islower(*isa) && !isdigit(*isa)) + if (unlikely(!islower(*isa) + && !isdigit(*isa))) ext_err = true; + /* Parse backwards */ + ext_end = isa; + if (unlikely(ext_err)) + break; + if (!isdigit(ext_end[-1])) + break; + /* Skip the minor version */ + while (isdigit(*--ext_end)) + ; + if (ext_end[0] != 'p' + || !isdigit(ext_end[-1])) { + /* Advance it to offset the pre-decrement */ + ++ext_end; + break; + } + /* Skip the major version */ + while (isdigit(*--ext_end)) + ; + ++ext_end; break; default: if (unlikely(!islower(*ext))) { @@ -151,14 +171,13 @@ void __init riscv_fill_hwcap(void) } if (*isa != '_') --isa; - /* - * TODO: Full version-aware handling including - * multi-letter extensions will be added in-future. - */ - if (ext_err || ext_long) + + if (unlikely(ext_err)) continue; - this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; - this_isa |= (1UL << (*ext - 'a')); + if (!ext_long) { + this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; + this_isa |= (1UL << (*ext - 'a')); + } } /* From patchwork Tue Feb 22 20:48:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 12755962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E38BC43217 for ; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:29 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 4/6] RISC-V: Implement multi-letter ISA extension probing framework Date: Tue, 22 Feb 2022 12:48:09 -0800 Message-Id: <20220222204811.2281949-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_124831_007383_8587D90C X-CRM114-Status: GOOD ( 15.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 24 ++++++++++++++++++------ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..170bd80da520 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +/* + * Increse this to higher value as kernel support more ISA extensions. + */ #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + +/* The base ID for multi-letter ISA extensions */ +#define RISCV_ISA_EXT_BASE 26 + +/* + * This enum represent the logical ID for each multi-letter RISC-V ISA extension. + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter + * extensions while all the multi-letter extensions should define the next + * available logical extension id. + */ +enum riscv_isa_ext_id { + RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, +}; unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b0df7eff47f7..c6693873e95c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; - unsigned long this_isa = 0; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); if (riscv_of_processor_hartid(node) < 0) continue; @@ -100,6 +100,7 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa += 4; #endif + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext = isa++; const char *ext_end = isa; @@ -172,12 +173,22 @@ void __init riscv_fill_hwcap(void) if (*isa != '_') --isa; +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext == sizeof(name) - 1) && \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + set_bit(bit, this_isa); \ + pr_info("Found ISA extension %s", name);\ + } \ + } while (false) \ + if (unlikely(ext_err)) continue; if (!ext_long) { this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; - this_isa |= (1UL << (*ext - 'a')); + set_bit(*ext - 'a', this_isa); } +#undef SET_ISA_EXT_MAP } /* @@ -190,10 +201,11 @@ void __init riscv_fill_hwcap(void) else elf_hwcap = this_hwcap; - if (riscv_isa[0]) - riscv_isa[0] &= this_isa; + if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else - riscv_isa[0] = this_isa; + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } /* We don't support systems with F but without D, so mask those out @@ -207,7 +219,7 @@ void __init riscv_fill_hwcap(void) for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] = (char)('a' + i); - pr_info("riscv: ISA extensions %s\n", print_str); + pr_info("riscv: base ISA extensions %s\n", print_str); memset(print_str, 0, sizeof(print_str)); for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) From patchwork Tue Feb 22 20:48:10 2022 Content-Type: text/plain; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Tue, 22 Feb 2022 12:48:10 -0800 Message-Id: <20220222204811.2281949-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_124833_075289_C0B8750F X-CRM114-Status: GOOD ( 10.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c6693873e95c..f3a4b0619aa0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + const char *temp; if (riscv_of_processor_hartid(node) < 0) continue; @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) continue; } + temp = isa; #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) isa += 4; @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa += 4; #endif + /* The riscv,isa DT property must start with rv64 or rv32 */ + if (temp == isa) + continue; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext = isa++; From patchwork Tue Feb 22 20:48:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 12755964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82C07C433EF for ; Tue, 22 Feb 2022 20:48:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pFnlHo+WDbmWlj2CkHcIQ+hluVpxFXEgHF7p2DQEa9o=; b=Ra32qfjSofAFY9 FV+07H1gcw/CyGzJcpcr+++WooLD86jnmzRg8N8Tsc8VGvCAnnPyXWxBCm83eOI4kX1etS2dbMCyc 4TGMSKQXg1MR+TNGn/zh+tuCsurgg5iP+QP4cMJ6hqSzhb7Q8gPNSl5Q32qgMGdoSCAujCkAEGpX0 NBkKP31iS/nX1NXIc3EY9iEB9Q1U3afPiv8je+q54ExjWGXPUOcz3Fe+FV9PXbCG8Y9K4M2CwfuCb 8OAvmBbegqIT+OpQEMnAR07EewXTw2YTzu4NC3Mo75e2lcKPwGWVWhWV96JobccxpoAglLBps+AzX VaV9UiPcBsJQtT6pn1WA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMc5S-00BZiD-RT; Tue, 22 Feb 2022 20:48:42 +0000 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMc5L-00BZc8-Ft for linux-riscv@lists.infradead.org; Tue, 22 Feb 2022 20:48:37 +0000 Received: by mail-oi1-x22e.google.com with SMTP id j24so13769794oii.11 for ; Tue, 22 Feb 2022 12:48:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8URXe1loYhEkYqA2mgPstYxk0kAqAk7osNiGz1KzfP4=; b=tkekYg+ui1gZE9tvXRPYNaXdnHSqvcZXJR3E2Vm5fQodbde1h2KEXdYVPBeSbBJrKE tZITXpUaJDk67Z/a7izDd9M3gsdIhhNTMcdTj6S8CxQsNWqSdzP/jKbyNPXB2oJu3avO 3Zk4Jzm23rDMqdxFIbyWksIRJgMYHe95vMZ4pU0NzJ4BWBMvSQ1mHfq53uAu7WYa6PEM +utp42+TYOdOY+tnl0KO6BUIuJx91baW39b4LLo7XR8xTBndLIkdHIwQHVU5hXpmXZsc ZJOLoy8uvivgGGcYyqXtIuEtIJ/Cze3eAL876RuQ9h20mvCPEdnfU11wF41bvhGTyTig senQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8URXe1loYhEkYqA2mgPstYxk0kAqAk7osNiGz1KzfP4=; b=6eO1yv2gZ4FUOgxLmgEO3YF0TD5wN9eDYc/efM75SfuG202JBU9XtZ6gHfKzB1c3Mb 4Yn6czaQxs8TuEmk3Zf5m89RQjeUKENO8VmQBqWH9a0PG5WgFfKK7kN/HAQJ3C+S8qp2 KEH1YuFY/zDLDBbmr9SrTAcmvqSlpkTfzBiCVthrYcQtIJWG5CUmqjbkBpmBgUb4eBoL GZ0HpnyG/uCvv0eZqQ5IpuTptwmubXvH1aul7hY+AIU0GgrPuWadtcs4MmUd9sj5t9M7 7nqlpxPQ8jQFt8J0efYSSAcHF7mNKteVmY7QdzYKx8QO817lkNEagPmyhlMWDKtJhW/D T8dg== X-Gm-Message-State: AOAM530rBlAvbqo3s2Zd/Y8d4WRfeDZScfhsjUMxIBZyW16oy1aaMMKW tC2cqS/uXNFBJKTb8zh/H3ms1g== X-Google-Smtp-Source: ABdhPJwB9rW8JuhYMN3o1Zy+a756u4qrYvSc4u5fAhxI6ME+4kF0AoSQeiNHi0jhT+ZAJKpoKp4vFQ== X-Received: by 2002:aca:5b85:0:b0:2d3:fe13:177f with SMTP id p127-20020aca5b85000000b002d3fe13177fmr2847716oib.59.1645562913488; Tue, 22 Feb 2022 12:48:33 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:33 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Tue, 22 Feb 2022 12:48:11 -0800 Message-Id: <20220222204811.2281949-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_124835_593222_13875F8F X-CRM114-Status: GOOD ( 19.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Same goes for the single letter extensions as well which prints the entire ISA string. Some of they may not be valid ISA extensions as well (e.g 'su') Parse only the valid & enabled ISA extension and print them. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/hwcap.h | 7 +++++ arch/riscv/kernel/cpu.c | 51 ++++++++++++++++++++++++++++++++-- 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..031ad15a059f 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -63,12 +64,57 @@ int riscv_of_parent_hartid(struct device_node *node) } #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop = #UPROP, \ + .isa_ext_id = EXTID, \ + } + +static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i = 0, arr_sz; + + arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <= 0) + return; + + seq_puts(f, "isa-ext\t\t: "); + for (i = 0; i <= arr_sz; i++) { + edata = &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "%s ", edata->uprop); + } + seq_puts(f, "\n"); +} + +/** + * These are the only valid base (single letter) ISA extensions as per the spec. + * It also specifies the canonical order in which it appears in the spec. + * Some of the extension may just be a place holder for now (B, K, P, J). + * This should be updated once corresponding extensions are ratified. + */ +static const char base_riscv_exts[13] = "imafdqcbkjpvh"; static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + int i; + seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + /* Print the rv[64/32] part */ + seq_write(f, isa, 4); + for (i = 0; i < sizeof(base_riscv_exts); i++) { + if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) + /* Print only enabled the base ISA extensions */ + seq_write(f, &base_riscv_exts[i], 1); + } seq_puts(f, "\n"); } @@ -115,6 +161,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) print_isa(m, isa); + print_isa_ext(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv"))