From patchwork Tue Feb 22 22:06:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12755987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6B5EC433F5 for ; Tue, 22 Feb 2022 22:14:18 +0000 (UTC) Received: from localhost ([::1]:50484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMdQH-0004Hg-AK for qemu-devel@archiver.kernel.org; Tue, 22 Feb 2022 17:14:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48856) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMdJY-0005lD-GL for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:20 -0500 Received: from [2607:f8b0:4864:20::c33] (port=42680 helo=mail-oo1-xc33.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMdJU-0005LZ-JR for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:19 -0500 Received: by mail-oo1-xc33.google.com with SMTP id s203-20020a4a3bd4000000b003191c2dcbe8so19648061oos.9 for ; Tue, 22 Feb 2022 14:07:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3g5GZ+uk3CMbwQHosVUdX40FGxQGNQFTnUC30jSO2R8=; b=qTEQtAbukFJZMj15HrOKM9ejlBYxkJjKDZ2W0ycz2OvsK3/i1M0AwzMuSM5jcWjo3M 1b/mtfND4hAuBBGS67Ba+SCzGZ7nZGaemz++GNu2DzEITRQuojYcsGFhYfj8aDyRfUvm 3KiPR9CqnsIuTBIh5lZSrcuKKRUsR/m5OYEDYjlWMlfkVIfggjYlK14r7va1C/TjgEdv 2ngZZtdmaqtkttp6VvOBnv5N9VNbieus7tX1Y2p2Pk5J6BAa59HCbePbntbbsC5Mhwno yp4ri17/XLPIJVHv5IY0NkTP9MNGyDnKLJS6Tm6dBreToH2NVKHkOKbgBRpyAnCXazOq 6C6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3g5GZ+uk3CMbwQHosVUdX40FGxQGNQFTnUC30jSO2R8=; b=3xchmVNCfHbvh7gmiSZHmvQTY0LGBbdVsogeF0QorUme6Z+1AvvFg+X9NacIjw2c2p 2chEguVNrfqs5KTzYMj5t7difjqscjflL35dPE1fMedRttOwcqHhsnKZv9h8F6aI2LXB +LxrQPr0N9fqU/cZlKinBM8bZ+Ut6bspsOL2jc2FrKMG7kBZNvnqxTHtHjhhbKIE9skS HO/f0WIYVvuMhcqUZ2iK76NT//xj1oiZFVOibdpSaWMmW/I/N4ohdVRmHzzMRXosuZsP t6K3B8sCSCEMGt8PN7vMUq+jghxRmPb8qAdjf7JSq+59UZvpatJhlj62Z00IgamHKWWb bGlg== X-Gm-Message-State: AOAM533qeTWt/EH42kaH0JIu7RMqb7bW1Acxqm+RwDOTohGrvMRTM1U2 44scZAh5xoG58KEWH2sAid6U0FNNg0y5Hw== X-Google-Smtp-Source: ABdhPJzzGlnsxVoUQHG+JSpuTHen+GjPm2PF4uYBy/8cauAULkQ+kQkabUdWFAs+NfYIjknUUotx3g== X-Received: by 2002:a05:6870:5d88:b0:d3:112c:3e2e with SMTP id fu8-20020a0568705d8800b000d3112c3e2emr2710763oab.230.1645567629482; Tue, 22 Feb 2022 14:07:09 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id n25sm4901913otq.78.2022.02.22.14.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 14:07:09 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 1/6] target/riscv: Define simpler privileged spec version numbering Date: Tue, 22 Feb 2022 14:06:59 -0800 Message-Id: <20220222220704.2294924-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222220704.2294924-1-atishp@rivosinc.com> References: <20220222220704.2294924-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c33 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc33.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Atish Patra , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9d24d678e98a..e5ff4c134c86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,8 +82,11 @@ enum { RISCV_FEATURE_AIA }; -#define PRIV_VERSION_1_10_0 0x00011000 -#define PRIV_VERSION_1_11_0 0x00011100 +/* Privileged specification version */ +enum { + PRIV_VERSION_1_10_0 = 0, + PRIV_VERSION_1_11_0, +}; #define VEXT_VERSION_1_00_0 0x00010000 From patchwork Tue Feb 22 22:07:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12755988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 839EAC433EF for ; Tue, 22 Feb 2022 22:14:19 +0000 (UTC) Received: from localhost ([::1]:50556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMdQI-0004KV-Gd for qemu-devel@archiver.kernel.org; Tue, 22 Feb 2022 17:14:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMdJa-0005lj-2K for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:22 -0500 Received: from [2607:f8b0:4864:20::c34] (port=40725 helo=mail-oo1-xc34.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMdJV-0005Lk-2f for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:21 -0500 Received: by mail-oo1-xc34.google.com with SMTP id u47-20020a4a9732000000b00316d0257de0so19641916ooi.7 for ; Tue, 22 Feb 2022 14:07:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0fDRU9fUV36kn4c3Xnw7jDoaNqJ76Gr20/A1kgalcYo=; b=dsa03m3hZRLah1dzxEvl17QOvRfgGEydYfVu3pZjcMShMYygQOVtPNFU1+6FxLKRHA ILFQqGzWbbaBx8dwOj/I558xAhWzszLg46B3e/6EWOBEe2NAnyPhW8KqdaugFHtdLbt6 fD/+6cHcgazUdQLWkxw7Gr75lO2CHDLFoY7UyGzk02QRE9MwupQbQWQ3eJlWadqeJ+GU 7a0GCLmHbcJ3WvGdu//kfPo8VvTyQaixdyyOCAbHK1bDVPGrmavsUIPeD1PspXhgLx22 I0/fZbudiOCrnxYDjbFo2EXfzsZtaj+TwtyzH3aUwovfAgP6SKfcYnEppAhYD4dZW2jZ lc3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0fDRU9fUV36kn4c3Xnw7jDoaNqJ76Gr20/A1kgalcYo=; b=M8gfV5tZStNun72RSP/Wq6seWC5uABUleI1rwaOITZEWViEwTTjPeEZc9MklJ5L3FV BkunshB2YvmGyzx4DahydSyNzUNXoagYNd8bvqDZ2hwhpvfsoGN4v5eqtKTuBr+zRdmw MAA6XBi+HnI2s/lkY1c+rnFPrFYv/tNKfHngfRksXQfyQu1yvRaHVAn37A8j5NarUtxN Rdu00DKrIlSXqRqeIK5TCBT9z+Q75A4EnqDnplM638Gr5yojJZV5OLVTtCe0ikb8zWaF sBLD5JuYHZ9qZXEe9Wl9rODIc7E4zvaK8DZEQC71WMKBqHusqFWV1y9Xxv1Fl9YzB+9D A39g== X-Gm-Message-State: AOAM530gu9H+QRrZalOmjaxAM1liQSvzS1D9CwGddVi1DS2CyMqJauLW Abe9kxSV0K6P+RpmekrnEbSO1/ACdH6V+Q== X-Google-Smtp-Source: ABdhPJwbR/XWxaGT4SN+/Nj4k0PFHF1hJUrmVuV8OBwj49r1BkU/F406ib1zgoUoGNiHekLIBU5Hdw== X-Received: by 2002:a05:6870:da0b:b0:d2:c66b:2e27 with SMTP id go11-20020a056870da0b00b000d2c66b2e27mr2757157oab.142.1645567630974; Tue, 22 Feb 2022 14:07:10 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id n25sm4901913otq.78.2022.02.22.14.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 14:07:10 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 2/6] target/riscv: Add the privileged spec version 1.12.0 Date: Tue, 22 Feb 2022 14:07:00 -0800 Message-Id: <20220222220704.2294924-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222220704.2294924-1-atishp@rivosinc.com> References: <20220222220704.2294924-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c34 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc34.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add the definition for ratified privileged specification version v1.12 Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,6 +86,7 @@ enum { enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, + PRIV_VERSION_1_12_0, }; #define VEXT_VERSION_1_00_0 0x00010000 From patchwork Tue Feb 22 22:07:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12755989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC267C433EF for ; Tue, 22 Feb 2022 22:15:16 +0000 (UTC) Received: from localhost ([::1]:51632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMdRD-00053R-Lx for qemu-devel@archiver.kernel.org; Tue, 22 Feb 2022 17:15:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMdJb-0005mZ-IW for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:23 -0500 Received: from [2607:f8b0:4864:20::c29] (port=35530 helo=mail-oo1-xc29.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMdJV-0005MN-1d for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:23 -0500 Received: by mail-oo1-xc29.google.com with SMTP id 189-20020a4a03c6000000b003179d7b30d8so19673865ooi.2 for ; Tue, 22 Feb 2022 14:07:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yWWSpdqkm9nlAxbyVkqk0sscIr0OJfJELM7qVATYEXQ=; b=8CZ91cLploGpp2tGwBZjLo5nZjNYdmoFYn3SvkBF7YW7j96I2CsT2Oz+SgiOmUiEBU ZAzZ/52dhvXZpQt0PlHi5W+0RqXPFimfmVHU/ysPM2j1vWh1r8VBy35oU/3SFO4hjKKx hTv+3WFJI0Drj0XIFyPpTKlL1E8deX+7LutgxYYqIwFv7u0odgPjcce7cNqt6JWPAxy8 Neis4AUUvw46at5ZwhmFGR3Sjdc4fUpj6i36WXZ1934nmq1MhHi6nRonTtRxb+dX1YSU Zy8JM0emU8jquf+UOxCbzqnzlj6eXtV/dWntV5YTmU8i2ddd2uGBA0V6Uh5pg/3l5Rtu viFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yWWSpdqkm9nlAxbyVkqk0sscIr0OJfJELM7qVATYEXQ=; b=arjDM3TkckDzk0JcMvjku9rKSi1RoPIFsylChE44wU3vZ/QgHReKIP5T1Obj3S6U+5 6cLuAgaOH5S+UIc+Wa2idgNyqM+ihRDOa9/91wBhFqfenznTp9FmrmeBEgNog0cwDiFJ UjIOSvaYohg36hu9gUQHLF4Ap8ksVp8Zy7woE7m2+EWpY1OslfP//7a8MlTDI/JxvYh1 XXckfiZ88Uq8sxtW9cUP7QTWBu1btc6lN1luuzgUJI81hmIfBtvW3BPQQkCVo+iVbPgU b/TAUcNbZRBymNRXhEfEq+jSBSi9dDJMAPYvzv7VWnbh56i1+WpScuvoDny0B921m4S+ z0lQ== X-Gm-Message-State: AOAM531QmrhJwNCx/CePRQtIyReLY44GJKSKvzgtT9oqHJcbLM8hydts rMNAGtFDMvXkfaxI+Luj+CYhunn+xsaJ3A== X-Google-Smtp-Source: ABdhPJwxxUGD82Pd/vgNRzTRdU+uj+QZE2FGjA82VKbtEm4ZABq4M+jVqZETxVnSzOgeEJ/hFg3ZxQ== X-Received: by 2002:a05:6870:5309:b0:ce:c0c9:630 with SMTP id j9-20020a056870530900b000cec0c90630mr2681345oan.130.1645567632317; Tue, 22 Feb 2022 14:07:12 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id n25sm4901913otq.78.2022.02.22.14.07.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 14:07:11 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 3/6] target/riscv: Introduce privilege version field in the CSR ops. Date: Tue, 22 Feb 2022 14:07:01 -0800 Message-Id: <20220222220704.2294924-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222220704.2294924-1-atishp@rivosinc.com> References: <20220222220704.2294924-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c29 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. However, it doesn't enforce the privilege version in this commit. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60b847141db2..0741f9822cf0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -593,6 +593,8 @@ typedef struct { riscv_csr_op_fn op; riscv_csr_read128_fn read128; riscv_csr_write128_fn write128; + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ + uint32_t min_priv_ver; } riscv_csr_operations; /* CSR function table constants */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8c63caa39245..25a0df498669 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_FRM] = { "frm", fs, read_frm, write_frm }, [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, - [CSR_VL] = { "vl", vs, read_vl }, - [CSR_VTYPE] = { "vtype", vs, read_vtype }, - [CSR_VLENB] = { "vlenb", vs, read_vlenb }, + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VL] = { "vl", vs, read_vl, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VTYPE] = { "vtype", vs, read_vtype, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VLENB] = { "vlenb", vs, read_vlenb, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_instret }, [CSR_INSTRET] = { "instret", ctr, read_instret }, @@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, - [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg }, - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie }, - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, - [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL }, - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, - - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie }, - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, - - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, @@ -3154,7 +3186,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, /* Physical Memory Protection */ - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, + [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, From patchwork Tue Feb 22 22:07:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12755982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B491C433FE for ; Tue, 22 Feb 2022 22:10:59 +0000 (UTC) Received: from localhost ([::1]:43856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMdN3-0008BM-VF for qemu-devel@archiver.kernel.org; Tue, 22 Feb 2022 17:10:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMdJZ-0005lh-Nt for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:22 -0500 Received: from [2607:f8b0:4864:20::c30] (port=43865 helo=mail-oo1-xc30.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMdJV-0005MT-1F for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:21 -0500 Received: by mail-oo1-xc30.google.com with SMTP id w10-20020a4ae08a000000b0031bdf7a6d76so19593334oos.10 for ; Tue, 22 Feb 2022 14:07:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kkZGA5zMICgSFHManAvIfubSG1Ccpwu/k/TvltcJAM4=; b=D6Cf+TzXAWffgsolwp+iXvBIVkV6P3613gYPbI4FblwAYFM5+nOcRtgm15+wL8qMNR QtDbF708dYNEoj0MmhmjzbgDNMI4FthGzBI+TZQtxOVWlmTN2y0JY4qrpSfD1SeyczLq +5ExY5tx2OQR30QhA3Ca7yG+k+HxSjrldbcLIZD3RTQgs+r0zRPOqFPUIA2LwrqwO6aT Nlfi2fG6TxADU1Lgnr+CiaTgpys0kk70T05A9ajzXirD4enMM7tCyuBaJBCI4eZQ5iTi GfD2OhBxuBM6TZuSIVkwv5Gs9JbmZ3UaOYtdGO903fxadA4y9jIO4jbZAZ9UYAIU42PG bB/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kkZGA5zMICgSFHManAvIfubSG1Ccpwu/k/TvltcJAM4=; b=xjbDe11VowotZ3rtJfMRcgOPWRg53H2aOIpuhrhojY2ThJjVYWmpcAB/Wkng4sLP92 PIZFGWWye2g64Kg2MvO3PEZxskQnlVsaaZK/kFwK/sfFiyC7lMbT6NSTAJSHos/92adr FjdHmKMA3vj/pTXFVZoqPT/9+8byEiaSOgbjJ1frPMLucVuubb8Qesa4xofxjVQhtBol /NFMQ4yBwORf6G2Y85CXBWVaE2jvnsu6RoRxApSr4Aw6okhAwvfM2UZkxYs9reSARHr/ yH/NW/kcWjvNpmm/6h1UjBFuKS8VFmQEGrlzsHfGQyiVGWvVuIyP4ppPA4OVsBtvqOZh NJVA== X-Gm-Message-State: AOAM531V/wIErTk1c6DNzDjaVGvSZvmepISIYG3zAzvG8sanw0wlEEyd tKSmOKicfzMAyY92QOwgilGATIF0f/a+mA== X-Google-Smtp-Source: ABdhPJxFpZDlvlFZ6b0L+TbCw0zzL8EVBuDTlCKhDAo+FhXoAG3q1LDdvi4HoBGpMKMR2fWvPBWDYA== X-Received: by 2002:a05:6870:3b05:b0:ce:c0c9:663 with SMTP id gh5-20020a0568703b0500b000cec0c90663mr2780830oab.181.1645567633854; Tue, 22 Feb 2022 14:07:13 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id n25sm4901913otq.78.2022.02.22.14.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 14:07:13 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 4/6] target/riscv: Add support for mconfigptr Date: Tue, 22 Feb 2022 14:07:02 -0800 Message-Id: <20220222220704.2294924-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222220704.2294924-1-atishp@rivosinc.com> References: <20220222220704.2294924-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c30 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc30.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f96d26399607..89440241632a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -148,6 +148,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 /* Machine Trap Setup */ #define CSR_MSTATUS 0x300 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 25a0df498669..18fe17b62f51 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3021,6 +3021,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIMPID] = { "mimpid", any, read_zero }, [CSR_MHARTID] = { "mhartid", any, read_mhartid }, + [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Machine Trap Setup */ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, read_mstatus_i128 }, From patchwork Tue Feb 22 22:07:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12755984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FBF9C433EF for ; Tue, 22 Feb 2022 22:11:23 +0000 (UTC) Received: from localhost ([::1]:45174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMdNS-0000en-1o for qemu-devel@archiver.kernel.org; Tue, 22 Feb 2022 17:11:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMdJb-0005m1-0i for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:23 -0500 Received: from [2607:f8b0:4864:20::231] (port=33634 helo=mail-oi1-x231.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMdJV-0005Mg-1q for qemu-devel@nongnu.org; Tue, 22 Feb 2022 17:07:22 -0500 Received: by mail-oi1-x231.google.com with SMTP id x193so16221232oix.0 for ; Tue, 22 Feb 2022 14:07:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=er3O3f7Ph7vBsTAPhBit3sfvbgYjjR3ybH8BV0JDaWk=; b=dBhmo/XnAWDQxfXl4mSL5mHvuXKC/sfS2IU0Bo62L4CGFja2n7OZDq007puo3k4IQD 2G11ZuiXedRawl0WKqTOgn0OS7RHSNKPVARYfJ5wc4GLL5yNuaXQEmROeNI1bCz5BHWn XHTaQmDmcI89jeSbqOhPgw70TVirdkQCnvPQVUVy+ah4t++sj5J/KUiUgxvXk5G2mVZE 44acRMOVsg3Sa2GqaZhuwBaSsFxMu0MphtubbCMEmBruSv78mhDnNm3HXgJtabxl36Jf Pz8djKNGDDCAuOucQqMbAwHaz0/rTafCnIu6/avuYzBrgXsiEOHi6VF68kgn78B27BCw ADXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=er3O3f7Ph7vBsTAPhBit3sfvbgYjjR3ybH8BV0JDaWk=; b=EfSO9/LZ0gwUZa/5jArSoEsv7C2x8QeEIzFrWDQeA8vJvq8PmgheIwW11P3+bDVPsm 4/Meg2MUyoQiye09I/+fXYkhJphbwcRvMKeMCgmrpU7mFcN6Rqf2l0dZ8A9PLul2/Y1Z pPkSMVpVMtK9pqsyUSoxt+qi1SNOn/2HyIDFOFOZIObex25MWjC6MjirRoAPWZLuBv0F s80mC4WIBwu75nOvmGZe3eyzVZnvMM/dgX3i5vqX5NfnzvgPIIq2hwRe3m0qj9E4H/uy GA8eGzHkByxqI2NTVDPfJFi/LHKgM161kQi4ojJFEKED9bgJDAx9SrIVsDlTdPZf7T8c 5L8g== X-Gm-Message-State: AOAM531sXQ6GVc4OFhXMfprXhI1e/Ux83Adw4/hhc9biFGLOFANd8Idb bFek3/1gFc/rm41net9RciEmFEQBzDWBAA== X-Google-Smtp-Source: ABdhPJxQ7voxIY88OxVhRzFYhIrez6QrCdUXcEqWGtKuYUGQsegn/gGXHfOynPKNKmwps7MIojGsVg== X-Received: by 2002:a05:6808:124f:b0:2cd:199d:ee01 with SMTP id o15-20020a056808124f00b002cd199dee01mr3182119oiv.101.1645567635290; Tue, 22 Feb 2022 14:07:15 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id n25sm4901913otq.78.2022.02.22.14.07.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 14:07:14 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 5/6] target/riscv: Add *envcfg* CSRs support Date: Tue, 22 Feb 2022 14:07:03 -0800 Message-Id: <20220222220704.2294924-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222220704.2294924-1-atishp@rivosinc.com> References: <20220222220704.2294924-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::231 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 39 +++++++++++++++ target/riscv/csr.c | 107 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 24 +++++++++ 4 files changed, 175 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0741f9822cf0..e5c8694cf081 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -303,6 +303,11 @@ struct CPURISCVState { target_ulong spmbase; target_ulong upmmask; target_ulong upmbase; + + /* CSRs for execution enviornment configuration */ + uint64_t menvcfg; + target_ulong senvcfg; + uint64_t henvcfg; #endif float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 89440241632a..58a0a8d69f72 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -202,6 +202,9 @@ #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +/* Supervisor Configuration CSRs */ +#define CSR_SENVCFG 0x10A + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -247,6 +250,10 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 +/* Hypervisor Configuration CSRs */ +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -290,6 +297,10 @@ #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 +/* Machine Configuration CSRs */ +#define CSR_MENVCFG 0x30A +#define CSR_MENVCFGH 0x31A + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -654,6 +665,34 @@ typedef enum RISCVException { #define PM_EXT_CLEAN 0x00000002ULL #define PM_EXT_DIRTY 0x00000003ULL +/* Execution enviornment configuration bits */ +#define MENVCFG_FIOM BIT(0) +#define MENVCFG_CBIE (3UL << 4) +#define MENVCFG_CBCFE BIT(6) +#define MENVCFG_CBZE BIT(7) +#define MENVCFG_PBMTE BIT(62) +#define MENVCFG_STCE BIT(63) + +/* For RV32 */ +#define MENVCFGH_PBMTE BIT(30) +#define MENVCFGH_STCE BIT(31) + +#define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_CBIE MENVCFG_CBIE +#define SENVCFG_CBCFE MENVCFG_CBCFE +#define SENVCFG_CBZE MENVCFG_CBZE + +#define HENVCFG_FIOM MENVCFG_FIOM +#define HENVCFG_CBIE MENVCFG_CBIE +#define HENVCFG_CBCFE MENVCFG_CBCFE +#define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PBMTE MENVCFG_PBMTE +#define HENVCFG_STCE MENVCFG_STCE + +/* For RV32 */ +#define HENVCFGH_PBMTE MENVCFGH_PBMTE +#define HENVCFGH_STCE MENVCFGH_STCE + /* Offsets for every pair of control bits per each priv level */ #define XS_OFFSET 0ULL #define U_OFFSET 2ULL diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 18fe17b62f51..ff7e36596447 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1366,6 +1366,101 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +/* Execution environment configuration setup */ +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; + + if (riscv_cpu_mxl(env) == MXL_RV64) { + mask |= MENVCFG_PBMTE | MENVCFG_STCE; + } + env->menvcfg = (env->menvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; + uint64_t valh = (uint64_t)val << 32; + + env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->senvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; + + env->senvcfg = (env->senvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + + if (riscv_cpu_mxl(env) == MXL_RV64) { + mask |= HENVCFG_PBMTE | HENVCFG_STCE; + } + + env->henvcfg = (env->henvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; + uint64_t valh = (uint64_t)val << 32; + + env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3069,6 +3164,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, + /* Execution environment configuration */ + [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 9895930b2976..4a50a05937fa 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -220,6 +220,29 @@ static const VMStateDescription vmstate_kvmtimer = { } }; +/* TODO: henvcfg need both hyper_needed & envcfg_needed */ +static bool envcfg_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0); +} + +static const VMStateDescription vmstate_envcfg = { + .name = "cpu/envcfg", + .version_id = 1, + .minimum_version_id = 1, + .needed = envcfg_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.menvcfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINT64(env.henvcfg, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, @@ -280,6 +303,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_pointermasking, &vmstate_rv128, &vmstate_kvmtimer, + &vmstate_envcfg, NULL } }; From patchwork Tue Feb 22 22:07:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12755990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03E6AC433F5 for ; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id n25sm4901913otq.78.2022.02.22.14.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 14:07:16 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 6/6] target/riscv: Enable privileged spec version 1.12 Date: Tue, 22 Feb 2022 14:07:04 -0800 Message-Id: <20220222220704.2294924-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222220704.2294924-1-atishp@rivosinc.com> References: <20220222220704.2294924-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::235 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. This commit enforces the privilege version for csrs introduced in v1.12 or after. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +++++--- target/riscv/csr.c | 5 +++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2668f9c358b2..1c72dfffdc61 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } #if defined(TARGET_RISCV64) @@ -474,7 +474,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version = PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { priv_version = PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version = PRIV_VERSION_1_10_0; @@ -489,7 +491,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (priv_version) { set_priv_version(env, priv_version); } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } if (cpu->cfg.mmu) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ff7e36596447..1c70c19cf9bd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2886,6 +2886,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ int read_only = get_field(csrno, 0xC00) == 3; + int csr_min_priv = csr_ops[csrno].min_priv_ver; #if !defined(CONFIG_USER_ONLY) int effective_priv = env->priv; @@ -2918,6 +2919,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, return RISCV_EXCP_ILLEGAL_INST; } + if (env->priv_ver < csr_min_priv) { + return RISCV_EXCP_ILLEGAL_INST; + } + return csr_ops[csrno].predicate(env, csrno); }