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Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- In fact we could patch _just_ the opcode prefix in flush_area_local(). --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -247,8 +247,7 @@ unsigned int flush_area_local(const void { alternative("", "sfence", X86_FEATURE_CLFLUSHOPT); for ( i = 0; i < sz; i += c->x86_clflush_size ) - alternative_input(".byte " __stringify(NOP_DS_PREFIX) ";" - " clflush %0", + alternative_input("ds; clflush %0", "data16 clflush %0", /* clflushopt */ X86_FEATURE_CLFLUSHOPT, "m" (((const char *)va)[i])); @@ -298,11 +297,11 @@ void cache_writeback(const void *addr, u # define INPUT(addr) "a" (addr), BASE_INPUT(addr) #endif /* - * Note regarding the use of NOP_DS_PREFIX: it's faster to do a clflush + * Note regarding the "ds" prefix use: it's faster to do a clflush * + prefix than a clflush + nop, and hence the prefix is added instead * of letting the alternative framework fill the gap by appending nops. */ - alternative_io_2(".byte " __stringify(NOP_DS_PREFIX) "; clflush %[p]", + alternative_io_2("ds; clflush %[p]", "data16 clflush %[p]", /* clflushopt */ X86_FEATURE_CLFLUSHOPT, CLWB_ENCODING, --- a/xen/arch/x86/include/asm/nops.h +++ b/xen/arch/x86/include/asm/nops.h @@ -5,8 +5,6 @@ * Define nops for use with alternative(). */ -#define NOP_DS_PREFIX 0x3e - /* * Opteron 64bit nops * 1: nop From patchwork Wed Feb 23 10:12:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 12756642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59D7AC433EF for ; Wed, 23 Feb 2022 10:13:09 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.277263.473707 (Exim 4.92) (envelope-from ) id 1nModl-00065E-Pz; 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This breaks the cognitive complexity of needing to know which leaf a specifically named feature should reside in, and is shorter to write. It is also far easier to identify as correct at a glance, given the correlation with the CPUID leaf being read." Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -332,23 +332,22 @@ void __init early_cpu_init(void) cpuid(0x00000001, &eax, &ebx, &ecx, &edx); c->x86 = get_cpu_family(eax, &c->x86_model, &c->x86_mask); - edx &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)]; - ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_SSE3)]; + edx &= ~cleared_caps[FEATURESET_1d]; + ecx &= ~cleared_caps[FEATURESET_1c]; if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) c->x86_cache_alignment = ((ebx >> 8) & 0xff) * 8; /* Leaf 0x1 capabilities filled in early for Xen. */ - c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; - c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx; + c->x86_capability[FEATURESET_1d] = edx; + c->x86_capability[FEATURESET_1c] = ecx; printk(XENLOG_INFO "CPU Vendor: %s, Family %u (%#x), Model %u (%#x), Stepping %u (raw %08x)\n", x86_cpuid_vendor_to_str(c->x86_vendor), c->x86, c->x86, c->x86_model, c->x86_model, c->x86_mask, eax); - if (c->cpuid_level >= 7) { - cpuid_count(7, 0, &eax, &ebx, &ecx, &edx); - c->x86_capability[cpufeat_word(X86_FEATURE_CET_SS)] = ecx; - } + if (c->cpuid_level >= 7) + cpuid_count(7, 0, &eax, &ebx, + &c->x86_capability[FEATURESET_7c0], &edx); eax = cpuid_eax(0x80000000); if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { --- a/xen/arch/x86/efi/efi-boot.h +++ b/xen/arch/x86/efi/efi-boot.h @@ -685,11 +685,11 @@ static void __init efi_arch_cpu(void) boot_tsc_stamp = rdtsc(); - caps[cpufeat_word(X86_FEATURE_HYPERVISOR)] = cpuid_ecx(1); + caps[FEATURESET_1c] = cpuid_ecx(1); if ( (eax >> 16) == 0x8000 && eax > 0x80000000 ) { - caps[cpufeat_word(X86_FEATURE_SYSCALL)] = cpuid_edx(0x80000001); + caps[FEATURESET_e1d] = cpuid_edx(0x80000001); if ( cpu_has_nx ) trampoline_efer |= EFER_NXE; --- a/xen/arch/x86/mpparse.c +++ b/xen/arch/x86/mpparse.c @@ -516,7 +516,7 @@ static inline void __init construct_defa (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; processor.mpc_featureflag = - boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_FPU)]; + boot_cpu_data.x86_capability[FEATURESET_1d]; processor.mpc_reserved[0] = 0; processor.mpc_reserved[1] = 0; for (i = 0; i < 2; i++) { --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -48,7 +48,7 @@ void tsx_init(void) bool has_rtm_always_abort; if ( boot_cpu_data.cpuid_level >= 7 ) - boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_ARCH_CAPS)] + boot_cpu_data.x86_capability[FEATURESET_7d0] = cpuid_count_edx(7, 0); if ( cpu_has_arch_caps ) From patchwork Wed Feb 23 10:13:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 12756662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5DF0C433F5 for ; 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Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: [PATCH 3/3] x86: correct fencing around CLFLUSH Content-Language: en-US From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= References: <91935ffd-a270-f1a1-28f1-645fa4167fcd@suse.com> In-Reply-To: <91935ffd-a270-f1a1-28f1-645fa4167fcd@suse.com> X-ClientProxiedBy: AS9PR06CA0361.eurprd06.prod.outlook.com (2603:10a6:20b:460::13) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 80afe333-36c1-45b7-7170-08d9f6b52ea2 X-MS-TrafficTypeDiagnostic: AM6PR0402MB3944:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: i3f0j+l1BXYm63Llx2q90YUDZKFvmc1FK0a2q96chVbmbkcVdJCbjkK0FhhxJRRIL5VnOkt4LETM0zMnRboZceFs1grngGIbZFSXz5Be/rNzZuXp7Docsv0OUxMpytysH26sFpfTGNqYKWyWzJjhAJk9aOocuHpNmvslj1mzeRmhvbrVNIibqIZ+LHcbFTSpaWq64TDIQr244R0pgsrvUjJiqfzbCQD2E/9Tvu82pvfaQjebepVgl/2l6KvbiTnMOfafmjlrYRdyrbaxsvh4H/gtM9+gzQbpkzg6EyUE/n6/U726o7fSnOmWG0mIpVazJM14GS+af2Z9Gy34cOQATgEqBQaSPM12dOOn6iBJ/dudepdLDC+UWM/eFMZK2qTjTuHEOoiE3efk7xXKcHdCkYd1TCOv2si8e7M725XYa+2z+rvMZ2NptCbnrFziMOtUDO6f+rcR5EBEEDR/gw3NpYGdf+vuktbjnB1aO4Jn0Px8a1NvDq4Ms2xi/zoT91nXNTdQrZ7UgmClw7y5rGedLwNZ53d7xMQA8sqBg0GoiUikjN8gT2VJ5wZ41emDCn7NVXeB/IuirsDrPLYgcdE4qrwn+1Bxx8dEbCeZWbVKbuOBol5OX6umSzdO/ndTldLpsq0p98AdipVwxE3i7HzjM8Ufi8Tot0IzJJftrrzkWM47g7nwefeUwvNe5zOsClxuAomE0vDDqW2o3mjh6EfKfEBtj2D+baz0PEsU/IA5LuTM54H7YjJ1LW9PFJqbo3rs X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR04MB5600.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(366004)(31696002)(86362001)(6916009)(2906002)(316002)(54906003)(8936002)(31686004)(26005)(186003)(2616005)(4326008)(6512007)(66556008)(6486002)(6506007)(66946007)(36756003)(508600001)(8676002)(38100700002)(5660300002)(66476007)(43740500002)(45980500001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?2beO6ML4pID8USsbI7AM/SUdJ34m?= =?utf-8?q?cEX99YIYlrYLjCuswGAGNskerRIOtCq8xyeXKu6Sb6bzsoA0BWEeV3yOpZTORpf4c?= =?utf-8?q?NaH3c/dobggrA6vVNXMr6MDy2V20QyeymBrjcApoWKn5uc9p1tYRpfiPtZ1zdNFG2?= =?utf-8?q?kvPnWMUdKko3fLx17eUG/DJ9WkrTE35E/+4tFIbo19MGyuG2m1O2qHtpCeqFVAGuj?= =?utf-8?q?555EqCte3r22zgwpry6p5V8nSvPmaVf/cKFIKnBZk4gwvXAaXRXvPN43xvCS79Kxi?= =?utf-8?q?DT56oGC4lNRh+6gxC/FweCkFW4WK21Sr9QyAkQosN3c91vU5gxNlGjRCSdrWjNGYB?= =?utf-8?q?gUnOxMFJLbI7kg1B4mUHeyU1g2yuBzivc2VTyovvrxtnAUFlLqz2Xa8msLO3Fpkkn?= =?utf-8?q?0tIcB05w8K1p8RNJaClQ4QU51cBX/2379WRMWdW/aGja9AbrJZF5ufI8qPz+m7Ek5?= =?utf-8?q?+mb8Y3BbFIVwk+tb+tnxCyM+5o1s5NKBJHr4u5gFpnwLFOIJH+YFrE/jP8FVMmFwd?= =?utf-8?q?jJHX+lxYH/I7WPSZ/ixQQ7RnbAYqj52j3PVK7BSEa22ilCKmdEif+XbOBmQEEmx+S?= =?utf-8?q?c/raZjhJb2LGzVUrn8TvWWGUI3NEQgRmfR6lNtRq4PnqZirizub1bFDaZWbJrshwc?= =?utf-8?q?/2z5/p0/gnesluTEMPCRDyEogQZUnN0iGXPgFUL5boo36AIbU2QmM9tAJ4ZBE7Pe0?= =?utf-8?q?Zyw6oTMxq4Ow2iIknzWtCRERvuHibhFogyJX1CtMg31By1oreR6nNmBr1yfwSRTwh?= =?utf-8?q?lK8YDed/Tlj8sUeC8qFibspavYNWxVsD6+zHMjnYcz4p7m14ngxQm2Ly05y2+H/+2?= =?utf-8?q?ScyHHoxevzBFveltPfm6Vh76h/6LM77zXXk+25a6+ubTgxX2Ysdrka8iiwAAHUqNL?= =?utf-8?q?C+IibigSJJUszvvVcPbKB7didtsRu798MeQ7Wh3CJ11LyUizzmWmOEPqUzfovUnQn?= =?utf-8?q?HzjzTO60nwA3igCKARyhMrsid//4Yne5NsKRlebBVM8bQhc+7GFI1hq2lt/EuXKyt?= =?utf-8?q?XAKAZhjCn4B94sWAYhFOZVEl0OUIQw+a5ooOnNnpgsuGhptzlJFDcODq1MhljtOQM?= =?utf-8?q?y/a/DdZ3S95IZbScE8xR5E1SesCPh+KsPRXfL46uTEOpkhVm+smHkbP7tDsdPuN19?= =?utf-8?q?2jVnogx39JnjBoTSQkwlBLgmJ91tJqs2ZKWRqWOYJRa0Bhbb+g9pdpBiQTEiLP1jk?= =?utf-8?q?v6mu2XtzJhvZJthUE9sj6rDBszGt5lX1T8zO7qM3NgVmKYWZTQjXDG29/o9cKSuw4?= =?utf-8?q?TNScQoosd7p9Zjod6CPS2Yy2DOyJ/YLzvXL+FXzRGt7jZAtULuEEnfDP6kXxxGPSg?= =?utf-8?q?hMWa+xvW6oxo+UMobiQEGXX8wz+hebfNl5yBnxbmvvMTbALEr3o/tRqdH9g6cS8tt?= =?utf-8?q?iPH6LM9sWO0fhr7o4AZXkuDfCsbt6cFkXd+FYXHahScAqdwNb9PFvdNw3IIGHt9gJ?= =?utf-8?q?s2tGk6u46vFJHIeljIZybcIocU1N8JxHBoCrxjhJh5aZhVvirdxqbFmlbT8DRS20s?= =?utf-8?q?PKoh8Bdb/yNliHZbqQuunh6Afj5EVb0JNo7Rmj+VGG7/7498iDZYbvM=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80afe333-36c1-45b7-7170-08d9f6b52ea2 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2022 10:13:48.2953 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lCSPMnGN90FqVsojaQuh7oCjVREzxu6IoC6UjpwOSUf2mgf7r8W1bRUUPJRtjp+hTKA6MmlCICU4mVEReOPbwA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3944 As noted in the context of 3330013e6739 ("VT-d / x86: re-arrange cache syncing"): While cache_writeback() has the SFENCE on the correct side of CLFLUSHOPT, flush_area_local() doesn't. While I can't prove it due to lacking a copy of the old SDM version, I can only assume this placement was a result of what had been described there originally. In any event recent versions of the SDM hve been telling us otherwise. For AMD (and Hygon, albeit there it's benign, since all their CPUs are expected to support CLFLUSHOPT) the situation is more complex: MFENCE is needed ahead and/or after CLFLUSH when the CPU doesn't also support CLFLUSHOPT. (It's "and" in our case, as we cannot know what the caller's needs are.) Fixes: 623c720fc8da3 ("x86: use CLFLUSHOPT when available") Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -346,9 +346,14 @@ void __init early_cpu_init(void) c->x86_model, c->x86_model, c->x86_mask, eax); if (c->cpuid_level >= 7) - cpuid_count(7, 0, &eax, &ebx, + cpuid_count(7, 0, &eax, + &c->x86_capability[FEATURESET_7b0], &c->x86_capability[FEATURESET_7c0], &edx); + if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || + cpu_has(c, X86_FEATURE_CLFLUSHOPT)) + setup_force_cpu_cap(X86_FEATURE_CLFLUSH_NO_MFENCE); + eax = cpuid_eax(0x80000000); if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { ebx = eax >= 0x8000001f ? cpuid_ebx(0x8000001f) : 0; --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -245,12 +245,15 @@ unsigned int flush_area_local(const void c->x86_clflush_size && c->x86_cache_size && sz && ((sz >> 10) < c->x86_cache_size) ) { - alternative("", "sfence", X86_FEATURE_CLFLUSHOPT); + alternative("mfence", , X86_FEATURE_CLFLUSH_NO_MFENCE); for ( i = 0; i < sz; i += c->x86_clflush_size ) alternative_input("ds; clflush %0", "data16 clflush %0", /* clflushopt */ X86_FEATURE_CLFLUSHOPT, "m" (((const char *)va)[i])); + alternative_2("mfence", + , X86_FEATURE_CLFLUSH_NO_MFENCE, + "sfence", X86_FEATURE_CLFLUSHOPT); flags &= ~FLUSH_CACHE; } else @@ -274,6 +277,8 @@ void cache_writeback(const void *addr, u unsigned int clflush_size = current_cpu_data.x86_clflush_size ?: 16; const void *end = addr + size; + alternative("mfence", , X86_FEATURE_CLFLUSH_NO_MFENCE); + addr -= (unsigned long)addr & (clflush_size - 1); for ( ; addr < end; addr += clflush_size ) { --- a/xen/arch/x86/include/asm/cpufeatures.h +++ b/xen/arch/x86/include/asm/cpufeatures.h @@ -24,7 +24,7 @@ XEN_CPUFEATURE(APERFMPERF, X86_SY XEN_CPUFEATURE(MFENCE_RDTSC, X86_SYNTH( 9)) /* MFENCE synchronizes RDTSC */ XEN_CPUFEATURE(XEN_SMEP, X86_SYNTH(10)) /* SMEP gets used by Xen itself */ XEN_CPUFEATURE(XEN_SMAP, X86_SYNTH(11)) /* SMAP gets used by Xen itself */ -/* Bit 12 - unused. */ +XEN_CPUFEATURE(CLFLUSH_NO_MFENCE, X86_SYNTH(12)) /* No MFENCE needed to serialize CLFLUSH */ XEN_CPUFEATURE(IND_THUNK_LFENCE, X86_SYNTH(13)) /* Use IND_THUNK_LFENCE */ XEN_CPUFEATURE(IND_THUNK_JMP, X86_SYNTH(14)) /* Use IND_THUNK_JMP */ XEN_CPUFEATURE(SC_NO_BRANCH_HARDEN, X86_SYNTH(15)) /* (Disable) Conditional branch hardening */