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Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -744,6 +744,23 @@ void __init detect_zen2_null_seg_behavio } +static void __init noinline detect_bugs(const struct cpuinfo_x86 *c) +{ + /* + * Older AMD CPUs don't save/load FOP/FIP/FDP unless an FPU exception + * is pending. Xen works around this at (F)XRSTOR time. + */ + if (!cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS)) + setup_force_cpu_cap(X86_BUG_FPU_PTRS); + + /* + * AMD CPUs before Zen2 don't clear segment bases/limits when loading + * a NULL selector. + */ + if (!cpu_has_nscb) + setup_force_cpu_cap(X86_BUG_NULL_SEG); +} + static void cf_check init_amd(struct cpuinfo_x86 *c) { u32 l, h; @@ -781,13 +805,6 @@ static void init_amd(struct cpuinfo_x86 wrmsr_amd_safe(0xc001100d, l, h & ~1); } - /* - * Older AMD CPUs don't save/load FOP/FIP/FDP unless an FPU exception - * is pending. Xen works around this at (F)XRSTOR time. - */ - if (c == &boot_cpu_data && !cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS)) - setup_force_cpu_cap(X86_BUG_FPU_PTRS); - if (c->x86 == 0x0f || c->x86 == 0x11) /* Always dispatch serialising on this hardare. */ __set_bit(X86_FEATURE_LFENCE_DISPATCH, c->x86_capability); @@ -796,17 +813,13 @@ static void init_amd(struct cpuinfo_x86 amd_init_ssbd(c); - /* Probe for NSCB on Zen2 CPUs when not virtualised */ - if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data && - c->x86 == 0x17) - detect_zen2_null_seg_behaviour(); + if (c == &boot_cpu_data) { + /* Probe for NSCB on Zen2 CPUs when not virtualised */ + if (!cpu_has_hypervisor && !cpu_has_nscb && c->x86 == 0x17) + detect_zen2_null_seg_behaviour(); - /* - * AMD CPUs before Zen2 don't clear segment bases/limits when loading - * a NULL selector. - */ - if (c == &boot_cpu_data && !cpu_has_nscb) - setup_force_cpu_cap(X86_BUG_NULL_SEG); + detect_bugs(c); + } /* MFENCE stops RDTSC speculation */ if (!cpu_has_lfence_dispatch) From patchwork Thu Feb 24 13:24:59 2022 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?SVAenAmTJ6WMu66nqZyFxqrLs9Ab?= =?utf-8?q?pr+awLqSKphE9Vi4ZPc6fiZ6uHK+IeBNPWZBiLmN6F203LEx5Htv+q1NGtBtcmMjN?= =?utf-8?q?opf3ybDB3//sjyqkIYcx4CIqPyqdLx1OGkIdl2yy97SakFIpv72SqxKu5X8ppA3Mi?= =?utf-8?q?xUpg8sPJO/tFlkeke6RBi1DpF+HuD6PDSYVe+iwjZPfhUm/ETqrCUycW3ICpNEVru?= =?utf-8?q?JuX+Tk/81Ha10SELUuMyctr3X7ijzUJB3+4ej3C+4FK7B1AnPKElXoACTxiwGXVBr?= =?utf-8?q?g7vFNAuA9hT+wPqiO5oRvi59jwCePHshWdLYvEkACQ5hcM9HpkqK8iIAMdYmOsowC?= =?utf-8?q?5n17yXYK0I8TFHiGaeQOK4/DKKDgBQuNcVcA5QfxLmhYaT8stPFUycYjI5q4oVImh?= =?utf-8?q?hCVCEJDgqWGlSQVBbuICVjiztJext5glWx3J1GaF212IpJyjq3HVDVJiGhRqH5G13?= =?utf-8?q?N5GrmjVpNb+m8ltxM74Uj5w8NIvBwftynAL+9ayfvGqjLD7FcK6UapZ9qEsEjf2Nf?= =?utf-8?q?3AROZkjoOnjvtH26fPsRdwEGQPp28J2PwFWxu5R94vNhVqGxx95XKTe3aBceA46oP?= =?utf-8?q?02ycQT6KyiUv8tz48TwO85IC9s0EKG5PxJR+5vVKScy2o9kAODbs2Pnz4cKAI72vr?= =?utf-8?q?wwHAP2WIwz17UCdQF7Fo+UTK6v1iDlvLaqKYB3G/3nYLoFs/7N9xm0KfL0bQE3w4L?= =?utf-8?q?RhfpTTaWWqCu3trNiWC86NXiDPPKSaZosSxD/bGfC3sizm4c2+mDLJUhqn/fb1U18?= =?utf-8?q?OFEAZKD4bPVJnXc/WWqmq0J4ZOa66Q7U9ID5aCNbWVstsi23U3OlmDDeqPPyfXLR7?= =?utf-8?q?pHRkfSftmCU7pNgYekK0nP0/vO2OvybL4gi2G5N5IHHwArOcouGENoggBoJy6q+fy?= =?utf-8?q?5F7YBbi0x9GbmTkH9+RyoumRhjzf/uRDcnWsu/+vJivw7mrOXRs8GIOj9954fojPu?= =?utf-8?q?JMB9bH1ZxUTaOJf+X42PzgPL5Dr+OM7fkXfwFX1KsWu+DAoCfZZFo9Rfpcr4PNcwZ?= =?utf-8?q?2Z0Xhv4d2Y4mW2Gk8v6ubdKb3p7IEnN6mxeLewaod/8EGdb7YycNGp+7DnVMU6+e1?= =?utf-8?q?NUGWrZb1MVi2euXGZ1AWU7rptbVABHVlkTw9BWemqn+wvxnZTEPF9dXPnU1m6V05o?= =?utf-8?q?/qJm1vIJfo/SIDeWxzdsVP6mwycbnHzqiFwggQcP42KNnNF2y3P1A1qGKBuQBXiBX?= =?utf-8?q?xTU0yN4y+loHgCa0yesRIc0uIV22bJcLHd1x9x7KtDNO1/ue4SCiEE65OQLwrYFt8?= =?utf-8?q?oae24qtmao+g1gptSpXqQpsK1NSotiTgLKCeUYdUDZYcBQDktFkfX/ALwLDB/ZX2A?= =?utf-8?q?sJVwT2+0ZjOXSVUu8kgaTs8zq6saKm1FzOpVv82xQeNnq+8FjUeHuYDm0yQo+zAu+?= =?utf-8?q?Q5u18KwpHIDlQqz34SrHM3JJ3MNKWnAl9QssaujzeBc26HfLzN/QGOT7kZZND1UNw?= =?utf-8?q?8N/bU31DK7b2jmnfbg/FWIVHVd5NOhn7etuIVFX/MXrWmnwYaHK06i5BrEUrqK/Nk?= =?utf-8?q?tD7B3F35nUiCQ2sgpZk/nLSowiwERr+HB/uegxezQzfpEBKHqcNZt+c=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: a530dd74-bf7a-48e7-8192-08d9f7990eea X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2022 13:25:00.3348 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: H+5trbyvSpiWi7KOnqNv7WgLR6c1r78D3tzFDr8uZO14VligxG+lgyQuJiBmmZMZXHuLX3UhFXPf9KMl15/mkQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5971 As noted in the context of 3330013e6739 ("VT-d / x86: re-arrange cache syncing"): While cache_writeback() has the SFENCE on the correct side of CLFLUSHOPT, flush_area_local() doesn't. While I can't prove it due to lacking a copy of the old SDM version, I can only assume this placement was a result of what had been described there originally. In any event recent versions of the SDM hve been telling us otherwise. For AMD the situation is more complex: MFENCE is needed ahead and/or after CLFLUSH when the CPU doesn't also support CLFLUSHOPT. (It's "and" in the flush_area_local() case, as we cannot know what the caller's needs are. For cache_writeback() fencing ahead of the flush is sufficient.) Fixes: 623c720fc8da3 ("x86: use CLFLUSHOPT when available") Signed-off-by: Jan Beulich --- TBD: I'd be okay with not touching cache_writeback(), for only being used by VT-d right now. --- v2: Mark AMD behavior as a bug rather than a feature. Retain quotes. --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -761,6 +761,13 @@ static void __init noinline detect_bugs( */ if (!cpu_has_nscb) setup_force_cpu_cap(X86_BUG_NULL_SEG); + + /* + * AMD CPUs not supporting CLFLUSHOPT require MFENCE to serialize + * CLFLUSH against other memory accesses. + */ + if (!cpu_has_clflushopt) + setup_force_cpu_cap(X86_BUG_CLFLUSH_MFENCE); } static void init_amd(struct cpuinfo_x86 *c) --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -245,12 +245,15 @@ unsigned int flush_area_local(const void c->x86_clflush_size && c->x86_cache_size && sz && ((sz >> 10) < c->x86_cache_size) ) { - alternative("", "sfence", X86_FEATURE_CLFLUSHOPT); + alternative("", "mfence", X86_BUG_CLFLUSH_MFENCE); for ( i = 0; i < sz; i += c->x86_clflush_size ) alternative_input("ds; clflush %0", "data16 clflush %0", /* clflushopt */ X86_FEATURE_CLFLUSHOPT, "m" (((const char *)va)[i])); + alternative_2("", + "sfence", X86_FEATURE_CLFLUSHOPT, + "mfence", X86_BUG_CLFLUSH_MFENCE); flags &= ~FLUSH_CACHE; } else @@ -274,6 +277,8 @@ void cache_writeback(const void *addr, u unsigned int clflush_size = current_cpu_data.x86_clflush_size ?: 16; const void *end = addr + size; + alternative("", "mfence", X86_BUG_CLFLUSH_MFENCE); + addr -= (unsigned long)addr & (clflush_size - 1); for ( ; addr < end; addr += clflush_size ) { --- a/xen/arch/x86/include/asm/cpufeatures.h +++ b/xen/arch/x86/include/asm/cpufeatures.h @@ -47,6 +47,7 @@ XEN_CPUFEATURE(RET_SIMPLE, X86_SY #define X86_BUG_FPU_PTRS X86_BUG( 0) /* (F)X{SAVE,RSTOR} doesn't save/restore FOP/FIP/FDP. */ #define X86_BUG_NULL_SEG X86_BUG( 1) /* NULL-ing a selector preserves the base and limit. */ +#define X86_BUG_CLFLUSH_MFENCE X86_BUG( 2) /* MFENCE needed to serialize CLFLUSH */ /* Total number of capability words, inc synth and bug words. */ #define NCAPINTS (FSCAPINTS + X86_NR_SYNTH + X86_NR_BUG) /* N 32-bit words worth of info */