From patchwork Thu Feb 24 20:18:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12759214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95C05C433EF for ; Thu, 24 Feb 2022 20:23:38 +0000 (UTC) Received: from localhost ([::1]:36246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNKeH-0005fE-PB for qemu-devel@archiver.kernel.org; Thu, 24 Feb 2022 15:23:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNKa4-00085k-Dw; Thu, 24 Feb 2022 15:19:16 -0500 Received: from [2607:f8b0:4864:20::230] (port=38693 helo=mail-oi1-x230.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nNKa2-000305-Ey; Thu, 24 Feb 2022 15:19:16 -0500 Received: by mail-oi1-x230.google.com with SMTP id y7so4744893oih.5; Thu, 24 Feb 2022 12:19:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y522670yPReb9dPlaPl6X8HKDCE4uL62kHfCdRfbumE=; b=Im6oWDOQ6Vg3D+XP2JntGeKUiw9f9QyXUq8/2uyr6mSctt8Pxfet7xV+AZFGEEd1Za fwI1hNdawCgqQc3Ts29W3HmQ49pzdYoQ0iXBKcHmcYeOzZF4IxQLARBmOQZ+A47n8ydq aWv7Q4P8QZGLeGlQi61JWOyA/M2QthFqyRtHGJqaz99hTIqYzbr+wRmGsa5bLE2KADT4 dXnfH9A2v72kiDdWuRG+PhRAaUvq2xF3iTI/RDd4CBzWkt0CV9yay8PBI+js22EJXrg3 kEVmtxcIedX22KE6hyD3ZCPR3hfEMUSRQdwRgyEGAZqdxZhJaFUJgiSoJ1uvqCcg4s68 uogg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y522670yPReb9dPlaPl6X8HKDCE4uL62kHfCdRfbumE=; b=bW/Mgsv7P1/KxmIOVLS0G7C0cvSYx1qgvhMHaHqDG9pWtdgDYtOFFZy9ETlYs6lrOm +AX6g3OfXGy1zP7cVP9ccXfGVmtwTAbv83gZ9/cy3dd5JOQ8vaJhv+J4R5XY5/HjbEnB MPtFlYwnOJqTAKc8W6TL8ZNAvh1v7A8t653/29c++Gs2x5Pb1Mc8aEaEpDyvU5VWsIp2 SF/cEArhhGl55Wijzyq+uO9LlQeuZ9ycBGQvouNjAEr2oGDtxbZN8r4RQstShVMaDa+4 QuVgNZozrNwthTReFWsxb94XjuMpZxBxIubOdQHZiTBxK8hxkAJxKgQMYE/qP2VvNxsk H/NA== X-Gm-Message-State: AOAM532qsaGFpKqFDqyk/bT4xBfUvtuAhl2dRHvU2ImXF/tHvZyyUJSL AJ4nHFkoEs9xCwR5Omgps9JQxFUCPyI= X-Google-Smtp-Source: ABdhPJzJO40rz+U0iWe+WjUj0DH62txLMO54vnXx4P4bZkRKvfmYDwf5H2ZJ/L74/W2Fktosqa3yrA== X-Received: by 2002:a05:6808:1396:b0:2d5:38a8:d5b2 with SMTP id c22-20020a056808139600b002d538a8d5b2mr8183589oiw.243.1645733952390; Thu, 24 Feb 2022 12:19:12 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c6:bec1:d9bb:8ce0:5ce7:a377]) by smtp.gmail.com with ESMTPSA id bh42-20020a056808182a00b002d538a8d5afsm305775oib.7.2022.02.24.12.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Feb 2022 12:19:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v13 1/4] target/ppc: make power8-pmu.c CONFIG_TCG only Date: Thu, 24 Feb 2022 17:18:57 -0300 Message-Id: <20220224201900.1037465-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220224201900.1037465-1-danielhb413@gmail.com> References: <20220224201900.1037465-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::230 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is an exclusive TCG helper. Gating it with CONFIG_TCG and changing meson.build accordingly will prevent problems --disable-tcg and --disable-linux-user later on. We're also changing the uses of !kvm_enabled() to tcg_enabled() to avoid adding "defined(CONFIG_TCG)" ifdefs, since tcg_enabled() will be defaulted to false with --disable-tcg and the block will always be skipped. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 16 +++++++--------- target/ppc/machine.c | 6 +++++- target/ppc/meson.build | 2 +- target/ppc/power8-pmu.h | 4 ++-- 4 files changed, 15 insertions(+), 13 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 61d36b11a0..544e052290 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5698,12 +5698,10 @@ static void register_power9_mmu_sprs(CPUPPCState *env) */ static void init_tcg_pmu_power8(CPUPPCState *env) { -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) /* Init PMU overflow timers */ - if (!kvm_enabled()) { + if (tcg_enabled()) { cpu_ppc_pmu_init(env); } -#endif } static void init_proc_book3s_common(CPUPPCState *env) @@ -7167,14 +7165,14 @@ static void ppc_cpu_reset(DeviceState *dev) #if !defined(CONFIG_USER_ONLY) env->nip = env->hreset_vector | env->excp_prefix; -#if defined(CONFIG_TCG) - if (env->mmu_model != POWERPC_MMU_REAL) { - ppc_tlb_invalidate_all(env); + + if (tcg_enabled()) { + if (env->mmu_model != POWERPC_MMU_REAL) { + ppc_tlb_invalidate_all(env); + } + pmu_update_summaries(env); } -#endif /* CONFIG_TCG */ #endif - - pmu_update_summaries(env); hreg_compute_hflags(env); env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 1b63146ed1..e673944597 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "helper_regs.h" #include "mmu-hash64.h" #include "migration/cpu.h" @@ -20,7 +21,10 @@ static void post_load_update_msr(CPUPPCState *env) */ env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - pmu_update_summaries(env); + + if (tcg_enabled()) { + pmu_update_summaries(env); + } } static int get_avr(QEMUFile *f, void *pv, size_t size, diff --git a/target/ppc/meson.build b/target/ppc/meson.build index a49a8911e0..79beaff147 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -16,6 +16,7 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files( 'misc_helper.c', 'timebase_helper.c', 'translate.c', + 'power8-pmu.c', )) ppc_ss.add(libdecnumber) @@ -51,7 +52,6 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'mmu-book3s-v3.c', 'mmu-hash64.c', 'mmu-radix64.c', - 'power8-pmu.c', )) target_arch += {'ppc': ppc_ss} diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index a839199561..256d90f523 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -13,11 +13,11 @@ #ifndef POWER8_PMU #define POWER8_PMU -void cpu_ppc_pmu_init(CPUPPCState *env); - #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void cpu_ppc_pmu_init(CPUPPCState *env); void pmu_update_summaries(CPUPPCState *env); #else +static inline void cpu_ppc_pmu_init(CPUPPCState *env) { } static inline void pmu_update_summaries(CPUPPCState *env) { } #endif From patchwork Thu Feb 24 20:18:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12759213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61AE8C433FE for ; Thu, 24 Feb 2022 20:21:30 +0000 (UTC) Received: from localhost ([::1]:59174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNKcC-00025A-Fi for qemu-devel@archiver.kernel.org; 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Thu, 24 Feb 2022 12:19:14 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v13 2/4] target/ppc: finalize pre-EBB PMU logic Date: Thu, 24 Feb 2022 17:18:58 -0300 Message-Id: <20220224201900.1037465-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220224201900.1037465-1-danielhb413@gmail.com> References: <20220224201900.1037465-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::231 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" There are still PMU exclusive bits to handle in fire_PMC_interrupt() before implementing the EBB support. Let's finalize it now to avoid dealing with PMU and EBB logic at the same time in the next patches. fire_PMC_interrupt() will fire an Performance Monitor alert depending on MMCR0_PMAE. If we are required to freeze the timers (MMCR0_FCECE) we'll also need to update summaries and delete the existing overflow timers. In all cases we're going to update the cycle counters. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 236e8e66e9..d245663158 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -222,6 +222,20 @@ static void pmu_update_overflow_timers(CPUPPCState *env) } } +static void pmu_delete_timers(CPUPPCState *env) +{ + QEMUTimer *pmc_overflow_timer; + int sprn; + + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + pmc_overflow_timer = get_cyc_overflow_timer(env, sprn); + + if (pmc_overflow_timer) { + timer_del(pmc_overflow_timer); + } + } +} + void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { bool hflags_pmcc0 = (value & MMCR0_PMCC0) != 0; @@ -271,8 +285,26 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; - if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { - return; + pmu_update_cycles(env); + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) { + env->spr[SPR_POWER_MMCR0] &= ~MMCR0_FCECE; + env->spr[SPR_POWER_MMCR0] |= MMCR0_FC; + + /* Changing MMCR0_FC requires a new HFLAGS_INSN_CNT calc */ + pmu_update_summaries(env); + + /* + * Delete all pending timers if we need to freeze + * the PMC. We'll restart them when the PMC starts + * running again. + */ + pmu_delete_timers(env); + } + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) { + env->spr[SPR_POWER_MMCR0] &= ~MMCR0_PMAE; + env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO; } /* PMC interrupt not implemented yet */ From patchwork Thu Feb 24 20:18:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12759212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26059C433F5 for ; Thu, 24 Feb 2022 20:21:29 +0000 (UTC) Received: from localhost ([::1]:59104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNKcC-00022P-2O for qemu-devel@archiver.kernel.org; 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Thu, 24 Feb 2022 12:19:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v13 3/4] target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions Date: Thu, 24 Feb 2022 17:18:59 -0300 Message-Id: <20220224201900.1037465-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220224201900.1037465-1-danielhb413@gmail.com> References: <20220224201900.1037465-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::22e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem state at the time the event-based branch was supposed to occur. ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB exception and External EBB exception. They are being added as POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB. PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that occurred and trigger the appropriate exception. Both exceptions are doing the same thing in this first implementation: clear BESCR_GE and enter the branch with env->nip retrieved from SPR_EBBHR. The checks being done by the interrupt code are msr_pr and BESCR_GE states. All other checks (EBB facility check, BESCR_PME bit, specific bits related to the event type) must be done beforehand. Reviewed-by: Cédric Le Goater Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 5 ++++- target/ppc/cpu_init.c | 4 ++++ target/ppc/excp_helper.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5b01d409b3..79375e8df4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -127,8 +127,10 @@ enum { /* ISA 3.00 additions */ POWERPC_EXCP_HVIRT = 101, POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */ + POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */ + POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */ /* EOL */ - POWERPC_EXCP_NB = 103, + POWERPC_EXCP_NB = 105, /* QEMU exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ }; @@ -2434,6 +2436,7 @@ enum { PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */ + PPC_INTERRUPT_EBB, /* Event-based Branch exception */ }; /* Processor Compatibility mask (PCR) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 544e052290..073fd10168 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2060,6 +2060,10 @@ static void init_excp_POWER8(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; + + /* Userland exceptions without vector value in PowerISA v3.1 */ + env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; + env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; #endif } diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 6538c56ab0..5e7d29ae00 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1554,6 +1554,21 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) new_msr |= (target_ulong)MSR_HVB; new_msr |= env->msr & ((target_ulong)1 << MSR_RI); break; + case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */ + case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */ + env->spr[SPR_BESCR] &= ~BESCR_GE; + + /* + * Save NIP for rfebb insn in SPR_EBBRR. Next nip is + * stored in the EBB Handler SPR_EBBHR. + */ + env->spr[SPR_EBBRR] = env->nip; + powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr); + + /* + * This exception is handled in userspace. No need to proceed. + */ + return; case POWERPC_EXCP_THERM: /* Thermal interrupt */ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ case POWERPC_EXCP_VPUA: /* Vector assist exception */ @@ -1797,6 +1812,24 @@ static void ppc_hw_interrupt(CPUPPCState *env) powerpc_excp(cpu, POWERPC_EXCP_THERM); return; } + /* EBB exception */ + if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) { + /* + * EBB exception must be taken in problem state and + * with BESCR_GE set. + */ + if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) { + env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB); + + if (env->spr[SPR_BESCR] & BESCR_PMEO) { + powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); + } else if (env->spr[SPR_BESCR] & BESCR_EEO) { + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); + } + + return; + } + } } if (env->resume_as_sreset) { From patchwork Thu Feb 24 20:19:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12759217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B29EFC433F5 for ; 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Thu, 24 Feb 2022 12:19:18 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c6:bec1:d9bb:8ce0:5ce7:a377]) by smtp.gmail.com with ESMTPSA id bh42-20020a056808182a00b002d538a8d5afsm305775oib.7.2022.02.24.12.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Feb 2022 12:19:18 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v13 4/4] target/ppc: trigger PERFM EBBs from power8-pmu.c Date: Thu, 24 Feb 2022 17:19:00 -0300 Message-Id: <20220224201900.1037465-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220224201900.1037465-1-danielhb413@gmail.com> References: <20220224201900.1037465-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::230 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set. fire_PMC_interrupt() will execute a new ebb_perfm_excp() helper that will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are set, do_ebb() will attempt to trigger a PERFM EBB event. If the EBB facility is enabled in both FSCR and HFSCR we consider that the EBB is valid and set BESCR_PMEO. After that, if we're running in problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll queue a PPC_INTERRUPT_EBB. Signed-off-by: Daniel Henrique Barboza --- target/ppc/excp_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/power8-pmu.c | 3 +-- 3 files changed, 50 insertions(+), 2 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5e7d29ae00..89b7b3ac00 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2066,6 +2066,54 @@ void helper_rfebb(CPUPPCState *env, target_ulong s) env->spr[SPR_BESCR] &= ~BESCR_GE; } } + +/* + * Triggers or queues an 'ebb_excp' EBB exception. All checks + * but FSCR, HFSCR and msr_pr must be done beforehand. + * + * PowerISA v3.1 isn't clear about whether an EBB should be + * postponed or cancelled if the EBB facility is unavailable. + * Our assumption here is that the EBB is cancelled if both + * FSCR and HFSCR EBB facilities aren't available. + */ +static void do_ebb(CPUPPCState *env, int ebb_excp) +{ + PowerPCCPU *cpu = env_archcpu(env); + CPUState *cs = CPU(cpu); + + /* + * FSCR_EBB and FSCR_IC_EBB are the same bits used with + * HFSCR. + */ + helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB); + helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB); + + if (ebb_excp == POWERPC_EXCP_PERFM_EBB) { + env->spr[SPR_BESCR] |= BESCR_PMEO; + } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) { + env->spr[SPR_BESCR] |= BESCR_EEO; + } + + if (msr_pr == 1) { + powerpc_excp(cpu, ebb_excp); + } else { + env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB; + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +void helper_ebb_perfm_excp(CPUPPCState *env) +{ + bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE && + env->spr[SPR_BESCR] & BESCR_PME && + env->spr[SPR_BESCR] & BESCR_GE; + + if (!perfm_ebb_enabled) { + return; + } + + do_ebb(env, POWERPC_EXCP_PERFM_EBB); +} #endif /*****************************************************************************/ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ab008c9d4e..8c2c03fd48 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(rfebb, void, env, tl) +DEF_HELPER_1(ebb_perfm_excp, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index d245663158..38e1ecb782 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -307,8 +307,7 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO; } - /* PMC interrupt not implemented yet */ - return; + helper_ebb_perfm_excp(env); } /* This helper assumes that the PMC is running. */