From patchwork Mon Feb 28 00:45:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1AB53C433EF for ; Mon, 28 Feb 2022 00:46:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97C3C10E225; Mon, 28 Feb 2022 00:46:44 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5922210E21C for ; Mon, 28 Feb 2022 00:46:43 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id CC234838FD; Mon, 28 Feb 2022 01:46:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009201; bh=6ucLCp5bAAtjqokyTODJTnHUYRUAgzR7q0kvgQ5ximw=; h=From:To:Cc:Subject:Date:From; b=VxOI2nWo6RO+XpJNkpXA/8dDuXYFPe8a9CVoW5v29k1JX5894Qjzc8mCZvrEZSUSF 9++rfiltoJoTIlSOtjglQ6pc0ybpoVT+LiSFHwPUNwbS3TNiCwraH2KikvUVGSSsgP QT8ZQqqdZQI4ODKIQ1+UlicrQ3goBrb1HkiUcB15TFUfWmN/lKMY6cBVJF6hu2Mt6J xfxbNSa/yYqQ9p0B7GJHapiNYZyGTGxsvENgPgjoE44J34XnjqaEP76TKwVh+hxV19 C2I3JADEQ9grgUEq5zslAKE6Lal868kAhW+KoKHGBArm//etAyQ61QUkErOMfPByNe dSTllAtl/znpA== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/9] dt-bindings: mxsfb: Add compatible for i.MX8MP Date: Mon, 28 Feb 2022 01:45:57 +0100 Message-Id: <20220228004605.367040-1-marex@denx.de> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , devicetree@vger.kernel.org, Peng Fan , Alexander Stein , Rob Herring , Laurent Pinchart , Robby Cai , Sam Ravnborg Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add compatible string for i.MX8MP LCDIF variant. This is called LCDIFv3 and is completely different from the LCDIFv3 found in i.MX23 in that it has a completely scrambled register layout compared to all previous LCDIF variants. The new LCDIFv3 also supports 36bit address space. However, except for the complete bit reshuffling, this is still LCDIF and it still works like one. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Rob Herring Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner Cc: devicetree@vger.kernel.org --- Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index 900a56cae80e6..9831ab53a053d 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -28,6 +28,7 @@ properties: - fsl,imx7d-lcdif - fsl,imx8mm-lcdif - fsl,imx8mn-lcdif + - fsl,imx8mp-lcdif - fsl,imx8mq-lcdif - const: fsl,imx6sx-lcdif From patchwork Mon Feb 28 00:45:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D150EC433EF for ; Mon, 28 Feb 2022 00:47:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FD0810E24D; Mon, 28 Feb 2022 00:46:57 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8119310E225 for ; Mon, 28 Feb 2022 00:46:43 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 72E4383A45; Mon, 28 Feb 2022 01:46:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009201; bh=QeMjNwm07tzx3hS9Y6txbXz3qEAe15cgYi1K/MTpAMA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0Ej57pmIgzwecQYeuQZezH0qCrAuBIyouUh2IZFbEvtEifTwLZpokgiV40mOXoGJP fvx+eB470dliAIdTBzBcVSfATY1ucjcJL6RmgWxGO5cdpRruk03/V8QzJyDQ+vdD+e uXKiK1oOEXtzrp1m5I5A+mTtdHS714MjPUafYVVKGEnQV7FvVcsYocJhdtliIMmK72 bH5Bj2dasvi8MeqcOXOvNX+0aNLl7xZx8/1i6tnQ53khjjoN9F59HnVsgGJKgXkO42 yamhfxZI49KGzihu4SlbEr7NY+BjWECmK83kxF0L+zLF+LiU/xEEsUAOPmqnzGKSU6 PY+C1Wxoog0CQ== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/9] drm: mxsfb: Simplify LCDIF clock handling Date: Mon, 28 Feb 2022 01:45:58 +0100 Message-Id: <20220228004605.367040-2-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The current clock handling in the LCDIF driver is a convoluted mess. Implement runtime PM ops which turn the clock ON and OFF and let the pm_runtime_get_sync()/pm_runtime_put_sync() calls in .atomic_enable and .atomic_disable callbacks turn the clock ON and OFF at the right time. This requires slight reordering in mxsfb_crtc_atomic_enable() and mxsfb_crtc_atomic_disable(), since all the register accesses must happen only with clock enabled and clock frequency configuration must happen with clock disabled. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner --- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 100 +++++++++++++++++------------- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 27 +++----- 2 files changed, 66 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index 375f26d4a4172..bb15e32d8a014 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -72,18 +72,6 @@ static const struct mxsfb_devdata mxsfb_devdata[] = { }, }; -void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb) -{ - if (mxsfb->clk_axi) - clk_prepare_enable(mxsfb->clk_axi); -} - -void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb) -{ - if (mxsfb->clk_axi) - clk_disable_unprepare(mxsfb->clk_axi); -} - static struct drm_framebuffer * mxsfb_fb_create(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) @@ -172,13 +160,9 @@ static void mxsfb_irq_disable(struct drm_device *drm) { struct mxsfb_drm_private *mxsfb = drm->dev_private; - mxsfb_enable_axi_clk(mxsfb); - /* Disable and clear VBLANK IRQ */ writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); - - mxsfb_disable_axi_clk(mxsfb); } static int mxsfb_irq_install(struct drm_device *dev, int irq) @@ -224,33 +208,33 @@ static int mxsfb_load(struct drm_device *drm, if (IS_ERR(mxsfb->clk)) return PTR_ERR(mxsfb->clk); - mxsfb->clk_axi = devm_clk_get(drm->dev, "axi"); + mxsfb->clk_axi = devm_clk_get_optional(drm->dev, "axi"); if (IS_ERR(mxsfb->clk_axi)) - mxsfb->clk_axi = NULL; + return PTR_ERR(mxsfb->clk_axi); - mxsfb->clk_disp_axi = devm_clk_get(drm->dev, "disp_axi"); + mxsfb->clk_disp_axi = devm_clk_get_optional(drm->dev, "disp_axi"); if (IS_ERR(mxsfb->clk_disp_axi)) - mxsfb->clk_disp_axi = NULL; + return PTR_ERR(mxsfb->clk_disp_axi); + + platform_set_drvdata(pdev, drm); ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); if (ret) return ret; - pm_runtime_enable(drm->dev); - /* Modeset init */ drm_mode_config_init(drm); ret = mxsfb_kms_init(mxsfb); if (ret < 0) { dev_err(drm->dev, "Failed to initialize KMS pipeline\n"); - goto err_vblank; + return ret; } ret = drm_vblank_init(drm, drm->mode_config.num_crtc); if (ret < 0) { dev_err(drm->dev, "Failed to initialise vblank\n"); - goto err_vblank; + return ret; } /* Start with vertical blanking interrupt reporting disabled. */ @@ -260,7 +244,7 @@ static int mxsfb_load(struct drm_device *drm, if (ret) { if (ret != -EPROBE_DEFER) dev_err(drm->dev, "Cannot connect bridge: %d\n", ret); - goto err_vblank; + return ret; } drm->mode_config.min_width = MXSFB_MIN_XRES; @@ -274,44 +258,37 @@ static int mxsfb_load(struct drm_device *drm, ret = platform_get_irq(pdev, 0); if (ret < 0) - goto err_vblank; + return ret; mxsfb->irq = ret; - pm_runtime_get_sync(drm->dev); ret = mxsfb_irq_install(drm, mxsfb->irq); - pm_runtime_put_sync(drm->dev); - if (ret < 0) { dev_err(drm->dev, "Failed to install IRQ handler\n"); - goto err_vblank; + return ret; } drm_kms_helper_poll_init(drm); - platform_set_drvdata(pdev, drm); - drm_helper_hpd_irq_event(drm); - return 0; - -err_vblank: - pm_runtime_disable(drm->dev); + pm_runtime_enable(drm->dev); - return ret; + return 0; } static void mxsfb_unload(struct drm_device *drm) { + pm_runtime_get_sync(drm->dev); + drm_kms_helper_poll_fini(drm); drm_mode_config_cleanup(drm); - pm_runtime_get_sync(drm->dev); mxsfb_irq_uninstall(drm); + pm_runtime_put_sync(drm->dev); + pm_runtime_disable(drm->dev); drm->dev_private = NULL; - - pm_runtime_disable(drm->dev); } DEFINE_DRM_GEM_CMA_FOPS(fops); @@ -388,23 +365,60 @@ static void mxsfb_shutdown(struct platform_device *pdev) drm_atomic_helper_shutdown(drm); } -#ifdef CONFIG_PM_SLEEP +static int mxsfb_rpm_suspend(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct mxsfb_drm_private *mxsfb = drm->dev_private; + + /* These clock supply the DISPLAY CLOCK Domain */ + clk_disable_unprepare(mxsfb->clk); + /* These clock supply the System Bus, AXI, Write Path, LFIFO */ + clk_disable_unprepare(mxsfb->clk_disp_axi); + /* These clock supply the Control Bus, APB, APBH Ctrl Registers */ + clk_disable_unprepare(mxsfb->clk_axi); + + return 0; +} + +static int mxsfb_rpm_resume(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct mxsfb_drm_private *mxsfb = drm->dev_private; + + /* These clock supply the Control Bus, APB, APBH Ctrl Registers */ + clk_prepare_enable(mxsfb->clk_axi); + /* These clock supply the System Bus, AXI, Write Path, LFIFO */ + clk_prepare_enable(mxsfb->clk_disp_axi); + /* These clock supply the DISPLAY CLOCK Domain */ + clk_prepare_enable(mxsfb->clk); + + return 0; +} + static int mxsfb_suspend(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); + int ret; - return drm_mode_config_helper_suspend(drm); + ret = drm_mode_config_helper_suspend(drm); + if (ret) + return ret; + + return mxsfb_rpm_suspend(dev); } static int mxsfb_resume(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); + mxsfb_rpm_resume(dev); + return drm_mode_config_helper_resume(drm); } -#endif static const struct dev_pm_ops mxsfb_pm_ops = { + .runtime_suspend = mxsfb_rpm_suspend, + .runtime_resume = mxsfb_rpm_resume, SET_SYSTEM_SLEEP_PM_OPS(mxsfb_suspend, mxsfb_resume) }; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 4cfb6c0016799..657b6afbbf1f9 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -100,10 +100,6 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; - if (mxsfb->clk_disp_axi) - clk_prepare_enable(mxsfb->clk_disp_axi); - clk_prepare_enable(mxsfb->clk); - /* Increase number of outstanding requests on all supported IPs */ if (mxsfb->devdata->has_ctrl2) { reg = readl(mxsfb->base + LCDC_V4_CTRL2); @@ -168,10 +164,6 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) reg = readl(mxsfb->base + LCDC_VDCTRL4); reg &= ~VDCTRL4_SYNC_SIGNALS_ON; writel(reg, mxsfb->base + LCDC_VDCTRL4); - - clk_disable_unprepare(mxsfb->clk); - if (mxsfb->clk_disp_axi) - clk_disable_unprepare(mxsfb->clk_disp_axi); } /* @@ -250,8 +242,6 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, mxsfb_set_formats(mxsfb, bus_format); - clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); - if (mxsfb->bridge && mxsfb->bridge->timings) bus_flags = mxsfb->bridge->timings->input_bus_flags; @@ -346,16 +336,12 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); + struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; struct drm_bridge_state *bridge_state; struct drm_device *drm = mxsfb->drm; u32 bus_format = 0; dma_addr_t paddr; - pm_runtime_get_sync(drm->dev); - mxsfb_enable_axi_clk(mxsfb); - - drm_crtc_vblank_on(crtc); - /* If there is a bridge attached to the LCDIF, use its bus format */ if (mxsfb->bridge) { bridge_state = @@ -382,6 +368,10 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, if (!bus_format) bus_format = MEDIA_BUS_FMT_RGB888_1X24; + clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); + + pm_runtime_get_sync(drm->dev); + mxsfb_crtc_mode_set_nofb(mxsfb, bus_format); /* Write cur_buf as well to avoid an initial corrupt frame */ @@ -392,6 +382,8 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, } mxsfb_enable_controller(mxsfb); + + drm_crtc_vblank_on(crtc); } static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, @@ -401,6 +393,8 @@ static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_device *drm = mxsfb->drm; struct drm_pending_vblank_event *event; + drm_crtc_vblank_off(crtc); + mxsfb_disable_controller(mxsfb); spin_lock_irq(&drm->event_lock); @@ -411,9 +405,6 @@ static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, } spin_unlock_irq(&drm->event_lock); - drm_crtc_vblank_off(crtc); - - mxsfb_disable_axi_clk(mxsfb); pm_runtime_put_sync(drm->dev); } From patchwork Mon Feb 28 00:45:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABFC0C433EF for ; Mon, 28 Feb 2022 00:46:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A49FD10E229; Mon, 28 Feb 2022 00:46:48 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id BACE210E21C for ; Mon, 28 Feb 2022 00:46:43 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id F2BE783A78; Mon, 28 Feb 2022 01:46:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009202; bh=lqFSO4QFcc91D5/Q9J1sWwC4sikFfHQ7hvvSYXappVc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xdC9yEqBGrrcexqbz5Z1EP5JKNGat7S2H+Y9ba7Oxj02jgrA1ubJwwaC6YA6IcxPD 5sxgbbiklmd1edwanc8GjD8K2NFi+PSUsQQijqptCJGneF2JPDWCQa0M9RBg1cA/2V JaiCOA2ApM4vbVjVIW6QHddL4ix+CutoZPRqErMd9QRt3DNRZBlVqfcDEMaNC1H9Th AaGQ6+to92AuQGvgPylNnBqxZ1mb+4uOVSvfM25jhRw9JRyWNrQ6hCawUI794QNVDr QWXL/svy2pnowm9pJZEEBB1NTMPI4SxSNVRQbA7Z36GGO6h8RqpfLKimOEf0ehxKi8 jpOTIfxTp5Few== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 3/9] drm: mxsfb: Simplify LCDIF IRQ handling Date: Mon, 28 Feb 2022 01:45:59 +0100 Message-Id: <20220228004605.367040-3-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The call to drm_crtc_vblank_off(&lcdif->crtc); disables IRQ generation from the LCDIF block already and this is called in mxsfb_load() before request_irq(), so explicitly disabling IRQ using custom function like mxsfb_irq_disable() is not needed, remove it. The request_irq() call would return -ENOTCONN if IRQ is IRQ_NOTCONNECTED already, so remove the unnecessary check. Finally, remove both mxsfb_irq_install() and mxsfb_irq_uninstall() as well, since they are no longer useful. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner --- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 38 +++++++------------------------ 1 file changed, 8 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index bb15e32d8a014..11298df50917c 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -156,33 +156,6 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data) return IRQ_HANDLED; } -static void mxsfb_irq_disable(struct drm_device *drm) -{ - struct mxsfb_drm_private *mxsfb = drm->dev_private; - - /* Disable and clear VBLANK IRQ */ - writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); - writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); -} - -static int mxsfb_irq_install(struct drm_device *dev, int irq) -{ - if (irq == IRQ_NOTCONNECTED) - return -ENOTCONN; - - mxsfb_irq_disable(dev); - - return request_irq(irq, mxsfb_irq_handler, 0, dev->driver->name, dev); -} - -static void mxsfb_irq_uninstall(struct drm_device *dev) -{ - struct mxsfb_drm_private *mxsfb = dev->dev_private; - - mxsfb_irq_disable(dev); - free_irq(mxsfb->irq, dev); -} - static int mxsfb_load(struct drm_device *drm, const struct mxsfb_devdata *devdata) { @@ -261,7 +234,8 @@ static int mxsfb_load(struct drm_device *drm, return ret; mxsfb->irq = ret; - ret = mxsfb_irq_install(drm, mxsfb->irq); + ret = request_irq(mxsfb->irq, mxsfb_irq_handler, 0, + drm->driver->name, drm); if (ret < 0) { dev_err(drm->dev, "Failed to install IRQ handler\n"); return ret; @@ -278,16 +252,20 @@ static int mxsfb_load(struct drm_device *drm, static void mxsfb_unload(struct drm_device *drm) { + struct mxsfb_drm_private *mxsfb = drm->dev_private; + pm_runtime_get_sync(drm->dev); + drm_crtc_vblank_off(&mxsfb->crtc); + drm_kms_helper_poll_fini(drm); drm_mode_config_cleanup(drm); - mxsfb_irq_uninstall(drm); - pm_runtime_put_sync(drm->dev); pm_runtime_disable(drm->dev); + free_irq(mxsfb->irq, drm->dev); + drm->dev_private = NULL; } From patchwork Mon Feb 28 00:46:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2C18C433F5 for ; Mon, 28 Feb 2022 00:47:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A9A5810E243; Mon, 28 Feb 2022 00:46:57 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5492310E21C for ; Mon, 28 Feb 2022 00:46:44 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 7CC6583BAF; Mon, 28 Feb 2022 01:46:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009202; bh=ftN8UVqoY/cnU4wjQaFw84PDvBEMuCcLLcJvuP4CPJY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U9XAbPIjgw+QvUTxXZXH81MfQOq00udZMONWL5qIpGzlXijNrXuuWjhrFW2iVR/62 rrN/WwNgrBVHpa/pG4Fpef8nwMwiu0FobPf+RBr8ROMYUYVyEkjU/ORoKWpohIm+Ip XALm4DAYSUS/Y2taA+s/5MIsObyvGrjP3b7K1jauDT7oVOLSl0F9yBbS3aVWpEdU+7 CUhvxvZ51Dq1uxtYI3+FBBZTrH4ooebOxyMuKNwjpqkwApMSIPP11wu4XWWYfb1AEU h2y8AeVb9caVHFcdYBd5AJHskRpi8qxtdhhGb9lh6TzjdRk0VsjEjc+WeKy/+oRHZf a8IKCmRxfvnFQ== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 4/9] drm: mxsfb: Wrap FIFO reset and comments into mxsfb_reset_block() Date: Mon, 28 Feb 2022 01:46:00 +0100 Message-Id: <20220228004605.367040-4-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Wrap FIFO reset and comments into mxsfb_reset_block(), this is a clean up. No functional change. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner --- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 36 +++++++++++++++++-------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 657b6afbbf1f9..015b289d93a3c 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -183,6 +183,12 @@ static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) { int ret; + /* + * It seems, you can't re-program the controller if it is still + * running. This may lead to shifted pictures (FIFO issue?), so + * first stop the controller and drain its FIFOs. + */ + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); if (ret) return ret; @@ -193,7 +199,20 @@ static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) if (ret) return ret; - return clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE); + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE); + if (ret) + return ret; + + /* Clear the FIFOs */ + writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); + readl(mxsfb->base + LCDC_CTRL1); + writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); + readl(mxsfb->base + LCDC_CTRL1); + + if (mxsfb->devdata->has_overlay) + writel(0, mxsfb->base + LCDC_AS_CTRL); + + return 0; } static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane) @@ -220,26 +239,11 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, u32 vdctrl0, vsync_pulse_len, hsync_pulse_len; int err; - /* - * It seems, you can't re-program the controller if it is still - * running. This may lead to shifted pictures (FIFO issue?), so - * first stop the controller and drain its FIFOs. - */ - /* Mandatory eLCDIF reset as per the Reference Manual */ err = mxsfb_reset_block(mxsfb); if (err) return; - /* Clear the FIFOs */ - writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); - readl(mxsfb->base + LCDC_CTRL1); - writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); - readl(mxsfb->base + LCDC_CTRL1); - - if (mxsfb->devdata->has_overlay) - writel(0, mxsfb->base + LCDC_AS_CTRL); - mxsfb_set_formats(mxsfb, bus_format); if (mxsfb->bridge && mxsfb->bridge->timings) From patchwork Mon Feb 28 00:46:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F637C433FE for ; Mon, 28 Feb 2022 00:47:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D281210E24B; Mon, 28 Feb 2022 00:46:57 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id B908510E229 for ; Mon, 28 Feb 2022 00:46:44 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 0E81383BCC; Mon, 28 Feb 2022 01:46:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009203; bh=tFc56DTs04ZcN3UQAj7XNofI/G4evJ/buPBTzXCPkqQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I+Qrg/Czkx+HwY7vOp2Nj0wMpVKXvglPDLbtYJiydPKkEMMngu2P+Wdx+H9wVxBsH /g8Q0dXfUMsDs+vv7RFZI8D9VjJPW/hZB64CE7LL1/fz3IRkywnPU0jHVdU/qdhuUA 6pNRcFqlfW9b/qLf/uwxPUZDfv4gD07+C8ucMYQ4Csfqldukk7jEdyGQai6aZZ0+zl c2VG932LZMrBlxFrwqSvqpQUwiM0HftR7GVKiQSJOqfaVIi28qmiMGmueXwLu3OMh3 FUcEKaGciT7IbcYXRd8KWoqsruGBVFVC3Imonv9RzuLzpthoZQvw89bu4AxmafjtJU 9B+tY21FrCqlg== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 5/9] drm: mxsfb: Move mxsfb_get_fb_paddr() away from register IO functions Date: Mon, 28 Feb 2022 01:46:01 +0100 Message-Id: <20220228004605.367040-5-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Move mxsfb_get_fb_paddr() out of the way, away from register IO functions. This is a clean up. No functional change. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner --- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 015b289d93a3c..7b0abd0472aae 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -43,6 +43,21 @@ static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val) mxsfb->devdata->hs_wdth_shift; } +static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane) +{ + struct drm_framebuffer *fb = plane->state->fb; + struct drm_gem_cma_object *gem; + + if (!fb) + return 0; + + gem = drm_fb_cma_get_gem_obj(fb, 0); + if (!gem) + return 0; + + return gem->paddr; +} + /* * Setup the MXSFB registers for decoding the pixels out of the framebuffer and * outputting them on the bus. @@ -215,21 +230,6 @@ static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) return 0; } -static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane) -{ - struct drm_framebuffer *fb = plane->state->fb; - struct drm_gem_cma_object *gem; - - if (!fb) - return 0; - - gem = drm_fb_cma_get_gem_obj(fb, 0); - if (!gem) - return 0; - - return gem->paddr; -} - static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, const u32 bus_format) { From patchwork Mon Feb 28 00:46:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E7CFC433EF for ; Mon, 28 Feb 2022 00:46:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A21F10E23E; Mon, 28 Feb 2022 00:46:57 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id 346D510E21C for ; Mon, 28 Feb 2022 00:46:45 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 918DB83BCF; Mon, 28 Feb 2022 01:46:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009204; bh=w/kQJbaxl7zsFUdYYusKQEtKbS0JRe0mS4rn5W8Ovno=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Qva6gku5vFo9TWpuHJ8OjUJbL8UFXwFq6QR0ftuZSWGWFfm/Y7bMRuZBOQjL3yfmA 47d/bxqmZ8Vczyhq18gvjJVr9utRORYBcKSkfrPksFOTTri8mjqlu12/SPsWYc88J7 yOEM34kL5i8Et5flxoCjmeY2xkNVy3xrbj8msfdKUm3nApR53eBliVPfHj9ysQrsxr l6KXTMj8BCC7Vhl20/RTx4eM97lbnO0WhIs/5xSQsWhKrDgpghQa24s8RFAo/vh4oW hhN/m4WxR7GJJkX9H86zm16MjfqhwYkSE1+ZbOovMGf+fwi3ceAyFOg94cOeJej8ih 0LjeDl7BlPeMg== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 6/9] drm: mxsfb: Factor out mxsfb_set_mode() Date: Mon, 28 Feb 2022 01:46:02 +0100 Message-Id: <20220228004605.367040-6-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Pull mode registers programming from mxsfb_enable_controller() into dedicated function mxsfb_set_mode(). This is a clean up. No functional change. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner --- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 96 +++++++++++++++++-------------- 1 file changed, 52 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 7b0abd0472aae..14f5cc590a51b 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -111,6 +111,57 @@ static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb, writel(ctrl, mxsfb->base + LCDC_CTRL); } +static void mxsfb_set_mode(struct mxsfb_drm_private *mxsfb, u32 bus_flags) +{ + struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; + u32 vdctrl0, vsync_pulse_len, hsync_pulse_len; + + writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) | + TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay), + mxsfb->base + mxsfb->devdata->transfer_count); + + vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start; + + vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* Always in DOTCLOCK mode */ + VDCTRL0_VSYNC_PERIOD_UNIT | + VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len); + if (m->flags & DRM_MODE_FLAG_PHSYNC) + vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; + if (m->flags & DRM_MODE_FLAG_PVSYNC) + vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; + /* Make sure Data Enable is high active by default */ + if (!(bus_flags & DRM_BUS_FLAG_DE_LOW)) + vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; + /* + * DRM_BUS_FLAG_PIXDATA_DRIVE_ defines are controller centric, + * controllers VDCTRL0_DOTCLK is display centric. + * Drive on positive edge -> display samples on falling edge + * DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING + */ + if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) + vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING; + + writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0); + + /* Frame length in lines. */ + writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1); + + /* Line length in units of clocks or pixels. */ + hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start; + writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) | + VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal), + mxsfb->base + LCDC_VDCTRL2); + + writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) | + SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start), + mxsfb->base + LCDC_VDCTRL3); + + writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay), + mxsfb->base + LCDC_VDCTRL4); + +} + static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; @@ -236,7 +287,6 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, struct drm_device *drm = mxsfb->crtc.dev; struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; u32 bus_flags = mxsfb->connector->display_info.bus_flags; - u32 vdctrl0, vsync_pulse_len, hsync_pulse_len; int err; /* Mandatory eLCDIF reset as per the Reference Manual */ @@ -256,49 +306,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, bus_flags); DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); - writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) | - TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay), - mxsfb->base + mxsfb->devdata->transfer_count); - - vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start; - - vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* Always in DOTCLOCK mode */ - VDCTRL0_VSYNC_PERIOD_UNIT | - VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | - VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len); - if (m->flags & DRM_MODE_FLAG_PHSYNC) - vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; - if (m->flags & DRM_MODE_FLAG_PVSYNC) - vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; - /* Make sure Data Enable is high active by default */ - if (!(bus_flags & DRM_BUS_FLAG_DE_LOW)) - vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; - /* - * DRM_BUS_FLAG_PIXDATA_DRIVE_ defines are controller centric, - * controllers VDCTRL0_DOTCLK is display centric. - * Drive on positive edge -> display samples on falling edge - * DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING - */ - if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) - vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING; - - writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0); - - /* Frame length in lines. */ - writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1); - - /* Line length in units of clocks or pixels. */ - hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start; - writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) | - VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal), - mxsfb->base + LCDC_VDCTRL2); - - writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) | - SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start), - mxsfb->base + LCDC_VDCTRL3); - - writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay), - mxsfb->base + LCDC_VDCTRL4); + mxsfb_set_mode(mxsfb, bus_flags); } static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, From patchwork Mon Feb 28 00:46:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 550F6C433F5 for ; Mon, 28 Feb 2022 00:47:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55E0210E24F; Mon, 28 Feb 2022 00:46:58 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id B393D10E21C for ; Mon, 28 Feb 2022 00:46:45 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 1822D83BD9; Mon, 28 Feb 2022 01:46:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009204; bh=GbZitkwwV4gg2dbtlotZDq9UYHgGcHW/Te/2YlotWO8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fJ38m1bj58kfMKlZvJ0ptBzrqRtljao6ZopBuTQZ75KtKgQ6UVU95nPQCMbWIMuzy jV9kUV3tPgOv/TPUtzpksvG/87/Mo0j95q86WKZCTaqNGlYqzPH8qqu56aHKoWHSvz VhTYe/TkqVxGiiT5VUAb89vUiW3T5sKA1Fx9ytT8P0sk56u9XEiPS9OXB/Ue9g8cXr ckpPc8RZ8WctzQfeUwnvTVuxsd3UvXI09M0b732k4Yj0CKHkptFWOho3PUoBeFvI6D EQ6I5rZfh570BlmR96A893jEJHjcfkhHP1hTrR4KBrUyqeRgCi5O9kcHeE7XKU/d3L LetcFoCLVKfkg== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 7/9] drm: mxsfb: Reorder mxsfb_crtc_mode_set_nofb() Date: Mon, 28 Feb 2022 01:46:03 +0100 Message-Id: <20220228004605.367040-7-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Reorder mxsfb_crtc_mode_set_nofb() such that all functions which perform register IO are called from one single location in this function. This is a clean up. No functional change. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner --- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 14f5cc590a51b..497603964add8 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -289,13 +289,6 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, u32 bus_flags = mxsfb->connector->display_info.bus_flags; int err; - /* Mandatory eLCDIF reset as per the Reference Manual */ - err = mxsfb_reset_block(mxsfb); - if (err) - return; - - mxsfb_set_formats(mxsfb, bus_format); - if (mxsfb->bridge && mxsfb->bridge->timings) bus_flags = mxsfb->bridge->timings->input_bus_flags; @@ -306,6 +299,13 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, bus_flags); DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); + /* Mandatory eLCDIF reset as per the Reference Manual */ + err = mxsfb_reset_block(mxsfb); + if (err) + return; + + mxsfb_set_formats(mxsfb, bus_format); + mxsfb_set_mode(mxsfb, bus_flags); } From patchwork Mon Feb 28 00:46:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1E8DC433F5 for ; Mon, 28 Feb 2022 00:47:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 726C210E241; Mon, 28 Feb 2022 00:46:57 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F64210E21C for ; Mon, 28 Feb 2022 00:46:46 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 992D483A45; Mon, 28 Feb 2022 01:46:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009205; bh=3dWUVjffHIT0nMugDyFD6N05sIK2IfE9q4aWK7wKjxM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EhhxAH9mMKSw7xC36f/Pdzhs3ukc2ZPvICQvWeArh6WLnfXPwhBE0+tQg9OCWJpIK FHH9MyxB3E2YeRd4cLfADnmX5pmHmt3u7fNSCHkqVYCw78HM/efjBFWSbAQHmn+3vV R7bnLr9YHKnZSVCNnmB3mNAAps6O7TRaCNPBntaHDtJ/JZzs5R/Hq3HdfOZih/6lwH izSrwxvpflnB1EYqUX2dnRUTZMeMDxBsrWJW1OiWXkYOyJFw+tJmg8g/DlbMEAuZhT AQ4HCPOyz56xVM5uxKLnXRkDaNrKqIWkyev0XZAeZqxb7AhJOudnKEBtsNPz07iQdU 2gnWzzlJTZpEQ== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 8/9] drm: mxsfb: Factor out mxsfb_update_buffer() Date: Mon, 28 Feb 2022 01:46:04 +0100 Message-Id: <20220228004605.367040-8-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Pull functionality responsible for programming framebuffer address into the controller into dedicated function mxsfb_update_buffer(). This is a clean up. No functional change. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner --- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 497603964add8..4baa3db1f3d10 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -58,6 +58,22 @@ static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane) return gem->paddr; } +static void +mxsfb_update_buffer(struct mxsfb_drm_private *mxsfb, struct drm_plane *plane, + bool both) +{ + dma_addr_t paddr; + + paddr = mxsfb_get_fb_paddr(plane); + if (!paddr) + return; + + if (both) + writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf); + + writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); +} + /* * Setup the MXSFB registers for decoding the pixels out of the framebuffer and * outputting them on the bus. @@ -352,7 +368,6 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_bridge_state *bridge_state; struct drm_device *drm = mxsfb->drm; u32 bus_format = 0; - dma_addr_t paddr; /* If there is a bridge attached to the LCDIF, use its bus format */ if (mxsfb->bridge) { @@ -387,11 +402,7 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, mxsfb_crtc_mode_set_nofb(mxsfb, bus_format); /* Write cur_buf as well to avoid an initial corrupt frame */ - paddr = mxsfb_get_fb_paddr(crtc->primary); - if (paddr) { - writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf); - writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); - } + mxsfb_update_buffer(mxsfb, crtc->primary, true); mxsfb_enable_controller(mxsfb); @@ -491,11 +502,8 @@ static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); - dma_addr_t paddr; - paddr = mxsfb_get_fb_paddr(plane); - if (paddr) - writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); + mxsfb_update_buffer(mxsfb, plane, false); } static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane, From patchwork Mon Feb 28 00:46:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12762231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A195C433F5 for ; Mon, 28 Feb 2022 00:46:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9720010E21C; Mon, 28 Feb 2022 00:46:48 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA74B10E21C for ; Mon, 28 Feb 2022 00:46:46 +0000 (UTC) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 20D1783A78; Mon, 28 Feb 2022 01:46:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1646009205; bh=IGUxpSgDL0C6Q5hep5Aonqof20YU8Tc1I1E14rMwkPg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Aobot1BH+BqAbz/DPHfaoY2ssu2yfQTNNfPU8xYER/9vHXgvD2R7OUF+07TzGFN60 1DcIZklgpwHemeyhLxjYPbQp5fjgYeDpwTHmjrDYfFyivgAjprdTX7YBE1PsG2m8Oo +qHIFUnXjUbgTXa1H5V38Y2/6KKCD1P7a+nAS4wcUUVhVNzwew/6tdASLWy/hccnp8 8NVUjIh3VIRLL2jo08Ea9WSRjGYAsno3qxNjzxt0vitZB8nwRNK0ksToCTtLMs/GlI lD5STJP/8jDwGEIlZpJoxJhF7xUTZxbM9R8oqXYjhbwzvL31JDuq0pvO93F5aewI1Z vDSmlS5b3FETA== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 9/9] drm: mxsfb: Add support for i.MX8MP LCDIF variant Date: Mon, 28 Feb 2022 01:46:05 +0100 Message-Id: <20220228004605.367040-9-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228004605.367040-1-marex@denx.de> References: <20220228004605.367040-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peng Fan , Alexander Stein , Laurent Pinchart , Sam Ravnborg , Robby Cai Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for i.MX8MP LCDIF variant. This is called LCDIFv3 and is completely different from the LCDIFv3 found in i.MX23 in that it has a completely scrambled register layout compared to all previous LCDIF variants. The new LCDIFv3 also supports 36bit address space. However, except for the complete bit reshuffling, this is still LCDIF and it still works like one, the boilerplate code is also the same, hence it is part of this driver. This is probably still a bit better than a separate driver with a lot of duplicated code. Signed-off-by: Marek Vasut Cc: Alexander Stein Cc: Laurent Pinchart Cc: Lucas Stach Cc: Peng Fan Cc: Robby Cai Cc: Sam Ravnborg Cc: Stefan Agner Reported-by: kernel test robot --- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 34 ++++- drivers/gpu/drm/mxsfb/mxsfb_drv.h | 1 + drivers/gpu/drm/mxsfb/mxsfb_kms.c | 219 +++++++++++++++++++++++++++-- drivers/gpu/drm/mxsfb/mxsfb_regs.h | 136 ++++++++++++++++++ 4 files changed, 374 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index 11298df50917c..7fd7fd1496f7d 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -40,6 +40,8 @@ enum mxsfb_devtype { * i.MX family number as the version. */ MXSFB_V6, + /* Starting at i.MX8MP the register layout is scrambled. */ + MXSFB_V8, }; static const struct mxsfb_devdata mxsfb_devdata[] = { @@ -51,6 +53,7 @@ static const struct mxsfb_devdata mxsfb_devdata[] = { .hs_wdth_shift = 24, .has_overlay = false, .has_ctrl2 = false, + .has_regsv8 = false, }, [MXSFB_V4] = { .transfer_count = LCDC_V4_TRANSFER_COUNT, @@ -60,6 +63,7 @@ static const struct mxsfb_devdata mxsfb_devdata[] = { .hs_wdth_shift = 18, .has_overlay = false, .has_ctrl2 = true, + .has_regsv8 = false, }, [MXSFB_V6] = { .transfer_count = LCDC_V4_TRANSFER_COUNT, @@ -69,6 +73,13 @@ static const struct mxsfb_devdata mxsfb_devdata[] = { .hs_wdth_shift = 18, .has_overlay = true, .has_ctrl2 = true, + .has_regsv8 = false, + }, + [MXSFB_V8] = { + /* Old register layout details do not apply here. */ + .has_overlay = false, + .has_ctrl2 = false, + .has_regsv8 = true, }, }; @@ -156,6 +167,22 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data) return IRQ_HANDLED; } +static irqreturn_t mxsfb_v8_irq_handler(int irq, void *data) +{ + struct drm_device *drm = data; + struct mxsfb_drm_private *mxsfb = drm->dev_private; + u32 reg; + + reg = readl(mxsfb->base + LCDC_V8_INT_STATUS_D0); + + if (reg & INT_STATUS_D0_VS_BLANK) + drm_crtc_handle_vblank(&mxsfb->crtc); + + writel(INT_STATUS_D0_VS_BLANK, mxsfb->base + LCDC_V8_INT_STATUS_D0); + + return IRQ_HANDLED; +} + static int mxsfb_load(struct drm_device *drm, const struct mxsfb_devdata *devdata) { @@ -191,7 +218,8 @@ static int mxsfb_load(struct drm_device *drm, platform_set_drvdata(pdev, drm); - ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask_and_coherent(drm->dev, + DMA_BIT_MASK(devdata->has_regsv8 ? 36 : 32)); if (ret) return ret; @@ -234,7 +262,8 @@ static int mxsfb_load(struct drm_device *drm, return ret; mxsfb->irq = ret; - ret = request_irq(mxsfb->irq, mxsfb_irq_handler, 0, + ret = request_irq(mxsfb->irq, devdata->has_regsv8 ? + mxsfb_v8_irq_handler : mxsfb_irq_handler, 0, drm->driver->name, drm); if (ret < 0) { dev_err(drm->dev, "Failed to install IRQ handler\n"); @@ -286,6 +315,7 @@ static const struct of_device_id mxsfb_dt_ids[] = { { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devdata[MXSFB_V3], }, { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devdata[MXSFB_V4], }, { .compatible = "fsl,imx6sx-lcdif", .data = &mxsfb_devdata[MXSFB_V6], }, + { .compatible = "fsl,imx8mp-lcdif", .data = &mxsfb_devdata[MXSFB_V8], }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxsfb_dt_ids); diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h b/drivers/gpu/drm/mxsfb/mxsfb_drv.h index ddb5b0417a82c..74c5e6013ca43 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h @@ -23,6 +23,7 @@ struct mxsfb_devdata { unsigned int hs_wdth_shift; bool has_overlay; bool has_ctrl2; + bool has_regsv8; }; struct mxsfb_drm_private { diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 4baa3db1f3d10..52df73982ccc1 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -74,6 +74,26 @@ mxsfb_update_buffer(struct mxsfb_drm_private *mxsfb, struct drm_plane *plane, writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); } +static void +mxsfb_v8_update_buffer(struct mxsfb_drm_private *mxsfb, struct drm_plane *plane) +{ + dma_addr_t paddr; + u32 reg; + + paddr = mxsfb_get_fb_paddr(plane); + if (!paddr) + return; + + writel(lower_32_bits(paddr), + mxsfb->base + LCDC_V8_CTRLDESCL_LOW0_4); + writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)), + mxsfb->base + LCDC_V8_CTRLDESCL_HIGH0_4); + + reg = readl(mxsfb->base + LCDC_V8_CTRLDESCL0_5); + reg |= CTRLDESCL0_5_SHADOW_LOAD_EN; + writel(reg, mxsfb->base + LCDC_V8_CTRLDESCL0_5); +} + /* * Setup the MXSFB registers for decoding the pixels out of the framebuffer and * outputting them on the bus. @@ -127,6 +147,57 @@ static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb, writel(ctrl, mxsfb->base + LCDC_CTRL); } +static void mxsfb_v8_set_formats(struct mxsfb_drm_private *mxsfb, + const u32 bus_format) +{ + struct drm_device *drm = mxsfb->drm; + const u32 format = mxsfb->crtc.primary->state->fb->format->format; + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB565_1X16: + writel(DISP_PARA_LINE_PATTERN_RGB565, + mxsfb->base + LCDC_V8_DISP_PARA); + break; + case MEDIA_BUS_FMT_RGB888_1X24: + writel(DISP_PARA_LINE_PATTERN_RGB888, + mxsfb->base + LCDC_V8_DISP_PARA); + break; + default: + dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format); + break; + } + + switch (format) { + case DRM_FORMAT_RGB565: + writel(CTRLDESCL0_5_BPP_16_RGB565, + mxsfb->base + LCDC_V8_CTRLDESCL0_5); + break; + case DRM_FORMAT_RGB888: + writel(CTRLDESCL0_5_BPP_24_RGB888, + mxsfb->base + LCDC_V8_CTRLDESCL0_5); + break; + case DRM_FORMAT_XRGB1555: + writel(CTRLDESCL0_5_BPP_16_ARGB1555, + mxsfb->base + LCDC_V8_CTRLDESCL0_5); + break; + case DRM_FORMAT_XRGB4444: + writel(CTRLDESCL0_5_BPP_16_ARGB4444, + mxsfb->base + LCDC_V8_CTRLDESCL0_5); + break; + case DRM_FORMAT_XBGR8888: + writel(CTRLDESCL0_5_BPP_32_ABGR8888, + mxsfb->base + LCDC_V8_CTRLDESCL0_5); + break; + case DRM_FORMAT_XRGB8888: + writel(CTRLDESCL0_5_BPP_32_ARGB8888, + mxsfb->base + LCDC_V8_CTRLDESCL0_5); + break; + default: + dev_err(drm->dev, "Unknown pixel format 0x%x\n", format); + break; + } +} + static void mxsfb_set_mode(struct mxsfb_drm_private *mxsfb, u32 bus_flags) { struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; @@ -178,6 +249,47 @@ static void mxsfb_set_mode(struct mxsfb_drm_private *mxsfb, u32 bus_flags) } +static void mxsfb_v8_set_mode(struct mxsfb_drm_private *mxsfb, u32 bus_flags) +{ + struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; + u32 ctrl; + + if (m->flags & DRM_MODE_FLAG_PHSYNC) + ctrl |= CTRL_INV_HS; + if (m->flags & DRM_MODE_FLAG_PVSYNC) + ctrl |= CTRL_INV_VS; + /* Make sure Data Enable is high active by default */ + if (!(bus_flags & DRM_BUS_FLAG_DE_LOW)) + ctrl |= CTRL_INV_DE; + if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) + ctrl |= CTRL_INV_PXCK; + + writel(ctrl, mxsfb->base + LCDC_CTRL); + + writel(DISP_SIZE_DELTA_Y(m->crtc_vdisplay) | + DISP_SIZE_DELTA_X(m->crtc_hdisplay), + mxsfb->base + LCDC_V8_DISP_SIZE); + + writel(HSYN_PARA_BP_H(m->htotal - m->hsync_end) | + HSYN_PARA_FP_H(m->hsync_start - m->hdisplay), + mxsfb->base + LCDC_V8_HSYN_PARA); + + writel(VSYN_PARA_BP_V(m->vtotal - m->vsync_end) | + VSYN_PARA_FP_V(m->vsync_start - m->vdisplay), + mxsfb->base + LCDC_V8_VSYN_PARA); + + writel(VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) | + VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start), + mxsfb->base + LCDC_V8_VSYN_HSYN_WIDTH); + + writel(CTRLDESCL0_1_HEIGHT(m->crtc_vdisplay) | + CTRLDESCL0_1_WIDTH(m->crtc_hdisplay), + mxsfb->base + LCDC_V8_CTRLDESCL0_1); + + writel(CTRLDESCL0_3_PITCH(mxsfb->crtc.primary->state->fb->pitches[0]), + mxsfb->base + LCDC_V8_CTRLDESCL0_3); +} + static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; @@ -230,6 +342,19 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); } +static void mxsfb_v8_enable_controller(struct mxsfb_drm_private *mxsfb) +{ + u32 reg; + + reg = readl(mxsfb->base + LCDC_V8_DISP_PARA); + reg |= DISP_PARA_DISP_ON; + writel(reg, mxsfb->base + LCDC_V8_DISP_PARA); + + reg = readl(mxsfb->base + LCDC_V8_CTRLDESCL0_5); + reg |= CTRLDESCL0_5_EN; + writel(reg, mxsfb->base + LCDC_V8_CTRLDESCL0_5); +} + static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; @@ -248,6 +373,19 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) writel(reg, mxsfb->base + LCDC_VDCTRL4); } +static void mxsfb_v8_disable_controller(struct mxsfb_drm_private *mxsfb) +{ + u32 reg; + + reg = readl(mxsfb->base + LCDC_V8_CTRLDESCL0_5); + reg &= ~CTRLDESCL0_5_EN; + writel(reg, mxsfb->base + LCDC_V8_CTRLDESCL0_5); + + reg = readl(mxsfb->base + LCDC_V8_DISP_PARA); + reg &= ~DISP_PARA_DISP_ON; + writel(reg, mxsfb->base + LCDC_V8_DISP_PARA); +} + /* * Clear the bit and poll it cleared. This is usually called with * a reset address and mask being either SFTRST(bit 31) or CLKGATE @@ -297,6 +435,26 @@ static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) return 0; } +static int mxsfb_v8_reset_block(struct mxsfb_drm_private *mxsfb) +{ + u32 reg; + int ret; + + writel(CTRL_SW_RESET, mxsfb->base + LCDC_CTRL + REG_SET); + + ret = readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, + (reg & CTRL_SW_RESET), 0, + RESET_TIMEOUT); + if (ret) + return ret; + + writel(CTRL_SW_RESET, mxsfb->base + LCDC_CTRL + REG_CLR); + + return readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, + !(reg & CTRL_SW_RESET), 0, + RESET_TIMEOUT); +} + static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, const u32 bus_format) { @@ -315,14 +473,25 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, bus_flags); DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); - /* Mandatory eLCDIF reset as per the Reference Manual */ - err = mxsfb_reset_block(mxsfb); - if (err) - return; + if (mxsfb->devdata->has_regsv8) { + /* Mandatory eLCDIF reset as per the Reference Manual */ + err = mxsfb_v8_reset_block(mxsfb); + if (err) + return; + + mxsfb_v8_set_formats(mxsfb, bus_format); - mxsfb_set_formats(mxsfb, bus_format); + mxsfb_v8_set_mode(mxsfb, bus_flags); + } else { + /* Mandatory eLCDIF reset as per the Reference Manual */ + err = mxsfb_reset_block(mxsfb); + if (err) + return; - mxsfb_set_mode(mxsfb, bus_flags); + mxsfb_set_formats(mxsfb, bus_format); + + mxsfb_set_mode(mxsfb, bus_flags); + } } static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, @@ -402,9 +571,15 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, mxsfb_crtc_mode_set_nofb(mxsfb, bus_format); /* Write cur_buf as well to avoid an initial corrupt frame */ - mxsfb_update_buffer(mxsfb, crtc->primary, true); + if (mxsfb->devdata->has_regsv8) { + mxsfb_v8_update_buffer(mxsfb, crtc->primary); - mxsfb_enable_controller(mxsfb); + mxsfb_v8_enable_controller(mxsfb); + } else { + mxsfb_update_buffer(mxsfb, crtc->primary, true); + + mxsfb_enable_controller(mxsfb); + } drm_crtc_vblank_on(crtc); } @@ -418,7 +593,10 @@ static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, drm_crtc_vblank_off(crtc); - mxsfb_disable_controller(mxsfb); + if (mxsfb->devdata->has_regsv8) + mxsfb_v8_disable_controller(mxsfb); + else + mxsfb_disable_controller(mxsfb); spin_lock_irq(&drm->event_lock); event = crtc->state->event; @@ -436,8 +614,13 @@ static int mxsfb_crtc_enable_vblank(struct drm_crtc *crtc) struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); /* Clear and enable VBLANK IRQ */ - writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); - writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); + if (mxsfb->devdata->has_regsv8) { + writel(INT_STATUS_D0_VS_BLANK, mxsfb->base + LCDC_V8_INT_STATUS_D0); + writel(INT_ENABLE_D0_VS_BLANK_EN, mxsfb->base + LCDC_V8_INT_ENABLE_D0); + } else { + writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); + writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); + } return 0; } @@ -447,8 +630,13 @@ static void mxsfb_crtc_disable_vblank(struct drm_crtc *crtc) struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); /* Disable and clear VBLANK IRQ */ - writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); - writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); + if (mxsfb->devdata->has_regsv8) { + writel(0, mxsfb->base + LCDC_V8_INT_ENABLE_D0); + writel(INT_STATUS_D0_VS_BLANK, mxsfb->base + LCDC_V8_INT_STATUS_D0); + } else { + writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); + writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); + } } static const struct drm_crtc_helper_funcs mxsfb_crtc_helper_funcs = { @@ -503,7 +691,10 @@ static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane, { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); - mxsfb_update_buffer(mxsfb, plane, false); + if (mxsfb->devdata->has_regsv8) + mxsfb_v8_update_buffer(mxsfb, plane); + else + mxsfb_update_buffer(mxsfb, plane, false); } static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane, diff --git a/drivers/gpu/drm/mxsfb/mxsfb_regs.h b/drivers/gpu/drm/mxsfb/mxsfb_regs.h index 694fea13e893e..43e08088a8a03 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_regs.h +++ b/drivers/gpu/drm/mxsfb/mxsfb_regs.h @@ -34,6 +34,30 @@ #define LCDC_AS_CLRKEYLOW 0x240 #define LCDC_AS_CLRKEYHIGH 0x250 +/* V8 register set */ +#define LCDC_V8_DISP_PARA 0x10 +#define LCDC_V8_DISP_SIZE 0x14 +#define LCDC_V8_HSYN_PARA 0x18 +#define LCDC_V8_VSYN_PARA 0x1c +#define LCDC_V8_VSYN_HSYN_WIDTH 0x20 +#define LCDC_V8_INT_STATUS_D0 0x24 +#define LCDC_V8_INT_ENABLE_D0 0x28 +#define LCDC_V8_INT_STATUS_D1 0x30 +#define LCDC_V8_INT_ENABLE_D1 0x34 +#define LCDC_V8_CTRLDESCL0_1 0x200 +#define LCDC_V8_CTRLDESCL0_3 0x208 +#define LCDC_V8_CTRLDESCL_LOW0_4 0x20c +#define LCDC_V8_CTRLDESCL_HIGH0_4 0x210 +#define LCDC_V8_CTRLDESCL0_5 0x214 +#define LCDC_V8_CSC0_CTRL 0x21c +#define LCDC_V8_CSC0_COEF0 0x220 +#define LCDC_V8_CSC0_COEF1 0x224 +#define LCDC_V8_CSC0_COEF2 0x228 +#define LCDC_V8_CSC0_COEF3 0x22c +#define LCDC_V8_CSC0_COEF4 0x230 +#define LCDC_V8_CSC0_COEF5 0x234 +#define LCDC_V8_PANIC0_THRES 0x238 + #define CTRL_SFTRST BIT(31) #define CTRL_CLKGATE BIT(30) #define CTRL_BYPASS_COUNT BIT(19) @@ -121,6 +145,118 @@ #define AS_CTRL_ALPHA_CTRL_EMBEDDED (0 << 1) #define AS_CTRL_AS_ENABLE BIT(0) +/* V8 register set */ +#define CTRL_SW_RESET BIT(31) +#define CTRL_FETCH_START_OPTION_FPV 0 +#define CTRL_FETCH_START_OPTION_PWV BIT(8) +#define CTRL_FETCH_START_OPTION_BPV BIT(9) +#define CTRL_FETCH_START_OPTION_RESV GENMASK(9, 8) +#define CTRL_FETCH_START_OPTION_MASK GENMASK(9, 8) +#define CTRL_NEG BIT(4) +#define CTRL_INV_PXCK BIT(3) +#define CTRL_INV_DE BIT(2) +#define CTRL_INV_VS BIT(1) +#define CTRL_INV_HS BIT(0) + +#define DISP_PARA_DISP_ON BIT(31) +#define DISP_PARA_SWAP_EN BIT(30) +#define DISP_PARA_LINE_PATTERN_RGB565 GENMASK(28, 26) +#define DISP_PARA_LINE_PATTERN_RGB888 0 +#define DISP_PARA_LINE_PATTERN_MASK GENMASK(29, 26) +#define DISP_PARA_DISP_MODE_MASK GENMASK(25, 24) +#define DISP_PARA_BGND_R_MASK GENMASK(23, 16) +#define DISP_PARA_BGND_G_MASK GENMASK(15, 8) +#define DISP_PARA_BGND_B_MASK GENMASK(7, 0) + +#define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16) +#define DISP_SIZE_DELTA_Y_MASK GENMASK(31, 16) +#define DISP_SIZE_DELTA_X(n) ((n) & 0xffff) +#define DISP_SIZE_DELTA_X_MASK GENMASK(15, 0) + +#define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16) +#define HSYN_PARA_BP_H_MASK GENMASK(31, 16) +#define HSYN_PARA_FP_H(n) ((n) & 0xffff) +#define HSYN_PARA_FP_H_MASK GENMASK(15, 0) + +#define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16) +#define VSYN_PARA_BP_V_MASK GENMASK(31, 16) +#define VSYN_PARA_FP_V(n) ((n) & 0xffff) +#define VSYN_PARA_FP_V_MASK GENMASK(15, 0) + +#define VSYN_HSYN_WIDTH_PW_V(n) (((n) & 0xffff) << 16) +#define VSYN_HSYN_WIDTH_PW_V_MASK GENMASK(31, 16) +#define VSYN_HSYN_WIDTH_PW_H(n) ((n) & 0xffff) +#define VSYN_HSYN_WIDTH_PW_H_MASK GENMASK(15, 0) + +#define INT_STATUS_D0_FIFO_EMPTY BIT(24) +#define INT_STATUS_D0_DMA_DONE BIT(16) +#define INT_STATUS_D0_DMA_ERR BIT(8) +#define INT_STATUS_D0_VS_BLANK BIT(2) +#define INT_STATUS_D0_UNDERRUN BIT(1) +#define INT_STATUS_D0_VSYNC BIT(0) + +#define INT_ENABLE_D0_FIFO_EMPTY_EN BIT(24) +#define INT_ENABLE_D0_DMA_DONE_EN BIT(16) +#define INT_ENABLE_D0_DMA_ERR_EN BIT(8) +#define INT_ENABLE_D0_VS_BLANK_EN BIT(2) +#define INT_ENABLE_D0_UNDERRUN_EN BIT(1) +#define INT_ENABLE_D0_VSYNC_EN BIT(0) + +#define INT_STATUS_D1_PLANE_PANIC BIT(0) + +#define INT_ENABLE_D1_PLANE_PANIC_EN BIT(0) + +#define CTRLDESCL0_1_HEIGHT(n) (((n) & 0xffff) << 16) +#define CTRLDESCL0_1_HEIGHT_MASK GENMASK(31, 16) +#define CTRLDESCL0_1_WIDTH(n) ((n) & 0xffff) +#define CTRLDESCL0_1_WIDTH_MASK GENMASK(15, 0) + +#define CTRLDESCL0_3_PITCH(n) ((n) & 0xffff) +#define CTRLDESCL0_3_PITCH_MASK GENMASK(15, 0) + +#define CTRLDESCL_HIGH0_4_ADDR_HIGH(n) ((n) & 0xf) +#define CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK GENMASK(3, 0) + +#define CTRLDESCL0_5_EN BIT(31) +#define CTRLDESCL0_5_SHADOW_LOAD_EN BIT(30) +#define CTRLDESCL0_5_BPP_16_RGB565 BIT(26) +#define CTRLDESCL0_5_BPP_16_ARGB1555 (BIT(26) | BIT(24)) +#define CTRLDESCL0_5_BPP_16_ARGB4444 (BIT(26) | BIT(25)) +#define CTRLDESCL0_5_BPP_YCbCr422 (BIT(26) | BIT(25) | BIT(24)) +#define CTRLDESCL0_5_BPP_24_RGB888 BIT(27) +#define CTRLDESCL0_5_BPP_32_ARGB8888 (BIT(27) | BIT(24)) +#define CTRLDESCL0_5_BPP_32_ABGR8888 (BIT(27) | BIT(25)) +#define CTRLDESCL0_5_BPP_MASK GENMASK(27, 24) +#define CTRLDESCL0_5_YUV_FORMAT_Y2VY1U 0 +#define CTRLDESCL0_5_YUV_FORMAT_Y2UY1V BIT(14) +#define CTRLDESCL0_5_YUV_FORMAT_VY2UY1 BIT(15) +#define CTRLDESCL0_5_YUV_FORMAT_UY2VY1 (BIT(15) | BIT(14)) +#define CTRLDESCL0_5_YUV_FORMAT_MASK GENMASK(15, 14) + +#define CSC0_CTRL_CSC_MODE_MASK GENMASK(2, 1) +#define CSC0_CTRL_BYPASS BIT(0) + +#define CSC0_COEF0_A2_MASK GENMASK(26, 16) +#define CSC0_COEF0_A1_MASK GENMASK(10, 0) + +#define CSC0_COEF1_B1_MASK GENMASK(26, 16) +#define CSC0_COEF1_A3_MASK GENMASK(10, 0) + +#define CSC0_COEF2_B3_MASK GENMASK(26, 16) +#define CSC0_COEF2_B2_MASK GENMASK(10, 0) + +#define CSC0_COEF3_C2_MASK GENMASK(26, 16) +#define CSC0_COEF3_C1_MASK GENMASK(10, 0) + +#define CSC0_COEF4_D1_MASK GENMASK(24, 16) +#define CSC0_COEF4_C3_MASK GENMASK(10, 0) + +#define CSC0_COEF5_D3_MASK GENMASK(24, 16) +#define CSC0_COEF5_D2_MASK GENMASK(8, 0) + +#define PANIC0_THRES_LOW_MASK GENMASK(24, 16) +#define PANIC0_THRES_HIGH_MASK GENMASK(8, 0) + #define MXSFB_MIN_XRES 120 #define MXSFB_MIN_YRES 120 #define MXSFB_MAX_XRES 0xffff