From patchwork Tue Mar 1 06:03:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E58A9C433FE for ; Tue, 1 Mar 2022 06:04:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232434AbiCAGEw (ORCPT ); Tue, 1 Mar 2022 01:04:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231624AbiCAGEq (ORCPT ); Tue, 1 Mar 2022 01:04:46 -0500 Received: from mail-io1-xd49.google.com (mail-io1-xd49.google.com [IPv6:2607:f8b0:4864:20::d49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55AD360D84 for ; Mon, 28 Feb 2022 22:04:06 -0800 (PST) Received: by mail-io1-xd49.google.com with SMTP id u25-20020a5d8199000000b006421bd641bbso8079961ion.11 for ; Mon, 28 Feb 2022 22:04:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=hKYGlAUdZ25ql2C/Gsw0koexLM8OWhnhOaAg6E1WDkU=; b=PNbBxy7c6v9D2F9vFc4E0Fyd4ICAd/PH1o1iJlOdm6vtAsni+2laL0XjK0GitpaciV VaN3YUgrTfhnxvEll4rj4+8zz9dMk/caFNY7AGGwSBr9VAekIBCjAdxhHCh2UI2bYCej ZKoTeWtxs5qYmP6HbOpZAEPKNscAmd9M1XExYyXpHhOduQa+cBNaKJVVYbsRDPsX/o5I BOYJVApKuvpeHukdVlXwpJKfZoqSryRheXUXTFGcu1eswnCqsg327k1P9OTHzJuu5Os8 MmDsxuIWXE+8/rkpZRkrFwrcgcm3DCNUlFyWIsmpyKvpezEkbWtt2XMgdEkBcZ0zUZyc 943w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=hKYGlAUdZ25ql2C/Gsw0koexLM8OWhnhOaAg6E1WDkU=; b=JZhk1Day2QVEuSVYg0qIFbWpIW/AoPi1ZCqJ/uHJiCmVNC6rhZp6Lr9FqCcoYRZa1Z ONBMNOxPI7C8Wi/j9DT7PVfCTyDMeVOQDqI4SZIClBy4PgcVSl3Fo4YnSE7EkKBHN1vs FMTk7vlwmAII1rTRuX85Nu6+ydUTaZjrXGO2IGLPXD/VvetF8oZPM7vyR98bCV0rtDhY ia08IyS8eiuoK6BmS0RGcBMny4Oc1q8+nw2Mqsyb+fiIspPJIE2+MFvreGE4UsSgHlox sphmqkp2QWGz68Nll/pTCBVaPih0v3IbDsxW8fTbg3G8ul29AUNnZtaaKaZt60yS5MSt k/zg== X-Gm-Message-State: AOAM531ZHGxA6YqIoCKu9akkVOZdK/LyzWhTl9b5UYJSgab2Da3qucPN TRRXjZ9kXQOqunmfGjxLVApgqUvGvJT9d+V4ONpQusFWXNTglh6PG0YDqFYLoriWDeIOKSb+odV VuA9prOKzhRaX+FK2tMx+NqefbCK3I5JwTX07dGRR0GbNTKXHUwQhCHZuGQ== X-Google-Smtp-Source: ABdhPJwNDxB3v29ycUUfRV/jirXb8eV4WfwkAb9bHnDgjPFmkRA3OSlTFzTQDSoU9N1uUIQWJyG0F/beEpI= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6e02:144e:b0:2c2:e890:2c7a with SMTP id p14-20020a056e02144e00b002c2e8902c7amr7814463ilo.103.1646114645543; Mon, 28 Feb 2022 22:04:05 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:44 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-2-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 1/8] KVM: nVMX: Keep KVM updates to BNDCFGS ctrl bits across MSR write From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when guest MPX disabled"), KVM has taken ownership of the "load IA32_BNDCFGS" and "clear IA32_BNDCFGS" VMX entry/exit controls. The ABI is that these bits must be set in the IA32_VMX_TRUE_{ENTRY,EXIT}_CTLS MSRs if the guest's CPUID supports MPX, and clear otherwise. However, commit aedbaf4f6afd ("KVM: x86: Extract kvm_update_cpuid_runtime() from kvm_update_cpuid()") partially broke KVM ownership of the aforementioned bits. Before, kvm_update_cpuid() was exercised frequently when running a guest and constantly applied its own changes to the BNDCFGS bits. Now, the BNDCFGS bits are only ever updated after a KVM_SET_CPUID/KVM_SET_CPUID2 ioctl, meaning that a subsequent MSR write from userspace will clobber these values. Uphold the old ABI by reapplying KVM's tweaks to the BNDCFGS bits after an MSR write from userspace. Fixes: aedbaf4f6afd ("KVM: x86: Extract kvm_update_cpuid_runtime() from kvm_update_cpuid()") Signed-off-by: Oliver Upton --- arch/x86/kvm/vmx/nested.c | 9 +++++++++ arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/kvm/vmx/vmx.h | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 1dfe23963a9e..a13f8f4e3d82 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -1291,6 +1291,15 @@ vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) *lowp = data; *highp = data >> 32; + + /* + * Ensure KVM fiddling with these MSRs is preserved after userspace + * write. + */ + if (msr_index == MSR_IA32_VMX_TRUE_ENTRY_CTLS || + msr_index == MSR_IA32_VMX_TRUE_EXIT_CTLS) + nested_vmx_entry_exit_ctls_update(&vmx->vcpu); + return 0; } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b325f99b2177..3a97220c5f78 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7246,7 +7246,7 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) #undef cr4_fixed1_update } -static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) +void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 7f2c82e7f38f..e134e2763502 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -423,6 +423,8 @@ static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu); +void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu); + /* * Note, early Intel manuals have the write-low and read-high bitmap offsets * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and From patchwork Tue Mar 1 06:03:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D86B7C433EF for ; Tue, 1 Mar 2022 06:04:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232452AbiCAGEz (ORCPT ); Tue, 1 Mar 2022 01:04:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231790AbiCAGEr (ORCPT ); Tue, 1 Mar 2022 01:04:47 -0500 Received: from mail-ot1-x349.google.com (mail-ot1-x349.google.com [IPv6:2607:f8b0:4864:20::349]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CF9960D87 for ; Mon, 28 Feb 2022 22:04:07 -0800 (PST) Received: by mail-ot1-x349.google.com with SMTP id f37-20020a9d2c28000000b005ad366aa68dso10577319otb.8 for ; Mon, 28 Feb 2022 22:04:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=k/u5xT5AyOJ878deH0FLroHeIz5vo7dAUy4eq2iMv4Y=; b=Ox3zTHlfIntsxUPlNJjNgI3pzLeNdHy7CAuIS6TJ7sDG5BoqHOSpQsu9X3xj7Pc+3h 3dxfXgUj6JrFQgBFZLuhhdFOexOhiFqIqGoIZDwy1Fv6vf6XVnTwISmfpNVPogqc75k1 wyW80dZBSxdNDlNrtO4f+CDlRUc8jGJlwk8TAWQ+pFKdIJ08A+G8Hh7wVGnWbju6fJqI PqXHiLFfVn94GVmzDLR0L0dlc0l/XNwJyTHT0riYAyJc+3JucAWts/1LuyuLFK9bpIgW ZeYj41Xgrqo9R/0xlDAwSs5K9gnIkVPo/H9jpr3JzFtFoaNFJlyzjYUK2qRtRse6L0w+ sz3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=k/u5xT5AyOJ878deH0FLroHeIz5vo7dAUy4eq2iMv4Y=; b=6EBf2pTAFnlyUTwfviS8WY2QQsYrwwYDJ6VllMnQs3eer8SFjoB27BQfZA6oCKcO86 HXSfTMm6xeAEw9bFOZqfj+pfn2oVo0SqNCvpMuGGffGA8ReortxxVqHQLiRxr+lSnA93 qx7wFic/WdxB+uB/Z5mzvewcAMQIygk7PjaalGvOm3SEq58NwPhk7/8xqtIKfvYyOZcr +k25gGEPzLjk+HplFTCNejI6sVF1cVby8bIFRlup1AJp7kLeHHabEeLA9ww/gRrGuUYv 9n2srCOlm8cQjH8vIpTJcm4wrlLsS+gLXefV3TwlBRLCm9x/4KOPlMfLMRJUB0KaU2zg gnkw== X-Gm-Message-State: AOAM532Rs/ceXOrCKVBRi0Z9LV8WtYO9APIyAqhhebP6iIjQlimvyIJt 6bnvcFKh2EPueCK+qWE/rWjwmyQ/8nzEEVMqVmzRbmi5gBg+2IU7GV05yfPPsAqwgMQwnujuKvR YyH+H8LxGjyIh6S4qbc7vnH4YOdttrQq8bJbg9ChK5NZ9id3GWW6SwhzOIw== X-Google-Smtp-Source: ABdhPJz5eOtfH8//O4h26vbtDAVoKkYCeVIMNMUxZwTkWvygUXBuWcYhTVog87mlDLu/Ou9yKI3P/j2vlp8= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6870:a1a3:b0:d3:f4a7:f3e3 with SMTP id a35-20020a056870a1a300b000d3f4a7f3e3mr2940202oaf.109.1646114646690; Mon, 28 Feb 2022 22:04:06 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:45 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-3-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 2/8] KVM: nVMX: Keep KVM updates to PERF_GLOBAL_CTRL ctrl bits across MSR write From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since commit 03a8871add95 ("KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL VM-{Entry,Exit} control"), KVM has taken ownership of the "load IA32_PERF_GLOBAL_CTRL" VMX entry/exit control bits. The ABI is that these bits will be set in the IA32_VMX_TRUE_{ENTRY,EXIT}_CTLS MSRs if the guest's CPUID exposes a vPMU that supports the IA32_PERF_GLOBAL_CTRL MSR (CPUID.0AH:EAX[7:0] > 1), and clear otherwise. However, commit aedbaf4f6afd ("KVM: x86: Extract kvm_update_cpuid_runtime() from kvm_update_cpuid()") partially broke KVM ownership of the aforementioned bits. Before, kvm_update_cpuid() was exercised frequently when running a guest and constantly applied its own changes to the "load IA32_PERF_GLOBAL_CTRL" bits. Now, the "load IA32_PERF_GLOBAL_CTRL" bits are only ever updated after a KVM_SET_CPUID/KVM_SET_CPUID2 ioctl, meaning that a subsequent MSR write from userspace will clobber these values. Note that older kernels without commit c44d9b34701d ("KVM: x86: Invoke vendor's vcpu_after_set_cpuid() after all common updates") still require that the entry/exit controls be updated from kvm_pmu_refresh(). Leave the benign call in place to allow for cleaner backporting and punt the cleanup to a later change. Uphold the old ABI by reapplying KVM's tweaks to the "load IA32_PERF_GLOBAL_CTRL" bits after an MSR write from userspace. Fixes: aedbaf4f6afd ("KVM: x86: Extract kvm_update_cpuid_runtime() from kvm_update_cpuid()") Reported-by: Jim Mattson Signed-off-by: Oliver Upton --- arch/x86/kvm/pmu.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 7a7b8d5b775e..2d9995668e0b 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -140,6 +140,11 @@ static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value) return sample_period; } +static inline u8 kvm_pmu_version(struct kvm_vcpu *vcpu) +{ + return vcpu_to_pmu(vcpu)->version; +} + void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel); void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx); void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 3a97220c5f78..224ef4c19a5d 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7261,6 +7261,18 @@ void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; } } + + /* + * KVM supports a 1-setting of the "load IA32_PERF_GLOBAL_CTRL" + * VM-{Entry,Exit} controls if the vPMU supports IA32_PERF_GLOBAL_CTRL. + */ + if (kvm_pmu_version(vcpu) >= 2) { + vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high |= VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } else { + vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } } static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) From patchwork Tue Mar 1 06:03:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C2A9C433F5 for ; Tue, 1 Mar 2022 06:04:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232520AbiCAGEy (ORCPT ); Tue, 1 Mar 2022 01:04:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232048AbiCAGEs (ORCPT ); Tue, 1 Mar 2022 01:04:48 -0500 Received: from mail-io1-xd49.google.com (mail-io1-xd49.google.com [IPv6:2607:f8b0:4864:20::d49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A62160D89 for ; Mon, 28 Feb 2022 22:04:08 -0800 (PST) Received: by mail-io1-xd49.google.com with SMTP id e23-20020a6b6917000000b006406b9433d6so10023774ioc.14 for ; Mon, 28 Feb 2022 22:04:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=+fpfdzqr9xU6NfmbrsCOkjMW9hL4umQ1wJKtm6Q5JZs=; b=no+Ibs3wsh0D+E70vs93/QjCl+k4DLHqPqYoFrhxs3xZhOG14n6XeWlDsS1ZUWeyie uOB3RuY0uXv8RcGkB9QDDKgQ7qmzM8fhKCZYK4ol03bdPeoCKWTafhXrXx5PSmTvXhSQ sLkK6g+mA+8CzffSrriaE/HhdOB3r4XZ3Qb4MDXsIhRQAZBm4jT2LYAuqg2yjbfKHbqH GVJ61mBGfhv1evMdrAk8/LDher2oDSkL2UsxkAXQmt4Yxif6YkiXNRTvaQ587JvchF24 VVIh7wvi0+8ePz8Zf32z7sf5fb14HznrsYFdyjSSmWv2TcsMymMM6L8xMXhQ76S32BMU JK+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=+fpfdzqr9xU6NfmbrsCOkjMW9hL4umQ1wJKtm6Q5JZs=; b=rzpMHU4RM83lXiOps5eu5lrecTowjfk9cPP8lDFV6K0QcPWWViFqmPc3hMUeB8FQ1O 3w4NnpBgkkVa/ypPximoR74g9X38PEvzx1zijSNqak0UfmG0wflslyTEpe4C5hkQ6QP1 3C+NaXs8zim1cukWfLghaqMPYr+iJ2yz1z2BW/nExIiRLoifdRod2khLAxgjIgxxxF5b 9La6ckpFhre4NLkv09gFcWhxItW023KYUAccYMAD9NRP8wDmKmF9y1TvyOm9YYl7vwO7 nf+BiftAM8r1r0seBa9UE4h+x7xcwdsC9XDBXvKqYZ2IS2j/9xSOkGCFb1hhGfOZVfVe bJpA== X-Gm-Message-State: AOAM530ylvJ6Mttq3ET/ALi1jEGjnfkx7DRnGMqJshZUUxFaiquUBHJF LqNaWrk/5uCz6ne5TJahjiFyOLlt4N1EOM9aHWQGb5h7evoV4+XfDEy0XSkwzqO7qP6ToZZl6XH gJYarvaXGsGU4XiFB2IIMaqOPTuM9Q7ehLEeDa78Nk2fhbNeWsATHPuznUA== X-Google-Smtp-Source: ABdhPJxvEf4u6yFjoA+HIY8bQ+rp8oxkHIsWac2zz+fAUHyxtA9ycZdNZuTuQGY65105CO04FHV2AEy+a3M= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6e02:e0d:b0:2bf:5556:4c4a with SMTP id a13-20020a056e020e0d00b002bf55564c4amr21252743ilk.31.1646114647819; Mon, 28 Feb 2022 22:04:07 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:46 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-4-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 3/8] KVM: nVMX: Drop nested_vmx_pmu_refresh() From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org nested_vmx_pmu_refresh() is now unneeded, as the call to nested_vmx_entry_exit_ctls_update() in vmx_vcpu_after_set_cpuid() guarantees that the VM-{Entry,Exit} control MSR changes are applied after setting CPUID. Drop all vestiges of nested_vmx_pmu_refresh(). No functional change intended. Signed-off-by: Oliver Upton --- arch/x86/kvm/vmx/nested.c | 22 ---------------------- arch/x86/kvm/vmx/nested.h | 2 -- arch/x86/kvm/vmx/pmu_intel.c | 3 --- 3 files changed, 27 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index a13f8f4e3d82..dec45606ce0c 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -4806,28 +4806,6 @@ int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, return 0; } -void nested_vmx_pmu_refresh(struct kvm_vcpu *vcpu, - bool vcpu_has_perf_global_ctrl) -{ - struct vcpu_vmx *vmx; - - if (!nested_vmx_allowed(vcpu)) - return; - - vmx = to_vmx(vcpu); - if (vcpu_has_perf_global_ctrl) { - vmx->nested.msrs.entry_ctls_high |= - VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; - vmx->nested.msrs.exit_ctls_high |= - VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; - } else { - vmx->nested.msrs.entry_ctls_high &= - ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; - vmx->nested.msrs.exit_ctls_high &= - ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; - } -} - static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer, int *ret) { diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index c92cea0b8ccc..14ad756aac46 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -32,8 +32,6 @@ int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata); int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, u32 vmx_instruction_info, bool wr, int len, gva_t *ret); -void nested_vmx_pmu_refresh(struct kvm_vcpu *vcpu, - bool vcpu_has_perf_global_ctrl); void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu); bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, int size); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 4e5b1eeeb77c..6433a1091333 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -541,9 +541,6 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters); - nested_vmx_pmu_refresh(vcpu, - intel_is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)); - if (intel_pmu_lbr_is_compatible(vcpu)) x86_perf_get_lbr(&lbr_desc->records); else From patchwork Tue Mar 1 06:03:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F410C433FE for ; Tue, 1 Mar 2022 06:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232526AbiCAGE4 (ORCPT ); Tue, 1 Mar 2022 01:04:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232383AbiCAGEw (ORCPT ); Tue, 1 Mar 2022 01:04:52 -0500 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C167C60CFB for ; Mon, 28 Feb 2022 22:04:09 -0800 (PST) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-2d6d36ec646so120355217b3.23 for ; Mon, 28 Feb 2022 22:04:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=H7mi9apdEnxrzE+/TvNYFRdRST2jicY9ozMhi537JbY=; b=hI002BoVgiodXwx/65LBkcjZv1ADrdTRFD0xLhKH/uFgduG6Ah1QTZJ9ErBKQZxa/L FyT9dF2n58YJUnZ0WvPLIwxWSLmI/yNuMlEPvRxwBJws4eZ1ZO+LCC+t5CXYrw1hGCUZ RLicMCqS8yKJ4KklrkyC6+cwaT0rionteofH2cipj2xfL0CE+uSF9sTmneMKn7Xovkqu 2U6NbpJWJWthhrz4G2BSpnsAM3DHezjXZEH7jy9Q4qp82wpJ3dDX0dHNZUxrYv5V7v9i cSVuZ+miCpeqpBTSLq6lphjG+H8W6WSUZXPxHVrx9emhLfcDXHBji9QxeYHe0j/X2edF HaWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=H7mi9apdEnxrzE+/TvNYFRdRST2jicY9ozMhi537JbY=; b=k0au36kodY201ats+eEwgfedw2LbQYGZDe1Ub8l9G2Gyn9CdjqFZQvMofOLpOdGvg+ Ni+iWb9Gnb6DVaNo8mtN9VXgO6t95XDG9U4GabwzauvTUlb3wuoHlKHy5WjWG5wSVuIJ ev/EH+ZMq0+xyDd5sk177Q88u21Kbf8Ph77CgkpTahi8PxC+uEPu5JdHpwObHqyiomtq M31fpycnFA72xlxfB7Obmu8J29eS8yIyEn/ll7xsc89OFXIOPUVPH2YTauNL/PY95gtM fu6zXK9/+IfRyOrjsIhwZ87lqWooQOA/+Sm8wJi8ChtDgN+8j3jIPge5U5nm3A7g4OIL 5QlA== X-Gm-Message-State: AOAM531ltM2+XVTr3iRP5jFfjPCkooXDAeBlECaZxDYtXojHWaMsO3aA coeWCHymV8JZK6IeyCnJvZ6YT7yLkKYN83GQcfrrcv4gEMpSianVl5u5XQqGnLWSZBVJBGlA2TS fTI5JkW03Qnk2uQA8xNdsCQFVxbx/iUzUsNPJg60LHMW3LPBjwXmtqfAsEQ== X-Google-Smtp-Source: ABdhPJwGj9YN7SV/EGBjvQBT2R9MW63u6mD5h/lVkWxZcAlfe8JkMTQhIKT2P+4mHi+Gn8dVMPIP0PlbplM= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6902:534:b0:61d:a782:81b6 with SMTP id y20-20020a056902053400b0061da78281b6mr22155197ybs.253.1646114648862; Mon, 28 Feb 2022 22:04:08 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:47 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-5-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 4/8] KVM: x86: Introduce KVM_CAP_DISABLE_QUIRKS2 From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM_CAP_DISABLE_QUIRKS is irrevocably broken. The capability does not advertise the set of quirks which may be disabled to userspace, so it is impossible to predict the behavior of KVM. Worse yet, KVM_CAP_DISABLE_QUIRKS will tolerate any value for cap->args[0], meaning it fails to reject attempts to set invalid quirk bits. The only valid workaround for the quirky quirks API is to add a new CAP. Actually advertise the set of quirks that can be disabled to userspace so it can predict KVM's behavior. Reject values for cap->args[0] that contain invalid bits. Finally, add documentation for the new capability and describe the existing quirks. Signed-off-by: Oliver Upton --- Documentation/virt/kvm/api.rst | 50 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/kvm_host.h | 7 +++++ arch/x86/kvm/x86.c | 8 ++++++ include/uapi/linux/kvm.h | 1 + 4 files changed, 66 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index f5d011351016..8f7240e79cc0 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -7079,6 +7079,56 @@ resource that is controlled with the H_SET_MODE hypercall. This capability allows a guest kernel to use a better-performance mode for handling interrupts and system calls. +7.31 KVM_CAP_DISABLE_QUIRKS2 +---------------------------- + +:Capability: KVM_CAP_DISABLE_QUIRKS2 +:Parameters: args[0] - set of KVM quirks to disable +:Architectures: x86 +:Type: vm + +This capability, if enabled, will cause KVM to disable some behavior +quirks. + +Calling KVM_CHECK_EXTENSION for this capability returns a bitmask of +quirks that can be disabled in KVM. + +The argument to KVM_ENABLE_CAP for this capability is a bitmask of +quirks to disable, and must be a subset of the bitmask returned by +KVM_CHECK_EXTENSION. + +The valid bits in cap.args[0] are: + +=================================== ============================================ + KVM_X86_QUIRK_LINT0_REENABLED By default, the reset value for the LVT + LINT0 register is 0x700 (APIC_MODE_EXTINT). + When this quirk is disabled, the reset value + is 0x10000 (APIC_LVT_MASKED). + + KVM_X86_QUIRK_CD_NW_CLEARED By default, KVM clears CR0.CD and CR0.NW. + When this quirk is disabled, KVM does not + change the value of CR0.CD and CR0.NW. + + KVM_X86_QUIRK_LAPIC_MMIO_HOLE By default, the MMIO LAPIC interface is + available even when configured for x2APIC + mode. When this quirk is disabled, KVM + disables the MMIO LAPIC interface if the + LAPIC is in x2APIC mode. + + KVM_X86_QUIRK_OUT_7E_INC_RIP By default, KVM pre-increments %rip before + exiting to userspace for an OUT instruction + to port 0x7e. When this quirk is disabled, + KVM does not pre-increment %rip before + exiting to userspace. + + KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT When this quirk is disabled, KVM sets + CPUID.01H:ECX[bit 3] (MONITOR/MWAIT) if + IA32_MISC_ENABLE[bit 18] (MWAIT) is set. + Additionally, when this quirk is disabled, + KVM clears CPUID.01H:ECX[bit 3] if + IA32_MISC_ENABLE[bit 18] is cleared. +=================================== ============================================ + 8. Other capabilities. ====================== diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index ccec837e520d..bc3405565967 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1963,4 +1963,11 @@ int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages); #define KVM_CLOCK_VALID_FLAGS \ (KVM_CLOCK_TSC_STABLE | KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC) +#define KVM_X86_VALID_QUIRKS \ + (KVM_X86_QUIRK_LINT0_REENABLED | \ + KVM_X86_QUIRK_CD_NW_CLEARED | \ + KVM_X86_QUIRK_LAPIC_MMIO_HOLE | \ + KVM_X86_QUIRK_OUT_7E_INC_RIP | \ + KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) + #endif /* _ASM_X86_KVM_HOST_H */ diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c712c33c1521..ec9b602be8da 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4350,6 +4350,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; break; } + case KVM_CAP_DISABLE_QUIRKS2: + r = KVM_X86_VALID_QUIRKS; + break; default: break; } @@ -5896,6 +5899,11 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, return -EINVAL; switch (cap->cap) { + case KVM_CAP_DISABLE_QUIRKS2: + r = -EINVAL; + if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) + break; + fallthrough; case KVM_CAP_DISABLE_QUIRKS: kvm->arch.disabled_quirks = cap->args[0]; r = 0; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index d2f1efc3aa35..91a6fe4e02c0 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1143,6 +1143,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_AIL_MODE_3 210 #define KVM_CAP_S390_MEM_OP_EXTENSION 211 #define KVM_CAP_PMU_CAPABILITY 212 +#define KVM_CAP_DISABLE_QUIRKS2 213 #ifdef KVM_CAP_IRQ_ROUTING From patchwork Tue Mar 1 06:03:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD430C433EF for ; Tue, 1 Mar 2022 06:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232531AbiCAGE6 (ORCPT ); Tue, 1 Mar 2022 01:04:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232397AbiCAGEw (ORCPT ); Tue, 1 Mar 2022 01:04:52 -0500 Received: from mail-io1-xd49.google.com (mail-io1-xd49.google.com [IPv6:2607:f8b0:4864:20::d49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A8FB60D87 for ; Mon, 28 Feb 2022 22:04:10 -0800 (PST) Received: by mail-io1-xd49.google.com with SMTP id g16-20020a05660226d000b00638d8e1828bso10018875ioo.13 for ; Mon, 28 Feb 2022 22:04:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=WmlQrPuUshRXR/ErY9Gh4Cre7PwL7ex7k3lY6rX2RPo=; b=qlaakjGDY1eQ1DwD8fqCv0wKsYf1fODdSr4UFxI7sB5iVaIzgwIx3MfWI51OCyz76z a3fN9qknJmxC+PGGIc1HBK3jPKtSO4pmHp2LAU37v23AddyZOZj4cSmwz0eD+stlEydd 0LIxQCvvBWo0MWcs1DNkroxP/qC/AYc1mu4n3d2l1/516pgFlVNA+fCcSeJYQOlBZvQb 4Fz/4L+clLo0jWjjMN/48o3y2Dm8/dhjAIfE5+jPlPNzfUwtWzQ2GLNymFYITJkW0Ucn 7wBOs6Ztccw7o0DwSUHfTj88oI3WGvdnyY7KiTtk8L1bCPgT1SxkaiSYvcg+K5MZyPJ/ VMpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=WmlQrPuUshRXR/ErY9Gh4Cre7PwL7ex7k3lY6rX2RPo=; b=qFirXohF+pSmv40/XwCCSoXHrI8kPrO7tCPHQJZrJuTxyf8AxRXU/PYaYR3WRVjMZp z7hTzxeofzqFJFJlj4JHqEVDc6DDvM/fVBSoHHYWjf0KJ12VVrBKZrl3+7IjuG9jhrz6 ZBIRt+pTeI8x74Xd3C2czoO4ScvjuMJhigLvHidyxSviRAArgW9g9zpK7I2Sm8SyDUxU 03ogJGUqgF7d7/c9VELSuqWn8YjXquJp0QiEbuZoaCozvJys9mgZqLSDNnfQ3as/k7B9 F6P7yIVcDIu3IgoCJfcJZQgSNsZYDgBtNxRGu19pn1S7tHZOsKtjhqRDuT7/PxL9gYaJ LUCg== X-Gm-Message-State: AOAM530WDrjeNkg50e2yvrRnGTHWd8JnoH371z9sQuXxqDALK3Vwmymz 4/GjZB531lx1zlu0UMrtqFwIQGplN04gExLbzXJdF81FANuvke0nK9LoVCw+P/Q0hW1UBjP1hnN eSZf7oTQjMIyxGNfBZzeBVwybSeGgIp/qdK3LWM6AYWet20VoHEAE6lS+TA== X-Google-Smtp-Source: ABdhPJxWKF155htloiIQjrJG0ZroOywjHl0mTG3YWJLZpyvP9t8ajeZEwVYfx4gB7jKaReodZMR+MzfC4DM= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6602:1594:b0:640:7236:e6ea with SMTP id e20-20020a056602159400b006407236e6eamr17788421iow.23.1646114650037; Mon, 28 Feb 2022 22:04:10 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:48 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-6-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 5/8] KVM: nVMX: Add a quirk for KVM tweaks to VMX control MSRs From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM really has no business messing with the vCPU state. Nonetheless, it has become ABI for KVM to adjust certain bits of the VMX entry/exit control MSRs depending on the guest CPUID. Namely, the bits associated with the IA32_PERF_GLOBAL_CTRL and IA32_BNDCFGS MSRs were conditionally enabled if the guest CPUID allows for it. Allow userspace to opt-out of changes to VMX control MSRs by adding a new KVM quirk. Suggested-by: Sean Christopherson Signed-off-by: Oliver Upton --- Documentation/virt/kvm/api.rst | 24 ++++++++++++++++++++++++ arch/x86/include/asm/kvm_host.h | 3 ++- arch/x86/include/uapi/asm/kvm.h | 11 ++++++----- arch/x86/kvm/vmx/vmx.c | 3 +++ 4 files changed, 35 insertions(+), 6 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 8f7240e79cc0..9bb79ca9de89 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -7127,6 +7127,30 @@ The valid bits in cap.args[0] are: Additionally, when this quirk is disabled, KVM clears CPUID.01H:ECX[bit 3] if IA32_MISC_ENABLE[bit 18] is cleared. + + KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS By default, KVM adjusts the values of + IA32_VMX_TRUE_ENTRY_CTLS and + IA32_VMX_TRUE_EXIT_CTLS MSRs under the + following conditions: + + - If CPUID.07H:EBX[bit 14] (MPX) is set, KVM + sets IA32_VMX_TRUE_ENTRY_CTLS[bit 48] + ('load IA32_BNDCFGS') and + IA32_VMX_TRUE_EXIT_CTLS[bit 55] + ('clear IA32_BNDCFGS'). Otherwise, these + corresponding MSR bits are cleared. + - If CPUID.0AH:EAX[bits 7:0] > 1, KVM sets + IA32_VMX_TRUE_ENTRY_CTLS[bit 45] + ('load IA32_PERF_GLOBAL_CTRL') and + IA32_VMX_TRUE_EXIT_CTLS[bit 44] + ('load IA32_PERF_GLOBAL_CTRL'). Otherwise, + these corresponding MSR bits are cleared. + + When this quirk is disabled, KVM will not + change the values of + IA32_VMX_TRUE_ENTRY_CTLS or + IA32_VMX_TRUE_EXIT_CTLS based on the + aforementioned CPUID bits. =================================== ============================================ 8. Other capabilities. diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index bc3405565967..1b905e6c4760 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1968,6 +1968,7 @@ int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages); KVM_X86_QUIRK_CD_NW_CLEARED | \ KVM_X86_QUIRK_LAPIC_MMIO_HOLE | \ KVM_X86_QUIRK_OUT_7E_INC_RIP | \ - KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) + KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT | \ + KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS) #endif /* _ASM_X86_KVM_HOST_H */ diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h index bf6e96011dfe..acbab6a97fae 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -428,11 +428,12 @@ struct kvm_sync_regs { struct kvm_vcpu_events events; }; -#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) -#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) -#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) -#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) -#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) +#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) +#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) +#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) +#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) +#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) +#define KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS (1 << 5) #define KVM_STATE_NESTED_FORMAT_VMX 0 #define KVM_STATE_NESTED_FORMAT_SVM 1 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 224ef4c19a5d..21b98bad1319 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7250,6 +7250,9 @@ void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); + if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS)) + return; + if (kvm_mpx_supported()) { bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); From patchwork Tue Mar 1 06:03:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85FE9C4332F for ; Tue, 1 Mar 2022 06:04:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232383AbiCAGE5 (ORCPT ); Tue, 1 Mar 2022 01:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232425AbiCAGEw (ORCPT ); Tue, 1 Mar 2022 01:04:52 -0500 Received: from mail-il1-x14a.google.com (mail-il1-x14a.google.com [IPv6:2607:f8b0:4864:20::14a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10C9E60D84 for ; Mon, 28 Feb 2022 22:04:11 -0800 (PST) Received: by mail-il1-x14a.google.com with SMTP id r4-20020a92d444000000b002c26d0c9354so10428650ilm.15 for ; Mon, 28 Feb 2022 22:04:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Wgqi2KPCKBH/bMb5m85+vN32dj3dX5av+lDesCp799s=; b=do7HFnBqFt/mQ6mPr6awgcpxK4/atJuQzEJBpvhh+J65YWPsH4xQr4qytT6tRmYkxC Ne49f8ddcbGne5ua0yd533R2HiHfgOZJKhv09EgkxJEtrFZGsoJlA+kZ8B8gtHocR/rN Orbx0OQ25QmLLxRuWDRKSwPShfxR6KDvpRL7Cn3lFaGJkAEBws0ETAzuuRcdKHe6vhCP CDtiDkHS1MqECcZ/x3uwq8YDd51CWPNIxa94nzAjBKwN/bTUgOR08k7M2E8Y3Jeqg4QM A6rooxDhMYQf6HXdAKt5ZLc0LWCmkN2tWb2B33MGXt/21uBbPn22qdC/3P6O4J5XfNa2 ZRkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Wgqi2KPCKBH/bMb5m85+vN32dj3dX5av+lDesCp799s=; b=SFV31Kh2nvJFljQDglqoFhIauihfJMMrX8hKCcr0lyuCAiwP20VCDluV2tEn/4XGHr CWnfYv4W01E+Tm6ATBSeJPXoXBuCC6Yw9p7GaEvizTwSh0Jb4gvSVDQcyfrYfYu+2KJX bE3cLkKSNrMpDi+sS6ZigxsZwA42aDMqw2ZzQ9EQSy13E3nUqVy4n0D8Lv52wkdygL3B ImVKXQxJCHZYL4Ww82NHxiEykMhrtY0IdlmrHgKWWo3HJmI8Q92Ie87JZBUqmRwCdNrj KXQP4CgHXlxcZvdAEDjh+QD1umRDgGoPDXDOHoDQ0n+VpPSSxF3B5mvcSNcn8sMijyPz P6XA== X-Gm-Message-State: AOAM53096H8q/vL2GCRzCDbURRLUhUBuZgdyUGVT3jQYcfQHbKb7OKT2 +mBJNqrATjm4NS4nudrQAvIu9dmFwi5+ijuTEi05jZA6ThDtqL0GjGC93eKTH9rn4P61HBi3Bf5 vJg+Z50okaJYjvVTG7AVM5O245tbvSbEvdHfBlzl2EmnsHPsfTP6qasaWPg== X-Google-Smtp-Source: ABdhPJy2jwNdQqeXJ9+0yxw19Q4q8daYK8SXc/+efNbMYVDN9KegvkPTKRcCUjsxld0LCE3zRWcUVECHuqo= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a92:b107:0:b0:2be:cb81:dd96 with SMTP id t7-20020a92b107000000b002becb81dd96mr21320841ilh.189.1646114651083; Mon, 28 Feb 2022 22:04:11 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:49 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-7-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 6/8] selftests: KVM: Separate static alloc from KVM_GET_SUPPORTED_CPUID call From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The library code allows for a single allocation of CPUID to store the value returned by KVM_GET_SUPPORTED_CPUID. Subsequent calls to the helper simply return a pointer to the aforementioned allocation. A subsequent change introduces a selftest that contains test cases which adjust the CPUID value before calling KVM_SET_CPUID2. Using a single definition of CPUID is problematic, as the changes are not isolated to a single test case. Create a helper that allocates memory for CPUID on a per-call basis. Signed-off-by: Oliver Upton --- .../selftests/kvm/include/x86_64/processor.h | 1 + .../selftests/kvm/lib/x86_64/processor.c | 33 +++++++++++++++---- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h index 8a470da7b71a..e36ab7de7717 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -390,6 +390,7 @@ void kvm_x86_state_cleanup(struct kvm_x86_state *state); struct kvm_msr_list *kvm_get_msr_index_list(void); uint64_t kvm_get_feature_msr(uint64_t msr_index); +struct kvm_cpuid2 *_kvm_get_supported_cpuid(void); struct kvm_cpuid2 *kvm_get_supported_cpuid(void); struct kvm_cpuid2 *vcpu_get_cpuid(struct kvm_vm *vm, uint32_t vcpuid); diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/testing/selftests/kvm/lib/x86_64/processor.c index 9f000dfb5594..b8921cd09ede 100644 --- a/tools/testing/selftests/kvm/lib/x86_64/processor.c +++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c @@ -772,17 +772,14 @@ static struct kvm_cpuid2 *allocate_kvm_cpuid2(void) * * Return: The supported KVM CPUID * - * Get the guest CPUID supported by KVM. + * Gets the supported guest CPUID with the KVM_GET_SUPPORTED_CPUID ioctl. */ -struct kvm_cpuid2 *kvm_get_supported_cpuid(void) +struct kvm_cpuid2 *_kvm_get_supported_cpuid(void) { - static struct kvm_cpuid2 *cpuid; + struct kvm_cpuid2 *cpuid; int ret; int kvm_fd; - if (cpuid) - return cpuid; - cpuid = allocate_kvm_cpuid2(); kvm_fd = open_kvm_dev_path_or_exit(); @@ -794,6 +791,30 @@ struct kvm_cpuid2 *kvm_get_supported_cpuid(void) return cpuid; } +/* + * KVM Supported CPUID Get + * + * Input Args: None + * + * Output Args: None + * + * Return: The supported KVM CPUID + * + * Gets the supported guest CPUID with the KVM_GET_SUPPORTED_CPUID ioctl. + * The first call creates a static allocation of CPUID for the process. + * Subsequent calls will return a pointer to the previously allocated CPUID. + */ +struct kvm_cpuid2 *kvm_get_supported_cpuid(void) +{ + static struct kvm_cpuid2 *cpuid; + + if (cpuid) + return cpuid; + + cpuid = _kvm_get_supported_cpuid(); + return cpuid; +} + /* * KVM Get MSR * From patchwork Tue Mar 1 06:03:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C082C433F5 for ; Tue, 1 Mar 2022 06:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232533AbiCAGE5 (ORCPT ); Tue, 1 Mar 2022 01:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232463AbiCAGEx (ORCPT ); Tue, 1 Mar 2022 01:04:53 -0500 Received: from mail-io1-xd49.google.com (mail-io1-xd49.google.com [IPv6:2607:f8b0:4864:20::d49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2AB060D8C for ; Mon, 28 Feb 2022 22:04:12 -0800 (PST) Received: by mail-io1-xd49.google.com with SMTP id t19-20020a6b5f13000000b0064041171126so10001039iob.10 for ; Mon, 28 Feb 2022 22:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Y2gSRLlIKfwt3PQVIyDoXWHcSD0YLnemOsWtBee5UcE=; b=O2171eiQcwgZrQdczAyEjwekP2a1oVK9UaDdJVfFrhnbKRN6EioIpb/4zBdDu+ggMt NWnYdo0lWT1+JMqj4d70p2Kd7k7GKrW1VcD1EL+s3+W5j0/EXtr3BVpgbq8yCcg14dQs ezfQtREnfgyDy+OuDbmr3tNuQNgpKStG7nNt870UmE6IRwKPSyoeW4ueHIsaLCD1C5gt Yooyb66XN11dRqz1aWasc95GN2LutdR8Nws8rg9kt7jsK9s3ykyVJOi7aisbOamUCmOF Q0KUJAxHFNakmqTug4qk6QqB/VMgYcvcddbHqjlaC5zl6TFo+EVUJebpBficaKKPymqq Upqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Y2gSRLlIKfwt3PQVIyDoXWHcSD0YLnemOsWtBee5UcE=; b=asWwR+ScZ05JXdOdyE46Gz4AxoSgTiLGzBL0cFMWaKu4UJB7Yu5j3uAg41SDZ05us6 HhEFAdEmUwiwZsSz/Vwyin82gSuQ2Yvzd/EMZoHRDMDYKHdWJ0JYMCFMFvlDh/YHqX+Z eGuXhyatnVzAY3hDMv15W8dfObutqk36LthJGL4UGlJcWo1raQMb78pdxqBkZp8M+gEI kjmi7vobr6t3KsvH+qTtpDleo56eMS9NbrNs0r/IonRT7Gumxq06BWZS+BCoyz1l3aie ctkK/HnLBetCddJPxseNhbxUgjOW3eS5/MuW6MNUpUt1SSbxP0DCGxoVSSaWL1M4Lkvh 1vog== X-Gm-Message-State: AOAM531oSi5sGFxeRY4jQpmoJH38WM4yq9wacz5L3r5+y9Sh2ji9x2rB ni3wo9Mhdj/b2myzJGKxgFBl3ofehbUNq/XBGME1fytg4+joxKdGpP/oFswvgKKxD+WgYesWVGo EUtCHQ4ywkqRgZR8gqmW9G3Yt0YUDFS3f22a6CJcjlovYN+7DYxZ6Ia4g/Q== X-Google-Smtp-Source: ABdhPJytl9V64tirtkgvEMVF0jOJofhG4nX1Vn+7CNatEitq0Vqa/Xaony2JLwHzUAK8/ew4Q3O6WUbeCj8= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6e02:1baf:b0:2c2:46eb:a074 with SMTP id n15-20020a056e021baf00b002c246eba074mr20346548ili.263.1646114652231; Mon, 28 Feb 2022 22:04:12 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:50 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-8-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 7/8] selftests: KVM: Add test for PERF_GLOBAL_CTRL VMX control MSR bits From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Test that the default behavior of KVM is to ignore userspace MSR writes and conditionally expose the "load IA32_PERF_GLOBAL_CTRL" bits in the VMX control MSRs if the guest CPUID exposes a supporting vPMU. Additionally, test that when the corresponding quirk is disabled, userspace can still clear these bits regardless of what is exposed in CPUID. Signed-off-by: Oliver Upton Reviewed-by: David Dunn --- tools/testing/selftests/kvm/.gitignore | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../kvm/x86_64/vmx_control_msrs_test.c | 160 ++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftests/kvm/.gitignore index 052ddfe4b23a..38edeace1432 100644 --- a/tools/testing/selftests/kvm/.gitignore +++ b/tools/testing/selftests/kvm/.gitignore @@ -38,6 +38,7 @@ /x86_64/userspace_msr_exit_test /x86_64/vmx_apic_access_test /x86_64/vmx_close_while_nested_test +/x86_64/vmx_control_msrs_test /x86_64/vmx_dirty_log_test /x86_64/vmx_exception_with_invalid_guest_state /x86_64/vmx_invalid_nested_guest_state diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index f7fa5655e535..a1f0c5885b6d 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -70,6 +70,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/userspace_io_test TEST_GEN_PROGS_x86_64 += x86_64/userspace_msr_exit_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_apic_access_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_close_while_nested_test +TEST_GEN_PROGS_x86_64 += x86_64/vmx_control_msrs_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_dirty_log_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_exception_with_invalid_guest_state TEST_GEN_PROGS_x86_64 += x86_64/vmx_invalid_nested_guest_state diff --git a/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c b/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c new file mode 100644 index 000000000000..4ab780483e15 --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * VMX control MSR test + * + * Copyright (C) 2022 Google LLC. + * + * Tests for KVM ownership of bits in the VMX entry/exit control MSRs. Checks + * that KVM will set owned bits where appropriate, and will not if + * KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS is disabled. + */ + +#include "kvm_util.h" +#include "vmx.h" + +#define VCPU_ID 0 + +static void get_vmx_control_msr(struct kvm_vm *vm, uint32_t msr_index, + uint32_t *low, uint32_t *high) +{ + uint64_t val; + + val = vcpu_get_msr(vm, VCPU_ID, msr_index); + *low = val; + *high = val >> 32; +} + +static void set_vmx_control_msr(struct kvm_vm *vm, uint32_t msr_index, + uint32_t low, uint32_t high) +{ + uint64_t val = (((uint64_t) high) << 32) | low; + + vcpu_set_msr(vm, VCPU_ID, msr_index, val); +} + +static void test_vmx_control_msr(struct kvm_vm *vm, uint32_t msr_index, uint32_t set, + uint32_t clear, uint32_t exp_set, uint32_t exp_clear) +{ + uint32_t low, high; + + get_vmx_control_msr(vm, msr_index, &low, &high); + + high &= ~clear; + high |= set; + + set_vmx_control_msr(vm, msr_index, low, high); + + get_vmx_control_msr(vm, msr_index, &low, &high); + ASSERT_EQ(high & exp_set, exp_set); + ASSERT_EQ(~high & exp_clear, exp_clear); +} + +static void clear_performance_monitoring_leaf(struct kvm_cpuid2 *cpuid) +{ + struct kvm_cpuid_entry2 ent = {0}; + + ent.function = 0xa; + TEST_ASSERT(set_cpuid(cpuid, &ent), + "failed to clear Architectual Performance Monitoring leaf (0xA)"); +} + +static void load_perf_global_ctrl_test(struct kvm_vm *vm) +{ + uint32_t entry_low, entry_high, exit_low, exit_high; + struct kvm_enable_cap cap = {0}; + struct kvm_cpuid2 *cpuid; + + get_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, &entry_low, &entry_high); + get_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, &exit_low, &exit_high); + + if (!(entry_high & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) || + !(exit_high & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)) { + print_skip("\"load IA32_PERF_GLOBAL_CTRL\" VM-{Entry,Exit} controls not supported"); + return; + } + + /* + * Test that KVM will set these bits regardless of userspace if the + * guest CPUID exposes a supporting vPMU. + */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, + 0, /* set */ + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, /* clear */ + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, /* exp_set */ + 0); /* exp_clear */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, + 0, /* set */ + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, /* clear */ + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, /* exp_set */ + 0); /* exp_clear */ + + /* + * Hide vPMU in CPUID + */ + cpuid = _kvm_get_supported_cpuid(); + clear_performance_monitoring_leaf(cpuid); + vcpu_set_cpuid(vm, VCPU_ID, cpuid); + free(cpuid); + + /* + * Test that KVM will clear these bits if guest CPUID does not expose a + * supporting vPMU. + */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, + 0, /* set */ + 0, /* clear */ + 0, /* exp_set */ + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL); /* exp_clear */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, + 0, /* set */ + 0, /* clear */ + 0, /* exp_set */ + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); /* exp_clear */ + + /* + * Re-enable vPMU in CPUID + */ + vcpu_set_cpuid(vm, VCPU_ID, kvm_get_supported_cpuid()); + + /* + * Disable the quirk, giving userspace control of the VMX capability + * MSRs. + */ + cap.cap = KVM_CAP_DISABLE_QUIRKS2; + cap.args[0] = KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS; + vm_enable_cap(vm, &cap); + + /* + * Test that userspace can clear these bits, even if it exposes a vPMU + * that supports IA32_PERF_GLOBAL_CTRL. + */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, + 0, /* set */ + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, /* clear */ + 0, /* exp_set */ + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL); /* exp_clear */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, + 0, /* set */ + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, /* clear */ + 0, /* exp_set */ + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); /* exp_clear */ +} + +int main(void) +{ + struct kvm_vm *vm; + + if (!kvm_check_cap(KVM_CAP_DISABLE_QUIRKS2)) { + print_skip("KVM_CAP_DISABLE_QUIRKS2 not supported"); + exit(KSFT_SKIP); + } + + nested_vmx_check_supported(); + + /* No need to run a guest for these tests */ + vm = vm_create_default(VCPU_ID, 0, NULL); + + load_perf_global_ctrl_test(vm); + + kvm_vm_free(vm); +} From patchwork Tue Mar 1 06:03:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12764174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5FEAC433FE for ; Tue, 1 Mar 2022 06:04:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232540AbiCAGE7 (ORCPT ); Tue, 1 Mar 2022 01:04:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232514AbiCAGEy (ORCPT ); Tue, 1 Mar 2022 01:04:54 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2D7460D92 for ; Mon, 28 Feb 2022 22:04:13 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id n66-20020a254045000000b0062883b59ddbso181927yba.12 for ; Mon, 28 Feb 2022 22:04:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=R9LFCj/8R7U0/GTd7qJpyU2UelQ8TY/nygE42d5f9qE=; b=fUBSH7+jK1sGBOB8u/GEXoG4oOTfdW8ES3NoUBvoYw2Cp2Pc1ubQ/UxNivIdqOotJa w92t9QSk3eR9ZsFmjjL7vZzhSikqFbo5YC6SQOayJRcvGPdlHQcV/jFEF26/HXlUkw8W J296udLWDSf0BO+pI0DZdwbE6DZeA08y1louDOgcQerBx49R3sPfcozyF3+xyZmmvYuy szIGa6W0toh0/GRVDQRNSdxNPMk7UaYejSMrhYLTJEW7qBMWrXbpm0TMI82OS2swfCWK E7npZGaYZOpsPFxiYL4ZFKaUnpwoP55UOUIFSi62jbFQvw8Qbst3vZ3hz7pFHZy7Y25g YjYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=R9LFCj/8R7U0/GTd7qJpyU2UelQ8TY/nygE42d5f9qE=; b=2/K3E0HvmEwgum81Sy//8275/2jxrIIW6jluWSC/PyjdKd8EV/MVE9KlCIvQOUf1dK /eScL6f1awrWptSR0HCi0Ii/LMvKCsSObysHoMpmV2iOs1YJC3JRDTUgZl1xxv5fmfcb pLsCPw0SM3abUc/eHGqY6+9ffzHWlZR9gD6tytnPw7dLK8LjtF1prDXRZpOruq27oZ0d ggGN8P6FOx2HKa1gDKsSapoQOfwVjEJQxqeKXGIryjrT/FWRyOIfIi5Ern/rQwa9+I6P wp9CyLpBRF3tlriOW/HuAmmucseo8xaQqiEWGwF8sFyOJBbfyWp8ChrtOuXmVWB5Kl4P afvQ== X-Gm-Message-State: AOAM532doRobUVyx1ubS6CqbCuWM/tjtlwdto+1+3eBOz+JhFY1Ac8YS lOq9u20AVKKXTr9PwKcG1xWTp/RbIqX2spEb7WiwqrfnhCqcjhiLG18gsMBbvFb8/zVaT3kgs20 Pyr0p+Sx2WecMGm7A6vfA/Dm40D7Ii9zGtauTH3V64DxH/MpnLjG5XIwksQ== X-Google-Smtp-Source: ABdhPJww0d1qwBPTz8rrlAVmKp2/n6SkSu4UykAiV1FXSfIxx+O6pkg40lvqRRMUxFe7fEB2BjvFzSxvlVw= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6902:189:b0:611:4169:48b3 with SMTP id t9-20020a056902018900b00611416948b3mr22793628ybh.18.1646114653165; Mon, 28 Feb 2022 22:04:13 -0800 (PST) Date: Tue, 1 Mar 2022 06:03:51 +0000 In-Reply-To: <20220301060351.442881-1-oupton@google.com> Message-Id: <20220301060351.442881-9-oupton@google.com> Mime-Version: 1.0 References: <20220301060351.442881-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 8/8] selftests: KVM: Add test for BNDCFGS VMX control MSR bits From: Oliver Upton To: kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , David Dunn , Oliver Upton Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Test that the default behavior of KVM is to ignore userspace MSR writes and conditionally expose the "{load,clear} IA32_BNDCFGS" bits in the VMX control MSRs if the guest CPUID exposes MPX. Additionally, test that when the corresponding quirk is disabled, userspace can still clear these bits regardless of what is exposed in CPUID. Signed-off-by: Oliver Upton --- .../selftests/kvm/include/x86_64/vmx.h | 2 + .../kvm/x86_64/vmx_control_msrs_test.c | 97 +++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/tools/testing/selftests/kvm/include/x86_64/vmx.h b/tools/testing/selftests/kvm/include/x86_64/vmx.h index 583ceb0d1457..811c66d9be74 100644 --- a/tools/testing/selftests/kvm/include/x86_64/vmx.h +++ b/tools/testing/selftests/kvm/include/x86_64/vmx.h @@ -80,6 +80,7 @@ #define VM_EXIT_SAVE_IA32_EFER 0x00100000 #define VM_EXIT_LOAD_IA32_EFER 0x00200000 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 +#define VM_EXIT_CLEAR_BNDCFGS 0x00800000 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff @@ -90,6 +91,7 @@ #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000 +#define VM_ENTRY_LOAD_BNDCFGS 0x00010000 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff diff --git a/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c b/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c index 4ab780483e15..132e7e435bfa 100644 --- a/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c +++ b/tools/testing/selftests/kvm/x86_64/vmx_control_msrs_test.c @@ -138,6 +138,102 @@ static void load_perf_global_ctrl_test(struct kvm_vm *vm) VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, /* clear */ 0, /* exp_set */ VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); /* exp_clear */ + + /* cleanup, enable the quirk again */ + cap.args[0] = 0; + vm_enable_cap(vm, &cap); +} + +static void clear_mpx_bit(struct kvm_cpuid2 *cpuid) +{ + struct kvm_cpuid_entry2 ent; + + ent = *kvm_get_supported_cpuid_index(0x7, 0x0); + ent.ebx &= ~(1u << 14); + + TEST_ASSERT(set_cpuid(cpuid, &ent), + "failed to clear CPUID.07H:EBX[14] (MPX)"); +} + +static void bndcfgs_test(struct kvm_vm *vm) +{ + uint32_t entry_low, entry_high, exit_low, exit_high; + struct kvm_enable_cap cap = {0}; + struct kvm_cpuid2 *cpuid; + + get_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, &entry_low, &entry_high); + get_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, &exit_low, &exit_high); + + if (!(entry_high & VM_ENTRY_LOAD_BNDCFGS) || + !(exit_high & VM_EXIT_CLEAR_BNDCFGS)) { + print_skip("\"load/clear IA32_BNDCFGS\" VM-{Entry,Exit} controls not supported"); + return; + } + + /* + * Test that KVM will set these bits regardless of userspace if the + * guest CPUID exposes MPX. + */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, + 0, /* set */ + VM_ENTRY_LOAD_BNDCFGS, /* clear */ + VM_ENTRY_LOAD_BNDCFGS, /* exp_set */ + 0); /* exp_clear */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, + 0, /* set */ + VM_EXIT_CLEAR_BNDCFGS, /* clear */ + VM_EXIT_CLEAR_BNDCFGS, /* exp_set */ + 0); /* exp_clear */ + + /* + * Hide MPX in CPUID + */ + cpuid = _kvm_get_supported_cpuid(); + clear_mpx_bit(cpuid); + vcpu_set_cpuid(vm, VCPU_ID, cpuid); + free(cpuid); + + /* + * Test that KVM will clear these bits if the guest CPUID does not + * expose MPX + */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, + 0, /* set */ + 0, /* clear */ + 0, /* exp_set */ + VM_ENTRY_LOAD_BNDCFGS); /* exp_clear */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, + 0, /* set */ + 0, /* clear */ + 0, /* exp_set */ + VM_EXIT_CLEAR_BNDCFGS); /* exp_clear */ + + /* + * Re-enable MPX in CPUID + */ + vcpu_set_cpuid(vm, VCPU_ID, kvm_get_supported_cpuid()); + + /* + * Disable the quirk, giving userspace control of the VMX capability + * MSRs. + */ + cap.cap = KVM_CAP_DISABLE_QUIRKS2; + cap.args[0] = KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS; + vm_enable_cap(vm, &cap); + + /* + * Test that userspace can clear these bits, even if it exposes MPX. + */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_ENTRY_CTLS, + 0, /* set */ + VM_ENTRY_LOAD_BNDCFGS, /* clear */ + 0, /* exp_set */ + VM_ENTRY_LOAD_BNDCFGS); /* exp_clear */ + test_vmx_control_msr(vm, MSR_IA32_VMX_TRUE_EXIT_CTLS, + 0, /* set */ + VM_EXIT_CLEAR_BNDCFGS, /* clear */ + 0, /* exp_set */ + VM_EXIT_CLEAR_BNDCFGS); /* exp_clear */ } int main(void) @@ -155,6 +251,7 @@ int main(void) vm = vm_create_default(VCPU_ID, 0, NULL); load_perf_global_ctrl_test(vm); + bndcfgs_test(vm); kvm_vm_free(vm); }