From patchwork Fri Mar 4 10:03:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12768882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1AD44C433EF for ; Fri, 4 Mar 2022 10:03:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JJa0yedwnR0M2DAruXsMc8mFeBnTBQg/k/oPjQIAjlM=; b=AeHiRKvGVgFJrT 7lw0YegXcHB6Bz8mb7ZrVQ03ygpHIBb5qfS6AtVC1QzsR1yBkONuXNbiiiLhLFfuA3mThbyBFNPnp 3k1E8W06O9P8w97A/oIVzwxkSme+7/kEeYabn2V/293jz/Z6ZUPm17WsQ2isB90g1XZNFYlJG1SGs FmuKOHB+i3AOlZ/QsiMAtCDB8flytBAq298zjjz8qR2CQJrBDcPbUBc9vM3/NRr0Ls9JtGzJDW7QY muQvl31vMDT4ZID5Gm3jkYnXcOL9DW9dSSvl8ZGNOc0pPaxFSPcvDo/HC60tA8ue7UpAPt1leSEjD 4gRcP5xWOZYUdA7eMTdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ4me-009TI8-74; Fri, 04 Mar 2022 10:03:36 +0000 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ4mY-009TFT-Ai for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 10:03:31 +0000 Received: by mail-pg1-x530.google.com with SMTP id 195so7109923pgc.6 for ; Fri, 04 Mar 2022 02:03:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/wivmtaq/SOM50t59wI6fLzJlaXtHmkBr6jDahJcOY4=; b=bGsRhcabvtlSfwd8B3Hc862NImw4ysYnY4vIXQXnY8c0yLMXuW0PWOkCVaYH0JddgX 7XaSpfnyNR176s48aOfJYFXy71qH1fJ3EKDwd49Xj3F5Y3iKd0WHgQkui2hDyZDse7VV HEq/JvcnB7tT50djw2mSzJSMbXst7GcASnJQwJe0mVpIA3Z6Ze0q1LfCirUuWD/0wUR0 B2ngyyebL8s4qkERUEDqCqZ7Go8vt76ElCnjnfNliAbA6d175ipCZTEec27TjBdsgtxB 1blU1E5FrL/PqUUV+WIHLFHThitCK4qGoqsxjnFgwJfsw1vMs+rpYR5QGKQJjZNGY8YF y+og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/wivmtaq/SOM50t59wI6fLzJlaXtHmkBr6jDahJcOY4=; b=P6l7zeK/QxkIQrJ6UAbQF7dkwPcCgA+HZoStoeCgcrNlslvylIwFiWYfmvw78BxvH/ LFVvL0Z8CQ3XytS8Pgo5/txQYB3dB8pneUNQ73BxxdAEqHIZPzyfWp13FvXdoqOUbj9N 17t74wzcvPtUR7evA/beqoGgixQvTbtGYXEaACBGrCmcACaErkfSCM6SIMRU8aMhqaHE z+aBJ/etvyhvKdv+XqPIvZxMrHKaV1d34Ul/CrVXDtAoSKuylip0Lwa72rVlc8oTEsLm SYaFwdC3acVWXbGn0zZxCo0pYyAbFJN5UXtxLrWTqgE8wCX3ZxVnuN4XKFh2+GoNzh5t dfFw== X-Gm-Message-State: AOAM531gZanbxNSKcj21xHkHpe6O08nU32/tpjAB3DGDUZAtBbWx7yFo wm4A2rYhO4bLlijzCpwK2DrGpA== X-Google-Smtp-Source: ABdhPJyn7J5CnDAcxUu7niaATceQ6lk+NyKYqye5kYn0ltG7hPXizvd7T07ZbTlOO9WCND1NeREjGA== X-Received: by 2002:a63:c61:0:b0:370:592b:3ad1 with SMTP id 33-20020a630c61000000b00370592b3ad1mr33584816pgm.240.1646388209553; Fri, 04 Mar 2022 02:03:29 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id j8-20020a056a00174800b004f26d3f5b03sm5461605pfc.39.2022.03.04.02.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:03:29 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v2 1/5] clk: sifive: duplicate the macro definitions for the time being Date: Fri, 4 Mar 2022 18:03:17 +0800 Message-Id: <8cfd57f01cfb59adb716eb13ca0c8250c246dcb2.1646388139.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_020330_440265_BF99DCE8 X-CRM114-Status: GOOD ( 11.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This is a temporary patch in whole patch set. We are going to change the macro name in dt-binding, in order to avoid breaking the driver build and git bisect, add these macro definitions for the time being, and we will remove them later. Signed-off-by: Zong Li --- drivers/clk/sifive/fu540-prci.c | 6 +++++- drivers/clk/sifive/fu740-prci.c | 11 ++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 29bab915003c..9e13119066eb 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -20,9 +20,13 @@ #include -#include "fu540-prci.h" #include "sifive-prci.h" +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data __prci_corepll_data = { diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 53f6e00a03b9..7141a22d90e3 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -8,9 +8,18 @@ #include -#include "fu540-prci.h" #include "sifive-prci.h" +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_DVFSCOREPLL 3 +#define PRCI_CLK_HFPCLKPLL 4 +#define PRCI_CLK_CLTXPLL 5 +#define PRCI_CLK_TLCLK 6 +#define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIE_AUX 8 + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data __prci_corepll_data = { From patchwork Fri Mar 4 10:03:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12768883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 518FDC433F5 for ; Fri, 4 Mar 2022 10:03:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=12KHvbwWD2e+BTmKw6U7Bp0tjrUS8vrmOwAJkCo9W6Y=; b=Ei0RonAPLyFxnW j/8EA/VRGARAaEwZgefB+1ZAGtuD3TKh/MXveIBzFIHKWdWI7PJcj0y8gU2ECnilmumy44B99GHG3 /4wietcaBFhJipo4FlpFyfXKvKSPT4UnUUqdwWwqRT3KolWs6RNkTTieA6oXx1eKCg1r6t9hrwlRb 7XEHbFWFlT/HjMAZ1gizC8pB1FBzzteVi+li285fkChCbbcmuM5BcTzO0+R+i1VzQQozhZgpreUg9 8DXUmfZEWH7HqGMMnNynzUh3npEMNtRjVyr/GWjN+vTbud1WdvIGUwkkhkAb83d2Oj5iXXtNTgKHu epeX7tzSEylHEwBnhQlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ4mk-009TLw-Tl; Fri, 04 Mar 2022 10:03:43 +0000 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQ4mb-009TGP-6R for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 10:03:34 +0000 Received: by mail-pf1-x436.google.com with SMTP id d187so7202023pfa.10 for ; Fri, 04 Mar 2022 02:03:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YJQeczGCyde6fs+sGcXvqejtqL/oWjg9SsCj9ixzkS8=; b=h2zhJkz4ejNA9UZn2qKXICuQVZ5crdHCD3aL0FrHrgAipBUZruvyGxutNpSmGwvz4h q2FYeIflyxi4WjnT1UHwy9sb7CPF0FWUfW2O1BijSPjrnOD1yVt7ojVuUP/v0+2TCfAL rs1N2rEApj2CSLe+gsoapMAQO4EkBHtlllYjOEFKYvfb/NDrscO1HTxxTeVEix4iUUa8 3h6v4pv7OGj36rQJ/IikLWbPoEHIc9Vk4xXIapdKiWk3BTZEVK92IhGdRfShRPWFcngL +qGv/J6YvIILTX4Ob/dGgmHl/zUSRENL5K3ZB7dRlHITceMzo3AJ0CfM+HNbSbyHDjsL aBHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YJQeczGCyde6fs+sGcXvqejtqL/oWjg9SsCj9ixzkS8=; b=1SJ5yN6d8G2uoNg8tjNHAY9uH5Dtq0XreoJLq4Vjc8JJycbDbKSJstRUdK1lNqi52c DN/XkMSrxGDTOKGRwqqjnmWB32gP3AovUqzO7c+CsSkpRQsqh4+AzxmzqwNRvSurdGYc d1zlccHXqHz+gDJkiLsgqmyXcqztCpcU2zwgt0rxte9Qpi1ZK/vaqkByffoaAg67tKjg YrRYk/R8UKi4iMFh2ziRdiEqdPdwHMNuD7oFPs/Jg8sRSstWwAM0QvvPwRtRMw1b8ojk T27psN7OV+akGZ+XvmleB9uByTuJBU8lRlwYyDlGJOHT3W50Pc8M7c/cud9G4LqOUIxa QxLg== X-Gm-Message-State: AOAM532xYCxnny+eVNBjMqbC2tzx3+ueCCCObCwwXH/nnL8XKTbsXVZi kTI7BVqyAYprB71ecRL+Br5p1kz7D1W0JA== X-Google-Smtp-Source: ABdhPJw8Wc3eKaZofkKh8W3VECbyxA6H4ZwEDiEWFzFFuLSB0crgYHjPTZ+vrcmF6tTgikJwX+lEtw== X-Received: by 2002:a63:85c6:0:b0:37e:61ff:863e with SMTP id u189-20020a6385c6000000b0037e61ff863emr602220pgd.412.1646388212452; Fri, 04 Mar 2022 02:03:32 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id j8-20020a056a00174800b004f26d3f5b03sm5461605pfc.39.2022.03.04.02.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:03:31 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li , Rob Herring , Palmer Dabbelt Subject: [PATCH v2 2/5] dt-bindings: change the macro name of prci in header files and example Date: Fri, 4 Mar 2022 18:03:18 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_020333_277014_9EF7E300 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We currently change the macro name for fu540 and fu740 by adding the prefix respectively, the dt-bindings should be modified as well. Signed-off-by: Zong Li Acked-by: Rob Herring Acked-by: Palmer Dabbelt --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 2 +- .../bindings/pci/sifive,fu740-pcie.yaml | 2 +- .../bindings/serial/sifive-serial.yaml | 2 +- include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++---- include/dt-bindings/clock/sifive-fu740-prci.h | 18 +++++++++--------- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index 427c5873f96a..939e31c48081 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -79,7 +79,7 @@ examples: interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>, <21>, <22>; reg = <0x10060000 0x1000>; - clocks = <&tlclk PRCI_CLK_TLCLK>; + clocks = <&tlclk FU540_PRCI_CLK_TLCLK>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml index 392f0ab488c2..195e6afeb169 100644 --- a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -104,7 +104,7 @@ examples: <0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; - clocks = <&prci PRCI_CLK_PCIE_AUX>; + clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; resets = <&prci 4>; pwren-gpios = <&gpio 5 0>; reset-gpios = <&gpio 8 0>; diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 09aae43f65a7..b0a8871e3641 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -59,7 +59,7 @@ examples: interrupt-parent = <&plic0>; interrupts = <80>; reg = <0x10010000 0x1000>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; }; ... diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h index 3b21d0522c91..5af372e8385f 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -10,9 +10,9 @@ /* Clock indexes for use by Device Tree data and the PRCI driver */ -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 +#define FU540_PRCI_CLK_COREPLL 0 +#define FU540_PRCI_CLK_DDRPLL 1 +#define FU540_PRCI_CLK_GEMGXLPLL 2 +#define FU540_PRCI_CLK_TLCLK 3 #endif diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h index 7899b7fee7db..672bdadbf6c0 100644 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ b/include/dt-bindings/clock/sifive-fu740-prci.h @@ -11,14 +11,14 @@ /* Clock indexes for use by Device Tree data and the PRCI driver */ -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_DVFSCOREPLL 3 -#define PRCI_CLK_HFPCLKPLL 4 -#define PRCI_CLK_CLTXPLL 5 -#define PRCI_CLK_TLCLK 6 -#define PRCI_CLK_PCLK 7 -#define PRCI_CLK_PCIE_AUX 8 +#define FU740_PRCI_CLK_COREPLL 0 +#define FU740_PRCI_CLK_DDRPLL 1 +#define FU740_PRCI_CLK_GEMGXLPLL 2 +#define FU740_PRCI_CLK_DVFSCOREPLL 3 +#define FU740_PRCI_CLK_HFPCLKPLL 4 +#define FU740_PRCI_CLK_CLTXPLL 5 +#define FU740_PRCI_CLK_TLCLK 6 +#define FU740_PRCI_CLK_PCLK 7 +#define FU740_PRCI_CLK_PCIE_AUX 8 #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ From patchwork Fri Mar 4 10:03:19 2022 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id j8-20020a056a00174800b004f26d3f5b03sm5461605pfc.39.2022.03.04.02.03.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:03:34 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li , Palmer Dabbelt Subject: [PATCH v2 3/5] riscv: dts: Change the macro name of prci in each device node Date: Fri, 4 Mar 2022 18:03:19 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_020336_585471_24E3FE62 X-CRM114-Status: UNSURE ( 9.59 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We currently change the macro name for fu540 and fu740 by adding the prefix respectively, these marcos are referenced by some device nodes, they should be modified as well. Signed-off-by: Zong Li Acked-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 22 +++++++++--------- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 26 +++++++++++----------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 3eef52b1a59b..aad45d7f498f 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -164,7 +164,7 @@ uart0: serial@10010000 { reg = <0x0 0x10010000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <4>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; status = "disabled"; }; dma: dma@3000000 { @@ -180,7 +180,7 @@ uart1: serial@10011000 { reg = <0x0 0x10011000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <5>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; status = "disabled"; }; i2c0: i2c@10030000 { @@ -188,7 +188,7 @@ i2c0: i2c@10030000 { reg = <0x0 0x10030000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <50>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; reg-shift = <2>; reg-io-width = <1>; #address-cells = <1>; @@ -201,7 +201,7 @@ qspi0: spi@10040000 { <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -212,7 +212,7 @@ qspi1: spi@10041000 { <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -222,7 +222,7 @@ qspi2: spi@10050000 { reg = <0x0 0x10050000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <6>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -235,8 +235,8 @@ eth0: ethernet@10090000 { <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; + clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>, + <&prci FU540_PRCI_CLK_GEMGXLPLL>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -246,7 +246,7 @@ pwm0: pwm@10020000 { reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <42>, <43>, <44>, <45>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -255,7 +255,7 @@ pwm1: pwm@10021000 { reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <46>, <47>, <48>, <49>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -281,7 +281,7 @@ gpio: gpio@10060000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_TLCLK>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; status = "disabled"; }; }; diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 8464b0e3c887..7b77c13496d8 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -166,7 +166,7 @@ uart0: serial@10010000 { reg = <0x0 0x10010000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <39>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; uart1: serial@10011000 { @@ -174,7 +174,7 @@ uart1: serial@10011000 { reg = <0x0 0x10011000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <40>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; i2c0: i2c@10030000 { @@ -182,7 +182,7 @@ i2c0: i2c@10030000 { reg = <0x0 0x10030000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <52>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; reg-shift = <2>; reg-io-width = <1>; #address-cells = <1>; @@ -194,7 +194,7 @@ i2c1: i2c@10031000 { reg = <0x0 0x10031000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <53>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; reg-shift = <2>; reg-io-width = <1>; #address-cells = <1>; @@ -207,7 +207,7 @@ qspi0: spi@10040000 { <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <41>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -218,7 +218,7 @@ qspi1: spi@10041000 { <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <42>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -228,7 +228,7 @@ spi0: spi@10050000 { reg = <0x0 0x10050000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <43>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -241,8 +241,8 @@ eth0: ethernet@10090000 { <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; + clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, + <&prci FU740_PRCI_CLK_GEMGXLPLL>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -252,7 +252,7 @@ pwm0: pwm@10020000 { reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <44>, <45>, <46>, <47>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -261,7 +261,7 @@ pwm1: pwm@10021000 { reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <48>, <49>, <50>, <51>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -287,7 +287,7 @@ gpio: gpio@10060000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; pcie@e00000000 { @@ -316,7 +316,7 @@ pcie@e00000000 { <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; clock-names = "pcie_aux"; - clocks = <&prci PRCI_CLK_PCIE_AUX>; + clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; pwren-gpios = <&gpio 5 0>; reset-gpios = <&gpio 8 0>; resets = <&prci 4>; From patchwork Fri Mar 4 10:03:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12768885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C0FCC433EF for ; Fri, 4 Mar 2022 10:04:07 +0000 (UTC) DKIM-Signature: v=1; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id j8-20020a056a00174800b004f26d3f5b03sm5461605pfc.39.2022.03.04.02.03.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:03:37 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li , Palmer Dabbelt Subject: [PATCH v2 4/5] clk: sifive: Add SoCs prefix in each SoCs-dependent data Date: Fri, 4 Mar 2022 18:03:20 +0800 Message-Id: <7728ef662c59449ce954b1b62c6ad5241e07adfb.1646388139.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_020339_419344_D5BC2B32 X-CRM114-Status: GOOD ( 14.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch is prerequisite for moving SoCs C files into SoCs header files. Currently, fu540-prci.c and fu740-prci.c use same names for several macro definitions and variables, it would cause redefinition error when we trying to include all stuff in sifive-prci.c. In this patch, we also remove the temporary macro definitions which are added by previous patch. Signed-off-by: Zong Li Acked-by: Palmer Dabbelt --- drivers/clk/sifive/fu540-prci.c | 29 +++++++---------- drivers/clk/sifive/fu740-prci.c | 56 ++++++++++++++------------------- 2 files changed, 35 insertions(+), 50 deletions(-) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 9e13119066eb..672c782ad604 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * Copyright (C) 2018-2019 Wesley Terpstra * Copyright (C) 2018-2019 Paul Walmsley - * Copyright (C) 2020 Zong Li + * Copyright (C) 2020-2022 Zong Li * * The FU540 PRCI implements clock and reset control for the SiFive * FU540-C000 chip. This driver assumes that it has sole control @@ -22,26 +22,21 @@ #include "sifive-prci.h" -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - /* PRCI integration data for each WRPLL instance */ -static struct __prci_wrpll_data __prci_corepll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, .enable_bypass = sifive_prci_coreclksel_use_hfclk, .disable_bypass = sifive_prci_coreclksel_use_corepll, }; -static struct __prci_wrpll_data __prci_ddrpll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, }; -static struct __prci_wrpll_data __prci_gemgxlpll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, }; @@ -67,25 +62,25 @@ static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu540[] = { - [PRCI_CLK_COREPLL] = { + [FU540_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &__prci_corepll_data, + .pwd = &sifive_fu540_prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU540_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, - .pwd = &__prci_ddrpll_data, + .pwd = &sifive_fu540_prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU540_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &__prci_gemgxlpll_data, + .pwd = &sifive_fu540_prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU540_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu540_prci_tlclksel_clk_ops, diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 7141a22d90e3..f27d1a42d946 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 SiFive, Inc. - * Copyright (C) 2020 Zong Li + * Copyright (C) 2020-2022 SiFive, Inc. + * Copyright (C) 2020-2022 Zong Li */ #include @@ -10,50 +10,40 @@ #include "sifive-prci.h" -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_DVFSCOREPLL 3 -#define PRCI_CLK_HFPCLKPLL 4 -#define PRCI_CLK_CLTXPLL 5 -#define PRCI_CLK_TLCLK 6 -#define PRCI_CLK_PCLK 7 -#define PRCI_CLK_PCIE_AUX 8 - /* PRCI integration data for each WRPLL instance */ -static struct __prci_wrpll_data __prci_corepll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, .enable_bypass = sifive_prci_coreclksel_use_hfclk, .disable_bypass = sifive_prci_coreclksel_use_final_corepll, }; -static struct __prci_wrpll_data __prci_ddrpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, }; -static struct __prci_wrpll_data __prci_gemgxlpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, }; -static struct __prci_wrpll_data __prci_dvfscorepll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, .enable_bypass = sifive_prci_corepllsel_use_corepll, .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, }; -static struct __prci_wrpll_data __prci_hfpclkpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, }; -static struct __prci_wrpll_data __prci_cltxpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, }; @@ -89,53 +79,53 @@ static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu740[] = { - [PRCI_CLK_COREPLL] = { + [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_corepll_data, + .pwd = &sifive_fu740_prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU740_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_ro_clk_ops, - .pwd = &__prci_ddrpll_data, + .pwd = &sifive_fu740_prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU740_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_gemgxlpll_data, + .pwd = &sifive_fu740_prci_gemgxlpll_data, }, - [PRCI_CLK_DVFSCOREPLL] = { + [FU740_PRCI_CLK_DVFSCOREPLL] = { .name = "dvfscorepll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_dvfscorepll_data, + .pwd = &sifive_fu740_prci_dvfscorepll_data, }, - [PRCI_CLK_HFPCLKPLL] = { + [FU740_PRCI_CLK_HFPCLKPLL] = { .name = "hfpclkpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_hfpclkpll_data, + .pwd = &sifive_fu740_prci_hfpclkpll_data, }, - [PRCI_CLK_CLTXPLL] = { + [FU740_PRCI_CLK_CLTXPLL] = { .name = "cltxpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_cltxpll_data, + .pwd = &sifive_fu740_prci_cltxpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU740_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu740_prci_tlclksel_clk_ops, }, - [PRCI_CLK_PCLK] = { + [FU740_PRCI_CLK_PCLK] = { .name = "pclk", .parent_name = "hfpclkpll", .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, - [PRCI_CLK_PCIE_AUX] = { + [FU740_PRCI_CLK_PCIE_AUX] = { .name = "pcie_aux", .parent_name = "hfclk", .ops = &sifive_fu740_prci_pcie_aux_clk_ops, From patchwork Fri Mar 4 10:03:21 2022 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id j8-20020a056a00174800b004f26d3f5b03sm5461605pfc.39.2022.03.04.02.03.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:03:40 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li , Palmer Dabbelt Subject: [PATCH v2 5/5] clk: sifive: Move all stuff into SoCs header files from C files Date: Fri, 4 Mar 2022 18:03:21 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_020342_306594_8BF50EF9 X-CRM114-Status: GOOD ( 18.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Improve PRCI driver to reduce the complexity, we remove the SoCs C files by putting all stuff in each SoCs header files, and include these SoCs-specific header files in core of PRCI. It can also avoid the W=1 kernel build warnings about variable defined but not used [-Wunused-const-variable=], like commit 487dc7bb6a0c ("clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used") does. Signed-off-by: Zong Li Suggested-by: Lee Jones Reviewed-by: Lee Jones Acked-by: Palmer Dabbelt --- drivers/clk/sifive/Makefile | 2 +- drivers/clk/sifive/fu540-prci.c | 88 -------------------- drivers/clk/sifive/fu540-prci.h | 91 ++++++++++++++++++++- drivers/clk/sifive/fu740-prci.c | 133 ------------------------------- drivers/clk/sifive/fu740-prci.h | 130 +++++++++++++++++++++++++++++- drivers/clk/sifive/sifive-prci.c | 5 -- 6 files changed, 214 insertions(+), 235 deletions(-) delete mode 100644 drivers/clk/sifive/fu540-prci.c delete mode 100644 drivers/clk/sifive/fu740-prci.c diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index 7b06fc04e6b3..efdf01f1c8d5 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o +obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c deleted file mode 100644 index 672c782ad604..000000000000 --- a/drivers/clk/sifive/fu540-prci.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018-2022 SiFive, Inc. - * Copyright (C) 2018-2019 Wesley Terpstra - * Copyright (C) 2018-2019 Paul Walmsley - * Copyright (C) 2020-2022 Zong Li - * - * The FU540 PRCI implements clock and reset control for the SiFive - * FU540-C000 chip. This driver assumes that it has sole control - * over all PRCI resources. - * - * This driver is based on the PRCI driver written by Wesley Terpstra: - * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 - * - * References: - * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" - */ - -#include - -#include - -#include "sifive-prci.h" - -/* PRCI integration data for each WRPLL instance */ - -static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { - .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_coreclksel_use_hfclk, - .disable_bypass = sifive_prci_coreclksel_use_corepll, -}; - -static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { - .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { - .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, - .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, -}; - -/* Linux clock framework integration */ - -static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = { - .set_rate = sifive_prci_wrpll_set_rate, - .round_rate = sifive_prci_wrpll_round_rate, - .recalc_rate = sifive_prci_wrpll_recalc_rate, - .enable = sifive_prci_clock_enable, - .disable = sifive_prci_clock_disable, - .is_enabled = sifive_clk_is_enabled, -}; - -static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = { - .recalc_rate = sifive_prci_wrpll_recalc_rate, -}; - -static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { - .recalc_rate = sifive_prci_tlclksel_recalc_rate, -}; - -/* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] = { - [FU540_PRCI_CLK_COREPLL] = { - .name = "corepll", - .parent_name = "hfclk", - .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &sifive_fu540_prci_corepll_data, - }, - [FU540_PRCI_CLK_DDRPLL] = { - .name = "ddrpll", - .parent_name = "hfclk", - .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, - .pwd = &sifive_fu540_prci_ddrpll_data, - }, - [FU540_PRCI_CLK_GEMGXLPLL] = { - .name = "gemgxlpll", - .parent_name = "hfclk", - .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &sifive_fu540_prci_gemgxlpll_data, - }, - [FU540_PRCI_CLK_TLCLK] = { - .name = "tlclk", - .parent_name = "corepll", - .ops = &sifive_fu540_prci_tlclksel_clk_ops, - }, -}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h index c220677dc010..e0173324f3c5 100644 --- a/drivers/clk/sifive/fu540-prci.h +++ b/drivers/clk/sifive/fu540-prci.h @@ -1,16 +1,99 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 SiFive, Inc. - * Zong Li + * Copyright (C) 2018-2021 SiFive, Inc. + * Copyright (C) 2018-2019 Wesley Terpstra + * Copyright (C) 2018-2019 Paul Walmsley + * Copyright (C) 2020-2021 Zong Li + * + * The FU540 PRCI implements clock and reset control for the SiFive + * FU540-C000 chip. This driver assumes that it has sole control + * over all PRCI resources. + * + * This driver is based on the PRCI driver written by Wesley Terpstra: + * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 + * + * References: + * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" */ #ifndef __SIFIVE_CLK_FU540_PRCI_H #define __SIFIVE_CLK_FU540_PRCI_H + +#include + +#include + #include "sifive-prci.h" -#define NUM_CLOCK_FU540 4 +/* PRCI integration data for each WRPLL instance */ + +static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_coreclksel_use_hfclk, + .disable_bypass = sifive_prci_coreclksel_use_corepll, +}; + +static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, +}; + +/* Linux clock framework integration */ + +static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = { + .set_rate = sifive_prci_wrpll_set_rate, + .round_rate = sifive_prci_wrpll_round_rate, + .recalc_rate = sifive_prci_wrpll_recalc_rate, + .enable = sifive_prci_clock_enable, + .disable = sifive_prci_clock_disable, + .is_enabled = sifive_clk_is_enabled, +}; + +static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = { + .recalc_rate = sifive_prci_wrpll_recalc_rate, +}; + +static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { + .recalc_rate = sifive_prci_tlclksel_recalc_rate, +}; + +/* List of clock controls provided by the PRCI */ +static struct __prci_clock __prci_init_clocks_fu540[] = { + [FU540_PRCI_CLK_COREPLL] = { + .name = "corepll", + .parent_name = "hfclk", + .ops = &sifive_fu540_prci_wrpll_clk_ops, + .pwd = &sifive_fu540_prci_corepll_data, + }, + [FU540_PRCI_CLK_DDRPLL] = { + .name = "ddrpll", + .parent_name = "hfclk", + .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, + .pwd = &sifive_fu540_prci_ddrpll_data, + }, + [FU540_PRCI_CLK_GEMGXLPLL] = { + .name = "gemgxlpll", + .parent_name = "hfclk", + .ops = &sifive_fu540_prci_wrpll_clk_ops, + .pwd = &sifive_fu540_prci_gemgxlpll_data, + }, + [FU540_PRCI_CLK_TLCLK] = { + .name = "tlclk", + .parent_name = "corepll", + .ops = &sifive_fu540_prci_tlclksel_clk_ops, + }, +}; -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; +static const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; #endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c deleted file mode 100644 index f27d1a42d946..000000000000 --- a/drivers/clk/sifive/fu740-prci.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2022 SiFive, Inc. - * Copyright (C) 2020-2022 Zong Li - */ - -#include - -#include - -#include "sifive-prci.h" - -/* PRCI integration data for each WRPLL instance */ - -static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { - .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_coreclksel_use_hfclk, - .disable_bypass = sifive_prci_coreclksel_use_final_corepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { - .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { - .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, - .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { - .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_corepllsel_use_corepll, - .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { - .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, - .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, - .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { - .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, - .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, -}; - -/* Linux clock framework integration */ - -static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = { - .set_rate = sifive_prci_wrpll_set_rate, - .round_rate = sifive_prci_wrpll_round_rate, - .recalc_rate = sifive_prci_wrpll_recalc_rate, - .enable = sifive_prci_clock_enable, - .disable = sifive_prci_clock_disable, - .is_enabled = sifive_clk_is_enabled, -}; - -static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = { - .recalc_rate = sifive_prci_wrpll_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = { - .recalc_rate = sifive_prci_tlclksel_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { - .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { - .enable = sifive_prci_pcie_aux_clock_enable, - .disable = sifive_prci_pcie_aux_clock_disable, - .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, -}; - -/* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { - [FU740_PRCI_CLK_COREPLL] = { - .name = "corepll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_corepll_data, - }, - [FU740_PRCI_CLK_DDRPLL] = { - .name = "ddrpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_ro_clk_ops, - .pwd = &sifive_fu740_prci_ddrpll_data, - }, - [FU740_PRCI_CLK_GEMGXLPLL] = { - .name = "gemgxlpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_gemgxlpll_data, - }, - [FU740_PRCI_CLK_DVFSCOREPLL] = { - .name = "dvfscorepll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_dvfscorepll_data, - }, - [FU740_PRCI_CLK_HFPCLKPLL] = { - .name = "hfpclkpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_hfpclkpll_data, - }, - [FU740_PRCI_CLK_CLTXPLL] = { - .name = "cltxpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_cltxpll_data, - }, - [FU740_PRCI_CLK_TLCLK] = { - .name = "tlclk", - .parent_name = "corepll", - .ops = &sifive_fu740_prci_tlclksel_clk_ops, - }, - [FU740_PRCI_CLK_PCLK] = { - .name = "pclk", - .parent_name = "hfpclkpll", - .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, - }, - [FU740_PRCI_CLK_PCIE_AUX] = { - .name = "pcie_aux", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_pcie_aux_clk_ops, - }, -}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h index 511a0bf7ba2b..f31cd30fc395 100644 --- a/drivers/clk/sifive/fu740-prci.h +++ b/drivers/clk/sifive/fu740-prci.h @@ -1,17 +1,139 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 SiFive, Inc. - * Zong Li + * Copyright (C) 2020-2021 SiFive, Inc. + * Copyright (C) 2020-2021 Zong Li */ #ifndef __SIFIVE_CLK_FU740_PRCI_H #define __SIFIVE_CLK_FU740_PRCI_H +#include + +#include + #include "sifive-prci.h" -#define NUM_CLOCK_FU740 9 +/* PRCI integration data for each WRPLL instance */ + +static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_coreclksel_use_hfclk, + .disable_bypass = sifive_prci_coreclksel_use_final_corepll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { + .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_corepllsel_use_corepll, + .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { + .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, + .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, + .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { + .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, + .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, +}; + +/* Linux clock framework integration */ + +static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = { + .set_rate = sifive_prci_wrpll_set_rate, + .round_rate = sifive_prci_wrpll_round_rate, + .recalc_rate = sifive_prci_wrpll_recalc_rate, + .enable = sifive_prci_clock_enable, + .disable = sifive_prci_clock_disable, + .is_enabled = sifive_clk_is_enabled, +}; -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; +static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = { + .recalc_rate = sifive_prci_wrpll_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = { + .recalc_rate = sifive_prci_tlclksel_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { + .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { + .enable = sifive_prci_pcie_aux_clock_enable, + .disable = sifive_prci_pcie_aux_clock_disable, + .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, +}; + +/* List of clock controls provided by the PRCI */ +static struct __prci_clock __prci_init_clocks_fu740[] = { + [FU740_PRCI_CLK_COREPLL] = { + .name = "corepll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_corepll_data, + }, + [FU740_PRCI_CLK_DDRPLL] = { + .name = "ddrpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_ro_clk_ops, + .pwd = &sifive_fu740_prci_ddrpll_data, + }, + [FU740_PRCI_CLK_GEMGXLPLL] = { + .name = "gemgxlpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_gemgxlpll_data, + }, + [FU740_PRCI_CLK_DVFSCOREPLL] = { + .name = "dvfscorepll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_dvfscorepll_data, + }, + [FU740_PRCI_CLK_HFPCLKPLL] = { + .name = "hfpclkpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_hfpclkpll_data, + }, + [FU740_PRCI_CLK_CLTXPLL] = { + .name = "cltxpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_cltxpll_data, + }, + [FU740_PRCI_CLK_TLCLK] = { + .name = "tlclk", + .parent_name = "corepll", + .ops = &sifive_fu740_prci_tlclksel_clk_ops, + }, + [FU740_PRCI_CLK_PCLK] = { + .name = "pclk", + .parent_name = "hfpclkpll", + .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, + }, + [FU740_PRCI_CLK_PCIE_AUX] = { + .name = "pcie_aux", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_pcie_aux_clk_ops, + }, +}; static const struct prci_clk_desc prci_clk_fu740 = { .clks = __prci_init_clocks_fu740, diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 80a288c59e56..916d2fc28b9c 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -12,11 +12,6 @@ #include "fu540-prci.h" #include "fu740-prci.h" -static const struct prci_clk_desc prci_clk_fu540 = { - .clks = __prci_init_clocks_fu540, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), -}; - /* * Private functions */