From patchwork Fri Mar 4 10:10:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12768900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50E18C433EF for ; Fri, 4 Mar 2022 10:10:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239520AbiCDKLb (ORCPT ); Fri, 4 Mar 2022 05:11:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239508AbiCDKL3 (ORCPT ); Fri, 4 Mar 2022 05:11:29 -0500 Received: from mail-oi1-x22f.google.com (mail-oi1-x22f.google.com [IPv6:2607:f8b0:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 048DA1A906C for ; Fri, 4 Mar 2022 02:10:42 -0800 (PST) Received: by mail-oi1-x22f.google.com with SMTP id l25so7360191oic.13 for ; Fri, 04 Mar 2022 02:10:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W88BFAMfIQPlzsE5Ded5mhnnTZPYQAXRUS4xOsxlGF8=; b=Z7FrQFwP4mQzZlkB+t/MUGoPQiN5FpXuFBrVMEGTrFHdsP/Ku0wM0ctZfEwhJ/TcCo YIgllBiFTU9Y5Bn64UNQNHSKbiXZfylJVAUjWeqlgG8Exo5pqex4c82ztKsGhkyX7ytW qk4he5M4sfasojeIafs3e4J/sLJ97UOqm7Xv9KH6t3FwFSafBfAedwNNgML2e6ahZKRm pGioqd6n1m1vQCCUgC0NAW4MQIlkV6EHbIqLbGgML5tUScx5zcLTxqSrGvx30Moe6IbC IIHPSztNrFaiAQBeve2GA7B5JAg5aeqWZWoYATAvNVG7e0gYrw43NADwcyaklWTAa9FC BmNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W88BFAMfIQPlzsE5Ded5mhnnTZPYQAXRUS4xOsxlGF8=; b=ZFC1Oan6UOlFx1tuAvIzqHFK9DKUSifQD9pJgR0QlLpWQNVCafz0gApy6Bzk1i4Jx4 47qtlQsDPGVn76Deo5zmi67kBfEiWjQhBa4tzfsBQQPRZmr1gDjN1v+D9BwbYD3/cb5F eKYKJa0nW+X0Hq1K2iJ2vsu13xodWW6S5E0wo+bS9+qFRmqxqpBX0pMyqZDYlcLL0cbk dOLPGShS2hmr6jfXLcpIUTwUl+xOWqUSfAH3uSs7Ce0YcJzKHiUBJB5WF7i22XQhX6WQ Pi51VFVmcrAWJii+ADyxkPMYbQsZhrtt4c8CdQcSCG4LxsfnHWDIq9Dm8D3pYpwFVnDL 0JvQ== X-Gm-Message-State: AOAM530UFIRsPkJRK4rntB7k7bkrRiiskK9OKMvwQWOMO7tNw/sgOquS RnkSJZCkU3Xr1ozPTFj1OLJt0+C46FvIpw== X-Google-Smtp-Source: ABdhPJwV54ScY8i/ips2wTe5bsNNncZk9pf1ppUMD4kkWEfEnfp74WGt5mf9/Ln+wN4O+APOBBkIXQ== X-Received: by 2002:aca:2112:0:b0:2d4:653d:82b8 with SMTP id 18-20020aca2112000000b002d4653d82b8mr8838442oiz.126.1646388641364; Fri, 04 Mar 2022 02:10:41 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id m26-20020a05680806da00b002d797266870sm2358769oih.9.2022.03.04.02.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:10:40 -0800 (PST) From: Atish Patra To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Atish Patra , Paolo Bonzini , Atish Patra , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH kvmtool 1/3] riscv: Update the uapi header as per Linux kernel Date: Fri, 4 Mar 2022 02:10:21 -0800 Message-Id: <20220304101023.764631-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304101023.764631-1-atishp@rivosinc.com> References: <20220304101023.764631-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The one reg interface is extended for multi-letter ISA extensions in KVM. Update the uapi header file as per that. Signed-off-by: Atish Patra --- riscv/include/asm/kvm.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h index f808ad1ce500..e01678aa2a55 100644 --- a/riscv/include/asm/kvm.h +++ b/riscv/include/asm/kvm.h @@ -47,6 +47,7 @@ struct kvm_sregs { /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_config { + /* This is a bitmap of all the single letter base ISA extensions */ unsigned long isa; }; @@ -82,6 +83,23 @@ struct kvm_riscv_timer { __u64 state; }; +/** + * ISA extension IDs specific to KVM. This is not the same as the host ISA + * extension IDs as that is internal to the host and should not be exposed + * to the guest. This should always be contiguous to keep the mapping simple + * in KVM implementation. + */ +enum KVM_RISCV_ISA_EXT_ID { + KVM_RISCV_ISA_EXT_A = 0, + KVM_RISCV_ISA_EXT_C, + KVM_RISCV_ISA_EXT_D, + KVM_RISCV_ISA_EXT_F, + KVM_RISCV_ISA_EXT_H, + KVM_RISCV_ISA_EXT_I, + KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_MAX, +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -123,6 +141,9 @@ struct kvm_riscv_timer { #define KVM_REG_RISCV_FP_D_REG(name) \ (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) +/* ISA Extension registers are mapped as type 7 */ +#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) + #endif #endif /* __LINUX_KVM_RISCV_H */ From patchwork Fri Mar 4 10:10:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12768901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C337C433F5 for ; Fri, 4 Mar 2022 10:10:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239525AbiCDKLc (ORCPT ); Fri, 4 Mar 2022 05:11:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239513AbiCDKLa (ORCPT ); Fri, 4 Mar 2022 05:11:30 -0500 Received: from mail-ot1-x32c.google.com (mail-ot1-x32c.google.com [IPv6:2607:f8b0:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EA021A9077 for ; Fri, 4 Mar 2022 02:10:43 -0800 (PST) Received: by mail-ot1-x32c.google.com with SMTP id j9-20020a9d7d89000000b005ad5525ba09so6993646otn.10 for ; Fri, 04 Mar 2022 02:10:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XojJYJYeQDYoRY8aa2UcwmJ2lrn8MPbZj4By1hOwJJ8=; b=sTvGpjvMN8kEMh5GEbSQjFMeNHe/cAlCgeH1wQgYfDjW3tvaoU+tWM5Ok6tsgANdZU rWJJ8pKMQ0clUqOqoH9VWE9OhzffRkOI6ph+qv23fYZLsOCw1tV/hKWZb5+Qu63vkQg7 R1qea9JmRrEaQkydbhI1SYYpjPPCvTPU6Fa+KWN8MZZcfDqFYFu1nHPHo+iA5K4apL6g wNvvNHKFpR70EgcJxHBCRRimf8kHz1Gcudx4voE5JeZSMXQ9xdA0vBWpMp+31SIJLTk1 HYQU04VTH0psWVeCjvYOaMUoocs6lImwSLXYytSEYMytRSxp5fK9qDr9dsYWMC8e56fU pJkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XojJYJYeQDYoRY8aa2UcwmJ2lrn8MPbZj4By1hOwJJ8=; b=IQUDH049n/a7DTDBVsYylJchJFeMoPPdhb7hu9hp5JcG+ls9UroO+JpZDwf5IcrGB6 JfstlA8GzXCLucwMenafwPI1XdzJZk6pmte0d8lzJaJy6R+/hUnNjGepaWmQXx45bHsP kIdGF3D5PobDk7Mf2W6Tbg9c3tChOxjxvUBEEI0hVdCb0oL6FRLM/1bnQAazujJ3Z7Rn 2NZQD90pp90uPal6915u5X3mg9kzIzS2l0K3zL4Oe5dAyDQBbvD917tLXDbhMYAmAP1k stgkzttODgB7SOxihpVDXJquw3LAhRocgUAteKpbQqRA4r9UCQIqo4mjSmSH2qXDCZtu wFiA== X-Gm-Message-State: AOAM533BEBRTnEEGSdKiH6qlWQmcAmees4pE2wx50KcbTDMw0mWWXhrd cmlpOifLI2JxZQI6Yt0X0hhwnDu0L3OLEg== X-Google-Smtp-Source: ABdhPJyh30ifafJvsK4GHm0W9wIMw8q/pQ6mJ6vEHJx2t/RYcYce3dcdGa3pxg+Nv2X1rK4b5sLhUw== X-Received: by 2002:a05:6830:1db0:b0:5af:22a6:e97d with SMTP id z16-20020a0568301db000b005af22a6e97dmr22166095oti.288.1646388642760; Fri, 04 Mar 2022 02:10:42 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id m26-20020a05680806da00b002d797266870sm2358769oih.9.2022.03.04.02.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:10:42 -0800 (PST) From: Atish Patra To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Atish Patra , Paolo Bonzini , Atish Patra , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH kvmtool 2/3] riscv: Append ISA extensions to the device tree Date: Fri, 4 Mar 2022 02:10:22 -0800 Message-Id: <20220304101023.764631-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304101023.764631-1-atishp@rivosinc.com> References: <20220304101023.764631-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The riscv,isa DT property only contains single letter base extensions until now. However, there are also multi-letter extensions which were ratified recently. Add a mechanism to append those extension details to the device tree so that guest can leverage those. Signed-off-by: Atish Patra --- riscv/fdt.c | 31 +++++++++++++++++++++++++++++++ riscv/include/kvm/kvm-cpu-arch.h | 5 +++++ riscv/kvm-cpu.c | 5 ----- 3 files changed, 36 insertions(+), 5 deletions(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index de15bfe37b58..2e69bd219fe5 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -9,6 +9,17 @@ #include #include +#define RISCV_ISA_EXT_REG(id) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ + id, \ + KVM_REG_SIZE_U64) +struct isa_ext_info { + const char *name; + unsigned long ext_id; +}; + +struct isa_ext_info isa_info_arr[] = { +}; + static void dump_fdt(const char *dtb_file, void *fdt) { int count, fd; @@ -31,6 +42,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) { int cpu, pos, i, index, valid_isa_len; const char *valid_isa_order = "IEMAFDQCLBJTPVNSUHKORWXYZG"; + int arr_sz = ARRAY_SIZE(isa_info_arr); _FDT(fdt_begin_node(fdt, "cpus")); _FDT(fdt_property_cell(fdt, "#address-cells", 0x1)); @@ -42,6 +54,8 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) char cpu_name[CPU_NAME_MAX_LEN]; char cpu_isa[CPU_ISA_MAX_LEN]; struct kvm_cpu *vcpu = kvm->cpus[cpu]; + struct kvm_one_reg reg; + unsigned long isa_ext_out = 0; snprintf(cpu_name, CPU_NAME_MAX_LEN, "cpu@%x", cpu); @@ -53,6 +67,23 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) if (vcpu->riscv_isa & (1 << (index))) cpu_isa[pos++] = 'a' + index; } + + for (i = 0; i < arr_sz; i++) { + reg.id = RISCV_ISA_EXT_REG(isa_info_arr[i].ext_id); + reg.addr = (unsigned long)&isa_ext_out; + if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) + die("KVM_GET_ONE_REG failed (isa_ext)"); + if (!isa_ext_out) + /* This extension is not available in hardware */ + continue; + + if ((strlen(isa_info_arr[i].name) + pos + 1) >= CPU_ISA_MAX_LEN) { + pr_warning("Insufficient space to append ISA exension\n"); + break; + } + pos += snprintf(cpu_isa + pos, CPU_ISA_MAX_LEN, "_%s", + isa_info_arr[i].name); + } cpu_isa[pos] = '\0'; _FDT(fdt_begin_node(fdt, cpu_name)); diff --git a/riscv/include/kvm/kvm-cpu-arch.h b/riscv/include/kvm/kvm-cpu-arch.h index 78fcd018c737..416fd05e9943 100644 --- a/riscv/include/kvm/kvm-cpu-arch.h +++ b/riscv/include/kvm/kvm-cpu-arch.h @@ -7,6 +7,11 @@ #include "kvm/kvm.h" +static inline __u64 __kvm_reg_id(__u64 type, __u64 idx, __u64 size) +{ + return KVM_REG_RISCV | type | idx | size; +} + struct kvm_cpu { pthread_t thread; diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c index df90c7b9f21a..7a26fd17cf5b 100644 --- a/riscv/kvm-cpu.c +++ b/riscv/kvm-cpu.c @@ -18,11 +18,6 @@ int kvm_cpu__get_debug_fd(void) return debug_fd; } -static __u64 __kvm_reg_id(__u64 type, __u64 idx, __u64 size) -{ - return KVM_REG_RISCV | type | idx | size; -} - #if __riscv_xlen == 64 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64 #else From patchwork Fri Mar 4 10:10:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12768902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F732C433FE for ; Fri, 4 Mar 2022 10:10:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239531AbiCDKLc (ORCPT ); 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(adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id m26-20020a05680806da00b002d797266870sm2358769oih.9.2022.03.04.02.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 02:10:43 -0800 (PST) From: Atish Patra To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Atish Patra , Paolo Bonzini , Atish Patra , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH kvmtool 3/3] riscv: Add Sstc extension support Date: Fri, 4 Mar 2022 02:10:23 -0800 Message-Id: <20220304101023.764631-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304101023.764631-1-atishp@rivosinc.com> References: <20220304101023.764631-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Sstc extension allows the guest OS to program the timer directly without relying on the SBI call. The kernel detects the presence of Sstc extnesion from the riscv,isa DT property. Add the Sstc extension to the device tree if it is supported by the host. Signed-off-by: Atish Patra --- riscv/fdt.c | 1 + riscv/include/asm/kvm.h | 1 + 2 files changed, 2 insertions(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index 2e69bd219fe5..a2bea5e17749 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -18,6 +18,7 @@ struct isa_ext_info { }; struct isa_ext_info isa_info_arr[] = { + {"sstc", KVM_RISCV_ISA_EXT_SSTC}, }; static void dump_fdt(const char *dtb_file, void *fdt) diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h index e01678aa2a55..c7c313272c0b 100644 --- a/riscv/include/asm/kvm.h +++ b/riscv/include/asm/kvm.h @@ -97,6 +97,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_H, KVM_RISCV_ISA_EXT_I, KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_SSTC, KVM_RISCV_ISA_EXT_MAX, };