From patchwork Fri Mar 4 20:10:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12769985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E5C5C433F5 for ; Fri, 4 Mar 2022 20:11:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ROWQIQGJ0NvV9zBvRk8CuGv9eyS1Nb/bcGxK6RuekaE=; b=T5IeHgO746tk+c 2Z0FIlhkMg6FrDHax5C+XUYgXLb0ldaf6faqPekG8p241bKUg+TqtYu38IepONmwK+NGUTkb5JfiE 0EDCEOGF8Ec0vJxiIJFndnRUdHlztXI1E+aZFxK1RIOO5puTMVKV2/5z26MhC5TQtVp8WLiLVbO8p Tm0BmrZHZkAkVknn70CrpnHFifwGybH0ExPNvXJNwXEMfLoa/sWj8yOMRczPoIWXOOGa1KgvpyAzk Rx21Hiomi/R9wxStfuGKA6Nes5jvFMoyDWJLnL8HlZtJTM2/RoqvWWDc/00IG7Nad6O7/x9oteaFM +s59tuZoYlHvqpBuy4lQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGE-00BtAs-6k; Fri, 04 Mar 2022 20:10:46 +0000 Received: from mail-qt1-x832.google.com ([2607:f8b0:4864:20::832]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGA-00Bt7N-PV for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 20:10:44 +0000 Received: by mail-qt1-x832.google.com with SMTP id t28so8362992qtc.7 for ; Fri, 04 Mar 2022 12:10:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c6aEUd2HwY01Z/Ayysg23IOPYksH4V6g17VAVrgQgx8=; b=OTNsK7j5dme3IWmBvygn+JNkeA/iSLbLNVG7NPSIxtQxVzkFwdmDsLe6Ps4Z0d+Asn /h6LTCk3MYXpN2rkmpaDUl53wNaFt6bkBi++QQ9H+m4XbD7iw3Gaql8PTvhIMS7po78I 9d/4qbHopPz7zYIvgS7kBzJkL2CyzM3p9URRe1XuSK4c7xxVol1G30HmKW0/FtkrQ9An fSPM38RBjJbm9z0yB5oVYrbY5sRppU7/e0h+Pm/zXNlwEnEJWSV5QJjjH4tKXxdFi3S4 xIOm7briW1DQJusAwcbL6NGDugS/efnIAfYxN4j73g5zZGVS5M0z2tRHOklbQDyFykPN vqIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c6aEUd2HwY01Z/Ayysg23IOPYksH4V6g17VAVrgQgx8=; b=w8oHqkxvPEg8lctaqcO11QPTxC4H29sx8Mw/LKbYynMj4SAbZ3U0EKgUS5pOjzx2zY SzXiT5J43IjEgomxq53hAuwZOqvWJ52SKBGJ/J9ZyhmWWyMMLBzQRpw6JG3Gv1fJS20+ vsoy1ELh1X3KYN9VRFWCOKwf/KrT8PX1p1QB1juJQXkTPVZ+S6fkK7SAM0iFcKUA0x7X DzPF3L9KGkVaBJ37cMadSBusTXrNME1EU1CeN94M4kM2xUFXDr9qv7bZcVULHMXvIDQQ QmCoknokye8nXyA+5cziSs9R6jqaBRUFm1n2ySBsGitJBZUbQAL52EcCgkNO/Poh4ViH 6frA== X-Gm-Message-State: AOAM533kiQQzsq/8BYQrf9gOsLMusV7mGwsWn9Kku3Ee2djmavW5GGfj tHK/oqwgFJ5X7psxXuFTXro2kLcN7GLH4g== X-Google-Smtp-Source: ABdhPJwc8lEqPa56iPaIxhTGB31XNo6PyIYeb5DupNo7mYfqTQjOKAVOAv57R7W4kjXKcWpmxkcP3A== X-Received: by 2002:ac8:5fd3:0:b0:2de:9f95:8eae with SMTP id k19-20020ac85fd3000000b002de9f958eaemr370759qta.217.1646424639864; Fri, 04 Mar 2022 12:10:39 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id 20-20020ac84e94000000b002de8f564305sm4605481qtp.1.2022.03.04.12.10.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 12:10:39 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH v2 1/7] RISC-V: Add SSTC extension CSR details Date: Fri, 4 Mar 2022 12:10:14 -0800 Message-Id: <20220304201020.810380-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com> References: <20220304201020.810380-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_121042_848507_12593CD9 X-CRM114-Status: UNSURE ( 8.04 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch just introduces the required CSR fields related to the SSTC extension. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index ae711692eec9..8f37c063a205 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -165,6 +165,9 @@ #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 #define CSR_VSTVEC 0x205 @@ -174,6 +177,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24D +#define CSR_VSTIMECMPH 0x25D #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 @@ -189,6 +194,8 @@ #define CSR_HTINST 0x64a #define CSR_HGATP 0x680 #define CSR_HGEIP 0xe12 +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 @@ -247,6 +254,10 @@ #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) +/* ENVCFG related bits */ +#define HENVCFG_STCE 63 +#define HENVCFGH_STCE 31 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ From patchwork Fri Mar 4 20:10:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12769984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38D5AC433FE for ; Fri, 4 Mar 2022 20:10:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vVvYSrR33X/x10IwBqkrFQvyd903TyX7GfvSDP8fjw4=; b=ZSSi2Euy5I9KUO tSMVdGDbYgvAs6amUP9tVz1fSwkqPxLYw75x8yn1tKsrsGb9wD1y2QVseTAd2iyMaBOERi+hHslWd z65lWh3w4y4w9aDnRf15g0njoa0mtyJcMYyRdjm/VfVgzvqgBFdH3Jiin/sIIxEHH3hiIC0DSlnEL Csa4As0DBaUxNnu7QXp8zZkCl1FQYe1K5Wo/Qwr1WMRzNWAOB9mAKEAGaoXxneTaMv4KhxQzohz8R PpWc0LuTRzBzOPkFXROF6ZeK5dPQB6FQg/FvXYCuZxEXRIlVNKCgPMdfAHPzsnXiv7vxDUmhnqz5e ezPy1bie4wxqgIlq9I5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGH-00BtDU-3N; Fri, 04 Mar 2022 20:10:49 +0000 Received: from mail-qk1-x72b.google.com ([2607:f8b0:4864:20::72b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGB-00Bt7w-TB for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 20:10:45 +0000 Received: by mail-qk1-x72b.google.com with SMTP id g24so7346541qkl.3 for ; Fri, 04 Mar 2022 12:10:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZOaq/RArOsIMDEytI6Sz1pnZYzBz3vUl5NUCRG67IW0=; b=qwkfyanXvztQ6XLHz71CS2ApVZCgU95lIC27jZPWXeHR2QT7ofzrhKQjLu8US8da3j +V4zJVXa1833fD7feTy7V19ftKSt58usT4zuDhsZY99fM3u4/VP08oB5BNHmy7mMUmBC Hd5+qCg79rcE+EW8alFQs34f1JBTdkEJhwX/KMoPc70/mwmRao4pvlOfyi9vWBIaga0J dqH7iXWKMJN0CAlQSWv3SEcZOgAGMT3IFmRtBnUsrvzvsDq6CJ+qHjejICE7X/qhd1mG QNyxZ3elzq1UufWglGovzC3hRw4Fbab9k9NwdCY6ZDP+EEK/o7lM7vwVVkxtC+PS1SFc LWog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZOaq/RArOsIMDEytI6Sz1pnZYzBz3vUl5NUCRG67IW0=; b=r0TKg69Abeo8t7aFS1kV7x2QvSuHkgJZVfsEnDuPeClwB70flKAuB024sYW3du0Uqc jmn0Lgn0ur1QSuSwyx0KXRl7UjBcRplnb2LXvyVf37OIIp5gXJaQYuXDN7iy3qD6Faxm CARcILCh3f3I9/TP0gUTlYVdPDuKAX2rnE60JMn3pGvl3l/YQYbD6qtXUvbautOKAZz9 4WymkgqrXUXbs5ADwjtaOgMXYRdTFD5EcigqSMQn82goKYVncwk/9KM2P+3HYTzJx0hE 4Ce+tgX2CclITTpEE1Xm+0iNS5+VcU19SzoObyfPBDzeQPhbjOlfOrE9CyscjBndDViu 7l0A== X-Gm-Message-State: AOAM53034dO+IF92o1EGB3uxC4OP0yE9aruuRYLHudNr6Wr8zXLvpkRp TK32Eak3mVqA5RP97kPHWPbrVg== X-Google-Smtp-Source: ABdhPJyz4bobvXoyET5/f3LrTYV3os+fQ89XumUD4klEmrv0+DoLEKr8Botl+4EiH0M454t8eFvVIw== X-Received: by 2002:ae9:dfc7:0:b0:648:e065:84be with SMTP id t190-20020ae9dfc7000000b00648e06584bemr209067qkf.129.1646424641718; Fri, 04 Mar 2022 12:10:41 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id 20-20020ac84e94000000b002de8f564305sm4605481qtp.1.2022.03.04.12.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 12:10:41 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH v2 2/7] RISC-V: Enable sstc extension parsing from DT Date: Fri, 4 Mar 2022 12:10:15 -0800 Message-Id: <20220304201020.810380-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com> References: <20220304201020.810380-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_121043_981346_D16C2E47 X-CRM114-Status: GOOD ( 11.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The ISA extension framework now allows parsing any multi-letter ISA extension. Enable that for sstc extension. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 691fc9c8099b..7335e9138fb7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -51,6 +51,7 @@ extern unsigned long elf_hwcap; * available logical extension id. */ enum riscv_isa_ext_id { + RISCV_ISA_EXT_SSTC = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 031ad15a059f..7568c7084a52 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -71,6 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node) } static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f3a4b0619aa0..1d8a06575cea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -192,8 +192,10 @@ void __init riscv_fill_hwcap(void) if (!ext_long) { this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); - } + } else { + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); #undef SET_ISA_EXT_MAP + } } /* From patchwork Fri Mar 4 20:10:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12769986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73D53C4332F for ; Fri, 4 Mar 2022 20:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vJjds4yxYpquKypc21gQQKS5hIDU50/rA043WkBJbk0=; b=lRhe4kmp8akCi9 6tyytIfFs4YCgk+sh+OxayfZ02asLSM+Dq3Qm2h/sn0nFe3sXSy9KY1c6II2DTpmHXcBCeHgENuB0 i4c19p0+hNlHQowdJaBwT5Mk57BtV8/z+RcQWrWWqj2LinEurxc+zgT+OS6ZdMRzYHYGqMq0brzTi bUtcNIiZRYJJD6J5VQ7ZZnD7t4tzEkWws4JNd+x9NSinKcReC5FJU7MgheEPtAA2PqomQmbHqETq7 Y5+I6wD/yme3T36cj9Xn9xwthyP0FAacDXGSDKBdCAEiQ49FcN35pqQjGTuPQwIPhbJ7zyaKL6ZY2 BMex3hwlp+gxM+lUkXoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGL-00BtGK-40; Fri, 04 Mar 2022 20:10:53 +0000 Received: from mail-qt1-x82b.google.com ([2607:f8b0:4864:20::82b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGD-00Bt94-1m for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 20:10:46 +0000 Received: by mail-qt1-x82b.google.com with SMTP id e2so8346171qte.12 for ; Fri, 04 Mar 2022 12:10:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=La2sWt3lJ51N8aiXaLxTZ81rzxffeRmbKmdg2xjj9EM=; b=llfQGxUrGrIoejHojVcb0Y3KUScFEeqhQN64bg0W4G16w2e2xy20xTh4VNEgip99So 7EIAnl+l6HMTK+Y1H2tYXX0B0OANzxweW3TS6UmqFdhSes5f/e8/muPvXtpilTy1Rl/Q MCtur+l2VFqXJM3gqXE0SmrsJqMVydFtm0mH8+Fqn4YEFDSSuwa3n5LubdlQRqcop1X7 tLDTiG7PokjlHkftXZrmY/k420PmVZKPhGp32eo3k4QrC/G3XmzH3l6HB2PMpG+2WFQL JZIwTm9my8jlHWQiiVx4InmFOJMfvlxtaRbhDWCMF7nO2chX8XlnOlmlEf5nQOaQXQfS 7HPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=La2sWt3lJ51N8aiXaLxTZ81rzxffeRmbKmdg2xjj9EM=; b=pnMVDPBE0FhXlhqpStVjysgynQikaEa+YN1jfhdFtt4M6vJj4ArTsHoLAb2WRvpc3c Jef23Uox6VTXv5wp04y/g5SExPuTm2sREQwaZtAihdi6oOIYjMWVEFdYuvJOoH7hzQA8 VQpBGCPAEIJNcCRNEewXtOMkq+BJi3IK/oS1hce8eClXwmL0tHQxSkVpdHPVkbdGffqH 6diJgzKjQsqYSrrESrbENqlAeeagfzKKJsT36/kI62VPJfJilgWZ5IBUz4wZiQIKSyDt /L83JpoWTH4O42GYNDvRx6UYDtKjcU2JuN/CQBa891EUiTHR9ryneb/nvX/kePK8ZCmH bg2g== X-Gm-Message-State: AOAM532bfZMjH+luj9nQrFgBigo5VO/x+Fll2lfkatTz/QsBwmaeKuUo Hh5nR6O+Wxt30zNAeXigAZqj5A== X-Google-Smtp-Source: ABdhPJySb8vTeaMNOaVqmNeyuKGat3EV0t1E2R+ui2Q6dQN1/Nz3MPMm95v3MmBjR1PmrcRFvR5rTA== X-Received: by 2002:ac8:7ed2:0:b0:2de:6f9b:5c3a with SMTP id x18-20020ac87ed2000000b002de6f9b5c3amr388493qtj.203.1646424643609; Fri, 04 Mar 2022 12:10:43 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id 20-20020ac84e94000000b002de8f564305sm4605481qtp.1.2022.03.04.12.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 12:10:43 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH v2 3/7] RISC-V: Prefer sstc extension if available Date: Fri, 4 Mar 2022 12:10:16 -0800 Message-Id: <20220304201020.810380-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com> References: <20220304201020.810380-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_121045_123434_58CA9DF6 X-CRM114-Status: GOOD ( 12.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V ISA has sstc extension which allows updating the next clock event via a CSR (stimecmp) instead of an SBI call. This should happen dynamically if sstc extension is available. Otherwise, it will fallback to SBI call to maintain backward compatibility. Signed-off-by: Atish Patra --- drivers/clocksource/timer-riscv.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 1767f8bf2013..d9398ae84a20 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -23,11 +23,24 @@ #include #include +static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); + static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { + uint64_t next_tval = get_cycles64() + delta; + csr_set(CSR_IE, IE_TIE); - sbi_set_timer(get_cycles64() + delta); + if (static_branch_likely(&riscv_sstc_available)) { +#if __riscv_xlen == 32 + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); + csr_write(CSR_STIMECMPH, next_tval >> 32); +#else + csr_write(CSR_STIMECMP, next_tval); +#endif + } else + sbi_set_timer(next_tval); + return 0; } @@ -165,6 +178,12 @@ static int __init riscv_timer_init_dt(struct device_node *n) if (error) pr_err("cpu hp setup state failed for RISCV timer [%d]\n", error); + + if (riscv_isa_extension_available(NULL, SSTC)) { + pr_info("Timer interrupt in S-mode is available via sstc extension\n"); + static_branch_enable(&riscv_sstc_available); + } + return error; } From patchwork Fri Mar 4 20:10:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12769987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4E0BC433FE for ; Fri, 4 Mar 2022 20:11:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YuHjY00jIK+4JeVNl7KTJJn5umMqUaJ6EcUws19rtf0=; b=BWGuPKAt5Kex7C 5ero+GhUarrLacCgLYAkXHDq2mcu9H4WYCWYnlnVpwMg8hydFbglDkZruj5X8OD2Yz6nwq9TTPqHF zbju3AmwiyMhj8/Z+uMZ++i4ExJ4dOOAh2fM78VFDzWHLZhXn9Cidif8DCMSWj6iKg0dGnNly7q+V sf5Uu26Pg9qET1c8QODhySPBDAPdF3LjstXvjgwBrju9JUQ9oWbmrD57YzniBhe7VqkVW2y/cjE/S A84YG/b1No1difOC4aFygMVQFZS48v8JYsdCX8h7FT9RXjGICd7nQAs23V/mmBkUPlBQqV3a6fUwA zO5jSvFkQ/u879Jj4KWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGP-00BtIv-4x; Fri, 04 Mar 2022 20:10:57 +0000 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGE-00BtAl-Tc for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 20:10:48 +0000 Received: by mail-qt1-x82c.google.com with SMTP id v3so8332182qta.11 for ; Fri, 04 Mar 2022 12:10:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qsIO2ya+cektsJMcKlRJepNqbeDF38Da8NmtSJ8s3gU=; b=N8FaQlw5OIEM3nPnrnG5ZP2TJJy/b2ccHKMgsAFTjSQD2qsuFgofIv2+b3o9BK1ZpN //j8EXvZd85ZIPGjHfXBgbqKRWSWnxfdpuL+fQK0aZMczrozI6OmH95uiuITNr3tToBt yo+IBGiuJ9MYEMUby4Y+iz940dgwRcjRcLlEM7LTUPJ0t2jcHcO6JqIo+/zKqJ0GRl60 kROrc93K3cYxxoudnV2HZfdlRMDAkvxBsaT0Z5V1O3vN9b05UwxF9kyv7DdQRgFoCRC6 YDEKxgc2mwGeYdA9wU3GErE1QEoOLqHp0DXpEukTcS8Ks0s/Bm36xscy4D8XcNBCJLSL 7Lpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qsIO2ya+cektsJMcKlRJepNqbeDF38Da8NmtSJ8s3gU=; b=Veco32pEI3XQGT6EB8GF1XOtl+JHi94AldJVplfDcKub8sN4W4JUe9Uecu/pjVnuIp HWd9ox+RmbfLxc03UUKsohRVGWUsStukIe19neQz4v4hykskGLICtHXIaTh5vCUmvt8c At6HkUbAiPKGn0o/WdvaDaksKMvLveKFD3Zzt0X0QVmlyjniB7fHJ7nwwYqZDeuD2a/9 XbbbA8OVakLCwVnhIQecp+4Txph+uyTWdqGS9ceCzULWxz36hcNskYLrfkZqwIdwXtBr Q6GTa97qPQ2F+JAd6MfOfYtKavFkPHyFlCrMkejOI4nHhFIbGOENcP9Wyqa5O6mTjxNo nICg== X-Gm-Message-State: AOAM531PClhSe5nCHCZRMk1ey5qx7kksIabodCAN2eKrXg1fn9hUZX39 V3JbSW0B2AYwJ5tukz1FcMBqsQ== X-Google-Smtp-Source: ABdhPJyBu28CBsOFIzyM9DOgbXjnNnxtobqGHxzYB0P4cAzhg/+V3vQ13sjTBnimNgfPW2IUppEExQ== X-Received: by 2002:a05:622a:1b8d:b0:2d1:38ca:6b1 with SMTP id bp13-20020a05622a1b8d00b002d138ca06b1mr396609qtb.688.1646424645574; Fri, 04 Mar 2022 12:10:45 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id 20-20020ac84e94000000b002de8f564305sm4605481qtp.1.2022.03.04.12.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 12:10:45 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH v2 4/7] RISC-V: KVM: Remove 's' & 'u' as valid ISA extension Date: Fri, 4 Mar 2022 12:10:17 -0800 Message-Id: <20220304201020.810380-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com> References: <20220304201020.810380-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_121046_983486_AEC73D3F X-CRM114-Status: GOOD ( 10.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org There are no ISA extension defined as 's' & 'u' in RISC-V specifications. The misa register defines 's' & 'u' bit as Supervisor/User privilege mode enabled. But it should not appear in the ISA extension in the device tree. Remove those from the allowed ISA extension for kvm. Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 624166004e36..3ae545e7b398 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -43,9 +43,7 @@ const struct kvm_stats_header kvm_vcpu_stats_header = { riscv_isa_extension_mask(d) | \ riscv_isa_extension_mask(f) | \ riscv_isa_extension_mask(i) | \ - riscv_isa_extension_mask(m) | \ - riscv_isa_extension_mask(s) | \ - riscv_isa_extension_mask(u)) + riscv_isa_extension_mask(m)) static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) { From patchwork Fri Mar 4 20:10:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12769988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2450C433F5 for ; Fri, 4 Mar 2022 20:11:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ze3Gf2PbALfA6HGsyRQyIjxpUAYQrmzMV36jllx+n44=; b=mRBSDRqB/ywjjG 0Y17sCCllkKQ3m6CVoBcri8Gax22vhofX5iOzvmzMf1T9wSaU2LSNSFpC0MiDwn7zG9quxgcx9jwC RgAOw7PESxasWcwwUnWSsK7C8iJUUzYzKw4aDhTOJhHivHEmwOkDLANQesGYUzBwABQMg0WQIa2Lm xqUbimtk3nofbyNOdj8baRTRL2JGFCphAyblw7KE+bNuCBwjaRZWlx8QlKIwyaCYR/Wn/fuZhrOGb 7/wEZ+ThVdoaql2VjaoA05g7EjEwqkHkD/yhNy952p9cmyUFd2IsvUQ4c1OmYSek7ridhqB8FehF1 qi1uP36KUTIGLlQ4I8YA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGT-00BtNk-Iv; Fri, 04 Mar 2022 20:11:01 +0000 Received: from mail-qk1-x72d.google.com ([2607:f8b0:4864:20::72d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGG-00BtBw-NG for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 20:10:51 +0000 Received: by mail-qk1-x72d.google.com with SMTP id j78so7349263qke.2 for ; Fri, 04 Mar 2022 12:10:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VGU3lDVBq59QqjYsyRxQH4/VHY2UtoMa8BpyGMZ/FLo=; b=ogou+8r1Nf1Cv1Sqo2avgI+ufHZcUQqdvKyABGfz/Jgc+M/SCWUFQ0E9dIfKtMXMSR 2NCi9Iv5Kpn5fzA3h8CIk/bNHWE8Pd3sJFOVKnlj7MJz78TxbTRnE5g4Mcc+97U5oUKg YsSPgos3H5hG5PVLOeekfix7+oR8CaU/8TXW+4p6m9nrW0hwiLMccODAxdIO5ktxqlRZ bq+2ViShK8qFFgqxSRwbWKq9b342rrny35pRQuSHIYK6CthnEhj/yd246vKtmYptSbkn jGrrst+bhQetTjyhauFJIwklZA6Do1cl2pH1QzrR0SQexPffkJrEqVl0xMQN+lqPhZUb C3rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VGU3lDVBq59QqjYsyRxQH4/VHY2UtoMa8BpyGMZ/FLo=; b=I7RZS5ePq4O4vlWXE2ssQ+v72MOlbUhSxjtcnCrB2cDDu9GZ9CnQ6HxUNsf/VqAoW7 Z3HytUEV8PvBrfGwmKPrEkV8QkQ9OjuH3xuDHsnWuKiK4p0I4OinVX5k3frI13KDxztG DgdhuXMMhXP63RUWDKQO4+F6HJGfzmmhTtKYGY7Z7XZxFiKDbm86Z+4yD2pDUMtP/hMo E5KWW1UIgp76wHcVlCrRZa5nNLmobUQM5NxUoFSG0idKY4bsmoZGhT2QMEtZ1ApQS43S FuAjSk7kVvnrG3eW/vuHtXfu7yvB3XeplkcX3aNhg4Dq2NySG9DiVeUKbrXa/zzRP726 MMxA== X-Gm-Message-State: AOAM533U7vzHoeNJETKS+l/d86AaTOlcKwCum4qe5aS9BRWj/0YtLHnY VP554Yw5rjjCjJYtiyTmkE/TxA== X-Google-Smtp-Source: ABdhPJziAT+GkcoKPwD8VK1mQG+Q81feZ7J2fFcV4cs55xPUicqo70tLtaLMRp0qMRbF9AiUkgGugw== X-Received: by 2002:a37:c06:0:b0:49b:7a31:cd54 with SMTP id 6-20020a370c06000000b0049b7a31cd54mr230310qkm.358.1646424647390; Fri, 04 Mar 2022 12:10:47 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id 20-20020ac84e94000000b002de8f564305sm4605481qtp.1.2022.03.04.12.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 12:10:46 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH v2 5/7] RISC-V: KVM: Restrict the extensions that can be disabled Date: Fri, 4 Mar 2022 12:10:18 -0800 Message-Id: <20220304201020.810380-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com> References: <20220304201020.810380-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_121048_832524_12155A2B X-CRM114-Status: GOOD ( 12.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, the config reg register allows to disable all allowed single letter ISA extensions. It shouldn't be the case as vmm shouldn't be able disable base extensions (imac). These extensions should always be enabled as long as they are enabled in the host ISA. Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 3ae545e7b398..388e83857ced 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -38,12 +38,16 @@ const struct kvm_stats_header kvm_vcpu_stats_header = { sizeof(kvm_vcpu_stats_desc), }; -#define KVM_RISCV_ISA_ALLOWED (riscv_isa_extension_mask(a) | \ - riscv_isa_extension_mask(c) | \ - riscv_isa_extension_mask(d) | \ - riscv_isa_extension_mask(f) | \ - riscv_isa_extension_mask(i) | \ - riscv_isa_extension_mask(m)) +#define KVM_RISCV_ISA_DISABLE_ALLOWED (riscv_isa_extension_mask(d) | \ + riscv_isa_extension_mask(f)) + +#define KVM_RISCV_ISA_DISABLE_NOT_ALLOWED (riscv_isa_extension_mask(a) | \ + riscv_isa_extension_mask(c) | \ + riscv_isa_extension_mask(i) | \ + riscv_isa_extension_mask(m)) + +#define KVM_RISCV_ISA_ALLOWED (KVM_RISCV_ISA_DISABLE_ALLOWED | \ + KVM_RISCV_ISA_DISABLE_NOT_ALLOWED) static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) { @@ -217,9 +221,10 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, switch (reg_num) { case KVM_REG_RISCV_CONFIG_REG(isa): if (!vcpu->arch.ran_atleast_once) { - vcpu->arch.isa = reg_val; + /* Ignore the disable request for these extensions */ + vcpu->arch.isa = reg_val | KVM_RISCV_ISA_DISABLE_NOT_ALLOWED; vcpu->arch.isa &= riscv_isa_extension_base(NULL); - vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED; + vcpu->arch.isa &= KVM_RISCV_ISA_DISABLE_ALLOWED; kvm_riscv_vcpu_fp_reset(vcpu); } else { return -EOPNOTSUPP; From patchwork Fri Mar 4 20:10:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12769989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22330C433EF for ; Fri, 4 Mar 2022 20:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MovOKnYOheE1yZUI5HOvdTDg4Qo7wO9+aNYmldNw9OE=; b=NgeZ0BFOF/xkvj a5wW9qyg7qUXECnfIyjSyg5YbzKA6oBSpYuSHpRNsUw2mDBkgv1MxgbxFqy14pZn7wGStexG9i7wg pObTKgcBSp1YEbwehAqE9Q7YZcnNijJD7jgsOvmfxTiEWE07R6JECkGRU7MEr6D1bkAfCxflA/kDD CYmpb5uCIlu+oysl8tP7UOF/EV207u3NSNFdcnOVVA0BPb3xUdbpC4ycvu7O9djVRxKHCx0N/Nvj1 PoVKIViW7uJGYQelHVqbo6Q3scXEUfq1cnwXXma40URY/3jB5NyPKM+msK9j7+9W59NNe52D/0RkM EEBLuJ1paB1VGIenYvLg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGY-00BtSj-JK; Fri, 04 Mar 2022 20:11:06 +0000 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGI-00BtDo-KG for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 20:10:52 +0000 Received: by mail-qv1-xf2c.google.com with SMTP id p8so4480138qvg.12 for ; Fri, 04 Mar 2022 12:10:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2wru3M1yMPyEFqwSTOW5mW4tskJC8ZDyyBoca3oJyRA=; b=G/n2GmKp91RxjtIcKoNLY3aPhTFHRvaWNSNT7e+Poso3oCfU9EFH09jY3oilnkw8g5 IR98aMxBJmioNNveW4kY5u+tBXMIuNob15L+GTIDhOcwcTMsqaDK+ba/Ta/9EF8cnUxR IJs7MHMrlNMJLjBv/JYaupxcYL5KWOw/ps/jjsPN5IExdCksxTIcUzr8AtoyhEXDdgOS Iv5xSBvJLu+dQdg6YwgiA8cDcevodKMMDW+0VcQSM1h6k5JSoQVBBrkmRGzq8ax7Royo IbZ6BWtkqOcv4ebACg12b9tJSAduqWWbn8DJolDpaxw/Yyd7WqZn6rb2tQ/I+7ojiPAH +/fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2wru3M1yMPyEFqwSTOW5mW4tskJC8ZDyyBoca3oJyRA=; b=nHIEplMDhY7WD6dDF5y9UiOEfLNzRmTokGtDhgs8c8VTnFcCKDVqQ64moIRnpzprRG wVxyQf3qBjFEGKQJt04ddTR4Zriwro/X3VIllW39P0M2/iO5vb5hsZJMG9uij1Npj1UY YCXgXzZ3/kB3m3LIc/KXS2Rzg0ubz4XvTnhMIDQVaQfI9gBV4Cg/nDEXDesbZDqzWAuW BZ+4btvzFV015PvQ1//mp1809jE7XQoyn4vuDbYIEVEm9f2pdcRv4lOwO/wBhPU/av7M kJ4yR8EMdX166Pf5xt+ZgndxVfGno5TD5OsVoA7i31rOlfvmbAZyqcaTvCitCin91LJT ooTw== X-Gm-Message-State: AOAM533c3cOtQwPPeBVVqaAnSPML6p/BJMf65OnPnxoIMWowYMG6Qbus SQ/mrAaiV58cx5G3wAN3yUN4QA== X-Google-Smtp-Source: ABdhPJwZyBYqJUXAuZTvlZXfoYOfmgkICsgs3Sp5Nz6XMt3sMwLXKzPOsJ8HcqSp+EhZ40MSNHpD4g== X-Received: by 2002:ad4:44a8:0:b0:435:16c8:76bb with SMTP id n8-20020ad444a8000000b0043516c876bbmr46624qvt.117.1646424649236; Fri, 04 Mar 2022 12:10:49 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id 20-20020ac84e94000000b002de8f564305sm4605481qtp.1.2022.03.04.12.10.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 12:10:48 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH v2 6/7] RISC-V: KVM: Introduce ISA extension register Date: Fri, 4 Mar 2022 12:10:19 -0800 Message-Id: <20220304201020.810380-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com> References: <20220304201020.810380-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_121050_744673_8D432D73 X-CRM114-Status: GOOD ( 22.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, there is no provision for vmm (qemu-kvm or kvmtool) to query about multiple-letter ISA extensions. The config register is only used for base single letter ISA extensions. A new ISA extension register is added that will allow the vmm to query about any ISA extension one at a time. It is enabled for both single letter or multi-letter ISA extensions. The ISA extension register is useful to if the vmm requires to retrieve/set single extension while the config register should be used if all the base ISA extension required to retrieve or set. For any multi-letter ISA extensions, the new register interface must be used. Signed-off-by: Atish Patra --- arch/riscv/include/uapi/asm/kvm.h | 20 ++++++ arch/riscv/kvm/vcpu.c | 101 ++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index f808ad1ce500..92bd469e2ba6 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -82,6 +82,23 @@ struct kvm_riscv_timer { __u64 state; }; +/** + * ISA extension IDs specific to KVM. This is not the same as the host ISA + * extension IDs as that is internal to the host and should not be exposed + * to the guest. This should always be contiguous to keep the mapping simple + * in KVM implementation. + */ +enum KVM_RISCV_ISA_EXT_ID { + KVM_RISCV_ISA_EXT_A = 0, + KVM_RISCV_ISA_EXT_C, + KVM_RISCV_ISA_EXT_D, + KVM_RISCV_ISA_EXT_F, + KVM_RISCV_ISA_EXT_H, + KVM_RISCV_ISA_EXT_I, + KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_MAX, +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -123,6 +140,9 @@ struct kvm_riscv_timer { #define KVM_REG_RISCV_FP_D_REG(name) \ (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) +/* ISA Extension registers are mapped as type 7 */ +#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 388e83857ced..a3ae7042c696 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -365,6 +365,103 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, return 0; } +/* Mapping between KVM ISA Extension ID & Host ISA extension ID */ +static unsigned long kvm_isa_ext_arr[] = { + RISCV_ISA_EXT_a, + RISCV_ISA_EXT_c, + RISCV_ISA_EXT_d, + RISCV_ISA_EXT_f, + RISCV_ISA_EXT_h, + RISCV_ISA_EXT_i, + RISCV_ISA_EXT_m, +}; + +static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_ISA_EXT); + unsigned long reg_val = 0; + unsigned long host_isa_ext; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + + if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) + return -EINVAL; + + host_isa_ext = kvm_isa_ext_arr[reg_num]; + if (__riscv_isa_extension_available(NULL, host_isa_ext)) + reg_val = 1; /* Mark the given extension as available */ + + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_ISA_EXT); + unsigned long reg_val; + unsigned long host_isa_ext; + unsigned long host_isa_ext_mask; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + + if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) + return -EINVAL; + + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + host_isa_ext = kvm_isa_ext_arr[reg_num]; + if (!__riscv_isa_extension_available(NULL, host_isa_ext)) + return -EOPNOTSUPP; + + if (host_isa_ext >= RISCV_ISA_EXT_BASE && + host_isa_ext < RISCV_ISA_EXT_MAX) { + /** Multi-letter ISA extension. Currently there is no provision + * to enable/disable the multi-letter ISA extensions for guests. + * Return success if the request is to enable any ISA extension + * that is available in the hardware. + * Return -EOPNOTSUPP otherwise. + */ + if (!reg_val) + return -EOPNOTSUPP; + else + return 0; + } + + /* Single letter base ISA extension */ + if (!vcpu->arch.ran_atleast_once) { + host_isa_ext_mask = BIT_MASK(host_isa_ext); + if (!reg_val && (host_isa_ext_mask & KVM_RISCV_ISA_DISABLE_ALLOWED)) + vcpu->arch.isa &= ~host_isa_ext_mask; + else + vcpu->arch.isa |= host_isa_ext_mask; + vcpu->arch.isa &= riscv_isa_extension_base(NULL); + vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED; + kvm_riscv_vcpu_fp_reset(vcpu); + } else { + return -EOPNOTSUPP; + } + + return 0; +} + static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -382,6 +479,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT) + return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); return -EINVAL; } @@ -403,6 +502,8 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT) + return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); return -EINVAL; } From patchwork Fri Mar 4 20:10:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12769990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A84D6C433F5 for ; Fri, 4 Mar 2022 20:11:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zOipk+4w3ZqXfwAdFnYAWUU9brlMLHTW+RJzvmdMZRw=; b=YBpMrhx+ZD5eCJ Msk1dcqkDGNF5nU8Yw7gSkbMgppBZAg6FUyM5YtJkccZwoXevKwHgtR3oqELJLnLFJp3tnIe2rr1c JN/kdpafOAprAEdT4qVGezun0jzai9BgzyZdl+O6KXnIV4vGXUcOTDh+jsMZ8Qqdfqr3yupfEiPjM gl9bio5TnNtvzuv2khZM4XZZ+0GhtXpBHRp6rGaizB0Uk7TZHOw3+X3jxSO3uoDVdleyDRcQ9JdMA V7EFOlEDtI214XdV/ErTTDOf7QRQGbrZXW/Vh97r8XbxsqMW/6i793n/F7J7V/cqu3dcL6tQjyP4E SF7FuP/iXPD7wHSFb4Sg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGd-00BtXd-CW; Fri, 04 Mar 2022 20:11:11 +0000 Received: from mail-qt1-x836.google.com ([2607:f8b0:4864:20::836]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQEGJ-00BtF2-T3 for linux-riscv@lists.infradead.org; Fri, 04 Mar 2022 20:10:55 +0000 Received: by mail-qt1-x836.google.com with SMTP id s15so8367474qtk.10 for ; Fri, 04 Mar 2022 12:10:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L51YRqAFrRt3gsxpEsaQpEo6O6Me/Tnsaqxdxx3Jl7c=; b=4eof9vIa/d6JqWuLNTaKiN/PrUkL783d6CCn3/pUhV6FSDGx+QxWSw3F4SYWH7epnf rS3GyBOOUn3lFUemonsCilsMAuQzJbtwoNJhKGa4+3y57/ngZki6wA/ol8RmnooOpux/ WsLCpIX68ygFaRFvyG5fGa/H2z42Lmb2lyM9YDr+hBonFY0CzxpN1BZbJ//3tyVtShCL EJgOk8B2nKhB1QN2GNY1Jnxhapgm372lCximzTAw2BLYxV+J/Svzx3ooMy8zmdMyzxQ9 eLl0zB5ctgkLdzSyUIy1Jy53gs0xn2MRygQauroS1JODqa96yG+G3tcQqXHiRBaU/pK7 fBXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L51YRqAFrRt3gsxpEsaQpEo6O6Me/Tnsaqxdxx3Jl7c=; b=qT4llq8uA+XQjRD0cF9Q3rroVHtcCeT4spCMj3glSIhTfC4msfMXY+asWVv7DqnEz7 VLjhS6r8OA/W6Mia2v/H7H8ecsqgOo3a7mWYJnmPeH+v965+m9X2XBsn5B9ArHXN8AaJ 5N/OIGHcUeeO9xkfC8Q2+/08ejdNSyLNHUfrZpNsbvdE3olrL2BoYpSIjf7JrC0ipqGs nM36xt5ej9aAsk3uhOYt9B5ktHN8VMTpLKjKUzgV3CSWa2g7VOi3sfdCFZY78l/+8oKW izGn8ewmgHD5yD/QenksEuR/UydLNL0XBpk6mKdR8MU7TbXgic0MiKdECTq7jzwlY89M C7jA== X-Gm-Message-State: AOAM531hkPHR/c/N0WtCCJVDhMUKX3A4NBTsqz/eTpW5eXzcqC3t9av/ hMzfmc+v2a5lDYrE1R3g5nb85A== X-Google-Smtp-Source: ABdhPJzXnidy0NB75gUwHIVSkZRVeRst/1zieIZpV1fgsGvQbDm4p2FbHJlV02Cn81qtkFokiEkN9g== X-Received: by 2002:ac8:7d42:0:b0:2de:4d3b:11cf with SMTP id h2-20020ac87d42000000b002de4d3b11cfmr368624qtb.415.1646424651107; Fri, 04 Mar 2022 12:10:51 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id 20-20020ac84e94000000b002de8f564305sm4605481qtp.1.2022.03.04.12.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 12:10:50 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH v2 7/7] RISC-V: KVM: Support sstc extension Date: Fri, 4 Mar 2022 12:10:20 -0800 Message-Id: <20220304201020.810380-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com> References: <20220304201020.810380-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_121052_004322_B0ADE202 X-CRM114-Status: GOOD ( 19.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sstc extension allows the guest to program the vstimecmp CSR directly instead of making an SBI call to the hypervisor to program the next event. The timer interrupt is also directly injected to the guest by the hardware in this case. To maintain backward compatibility, the hypervisors also update the vstimecmp in an SBI set_time call if the hardware supports it. Thus, the older kernels in guest also take advantage of the sstc extension. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_host.h | 1 + arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/main.c | 12 ++- arch/riscv/kvm/vcpu.c | 4 +- arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++- 6 files changed, 158 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 99ef6a120617..2ed93cdb334f 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -135,6 +135,7 @@ struct kvm_vcpu_csr { unsigned long hvip; unsigned long vsatp; unsigned long scounteren; + u64 vstimecmp; }; struct kvm_vcpu_arch { diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h index 375281eb49e0..a24a265f3ccb 100644 --- a/arch/riscv/include/asm/kvm_vcpu_timer.h +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -28,6 +28,11 @@ struct kvm_vcpu_timer { u64 next_cycles; /* Underlying hrtimer instance */ struct hrtimer hrt; + + /* Flag to check if sstc is enabled or not */ + bool sstc_enabled; + /* A function pointer to switch between stimecmp or hrtimer at runtime */ + int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles); }; int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles); @@ -39,6 +44,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu); int kvm_riscv_guest_timer_init(struct kvm *kvm); - +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu); #endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 92bd469e2ba6..d2f02ba1947a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -96,6 +96,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_H, KVM_RISCV_ISA_EXT_I, KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_SSTC, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 2e5ca43c8c49..83c4db7fc35f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -32,7 +32,7 @@ int kvm_arch_hardware_setup(void *opaque) int kvm_arch_hardware_enable(void) { - unsigned long hideleg, hedeleg; + unsigned long hideleg, hedeleg, henvcfg; hedeleg = 0; hedeleg |= (1UL << EXC_INST_MISALIGNED); @@ -51,6 +51,16 @@ int kvm_arch_hardware_enable(void) csr_write(CSR_HCOUNTEREN, -1UL); + if (riscv_isa_extension_available(NULL, SSTC)) { +#ifdef CONFIG_64BIT + henvcfg = csr_read(CSR_HENVCFG); + csr_write(CSR_HENVCFG, henvcfg | 1UL<arch.isa); kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); + kvm_riscv_vcpu_timer_save(vcpu); csr_write(CSR_HGATP, 0); csr->vsstatus = csr_read(CSR_VSSTATUS); diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 5c4c37ff2d48..d226a931de92 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) return 0; } -int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles) +{ +#if __riscv_xlen == 32 + csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF); + csr_write(CSR_VSTIMECMPH, ncycles >> 32); +#else + csr_write(CSR_VSTIMECMP, ncycles); +#endif + return 0; +} + +static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles) { struct kvm_vcpu_timer *t = &vcpu->arch.timer; struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; @@ -88,6 +99,68 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) return 0; } +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + return t->timer_next_event(vcpu, ncycles); +} + +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h) +{ + u64 delta_ns; + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer); + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + + if (kvm_riscv_current_cycles(gt) < t->next_cycles) { + delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t); + hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns)); + return HRTIMER_RESTART; + } + + t->next_set = false; + kvm_vcpu_kick(vcpu); + + return HRTIMER_NORESTART; +} + +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp; + + if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t) || + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER)) + return true; + else + return false; +} + +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + u64 delta_ns; + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp; + + if (!t->init_done) + return; + + delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t); + if (delta_ns) { + t->next_cycles = vstimecmp_val; + hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL); + t->next_set = true; + } +} + +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu) +{ + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); +} + int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -180,10 +253,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) return -EINVAL; hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; t->init_done = true; t->next_set = false; + /* Enable sstc for every vcpu if available in hardware */ + if (riscv_isa_extension_available(NULL, SSTC)) { + t->sstc_enabled = true; + t->hrt.function = kvm_riscv_vcpu_vstimer_expired; + t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp; + } else { + t->sstc_enabled = false; + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; + t->timer_next_event = kvm_riscv_vcpu_update_hrtimer; + } + return 0; } @@ -202,7 +285,7 @@ int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); } -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu) { struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; @@ -214,6 +297,55 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) #endif } +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + kvm_riscv_vcpu_update_timedelta(vcpu); + + if (!t->sstc_enabled) + return; + + csr = &vcpu->arch.guest_csr; +#ifdef CONFIG_64BIT + csr_write(CSR_VSTIMECMP, csr->vstimecmp); +#else + csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp); + csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32)); +#endif + + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + kvm_riscv_vcpu_timer_unblocking(vcpu); +} + +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + if (!t->sstc_enabled) + return; + + csr = &vcpu->arch.guest_csr; + t = &vcpu->arch.timer; +#ifdef CONFIG_64BIT + csr->vstimecmp = csr_read(CSR_VSTIMECMP); +#else + csr->vstimecmp = csr_read(CSR_VSTIMECMP); + csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) << 32; +#endif + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + if (kvm_vcpu_is_blocking(vcpu)) + kvm_riscv_vcpu_timer_blocking(vcpu); +} + int kvm_riscv_guest_timer_init(struct kvm *kvm) { struct kvm_guest_timer *gt = &kvm->arch.timer;