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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id k1-20020a056a00168100b004e0e45a39c6sm14447385pfc.181.2022.03.06.21.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Mar 2022 21:44:34 -0800 (PST) From: Zong Li To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, krzysztof.kozlowski@canonical.com, conor.dooley@microchip.com, geert@linux-m68k.org, bin.meng@windriver.com, green.wan@sifive.com, vkoul@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Zong Li , Palmer Dabbelt , Rob Herring Subject: [PATCH v7 1/3] dt-bindings: dma-engine: sifive,fu540: Add dma-channels property and modify compatible Date: Mon, 7 Mar 2022 13:44:24 +0800 Message-Id: <1e75ad35b7d1fb6156781bf9c545e1f084c43a1e.1646631717.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add dma-channels property, then we can determine how many channels there by device tree, rather than statically defining it in PDMA driver. In addition, we also modify the compatible for PDMA versioning scheme. Signed-off-by: Zong Li Suggested-by: Palmer Dabbelt Reviewed-by: Rob Herring Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Acked-by: Krzysztof Kozlowski --- .../bindings/dma/sifive,fu540-c000-pdma.yaml | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index 75ad898c59bc..92f410f54d72 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -25,7 +25,15 @@ description: | properties: compatible: items: - - const: sifive,fu540-c000-pdma + - enum: + - sifive,fu540-c000-pdma + - const: sifive,pdma0 + description: + Should be "sifive,-pdma" and "sifive,pdma". + Supported compatible strings are - + "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the + SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block + with no chip integration tweaks. reg: maxItems: 1 @@ -34,6 +42,12 @@ properties: minItems: 1 maxItems: 8 + dma-channels: + description: For backwards-compatibility, the default value is 4 + minimum: 1 + maximum: 4 + default: 4 + '#dma-cells': const: 1 @@ -48,8 +62,9 @@ additionalProperties: false examples: - | dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; reg = <0x3000000 0x8000>; + dma-channels = <4>; interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; #dma-cells = <1>; }; From patchwork Mon Mar 7 05:44:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12771182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1461C433EF for ; Mon, 7 Mar 2022 05:44:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235398AbiCGFpg (ORCPT ); Mon, 7 Mar 2022 00:45:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235386AbiCGFpd (ORCPT ); Mon, 7 Mar 2022 00:45:33 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AB314B1EB for ; Sun, 6 Mar 2022 21:44:39 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id e13so12822432plh.3 for ; Sun, 06 Mar 2022 21:44:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O3fmm4nvalmQleWa1byPzKYwRMYCW7Pxtk8Gk5epwAE=; b=fl6tc4VC43ATK5SOcF9SU87whyYsM0/UNtzRWx1LVbVHj6trycs4EzVouaEEZrcpKE YC3iW3uXyA9P+iYT3vY/qMfHCuVwCd8S1tqyHxVxtac71XDsOIu+nMvTTY7QMQ/RNvWB KeuqZjyWE+hUEVXjKZhptxrbfUOlV7XU4tRNHayODoaEB7NjoS+o2a0Mnp7UWJLF2bIj jTC291bbLpDvmrw5q6vX//tuLYirSx6QQATmcn5dOYn1ETGZiqQ25erIbgBbeog9VnzY VuA8xqF0bs5B/8CdvaQLH3WrRzU7N/+YFucgiQo1AJA4I+6uqV7BbPIsg10CFjo09Fv0 NrSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O3fmm4nvalmQleWa1byPzKYwRMYCW7Pxtk8Gk5epwAE=; b=qf6TNq/1cOkbA/NHCJqBDQSyO+VoD7yOOocyqIOfkFs5gYEGs+3lo9BLOaduqJgFIG iupj3Zhbq7VW+NzOtez3IXLwvhAlA5qL4tF7GpICntr9wmsllu5rESZCgVUtu8+NaXKi 2iLWK22aOeSL2S33/QqWbnlbhWsAUU3yiZSNVazkOWb6yDxEqCptxkX+k1vbgD8lLlXd hNf+Y4schOynu5HJVHxbvxmiizMYTIK2ciPEXAuUM2E8orvLVTQgT4c2QA7oYmtwrXlN aPbZ2Kb11aqA397pjGUWWyaSHgbOqErnGhW9fSbgUel7ZF9n6k7ZpubPlNkUCrzsbocG TdAw== X-Gm-Message-State: AOAM530PXWBKKscLlTqN+7CJys0blAuF+qzIxydNZSTLyYNZs3AAHRnh MC+YgWjEiH+Q0XxegiS6WG4bRCgNSk+8ng== X-Google-Smtp-Source: ABdhPJxmHZJzk1QvRtzUfWeyEP/BccLNeBIBfFdyOzW6/M5gESO4UArQMmmb+9KSWVVM69HaTw8K5Q== X-Received: by 2002:a17:90b:314b:b0:1bf:7c7:d304 with SMTP id ip11-20020a17090b314b00b001bf07c7d304mr23359289pjb.224.1646631878754; Sun, 06 Mar 2022 21:44:38 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id k1-20020a056a00168100b004e0e45a39c6sm14447385pfc.181.2022.03.06.21.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Mar 2022 21:44:38 -0800 (PST) From: Zong Li To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, krzysztof.kozlowski@canonical.com, conor.dooley@microchip.com, geert@linux-m68k.org, bin.meng@windriver.com, green.wan@sifive.com, vkoul@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Zong Li , Palmer Dabbelt Subject: [PATCH v7 2/3] riscv: dts: Add dma-channels property and modify compatible Date: Mon, 7 Mar 2022 13:44:25 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add dma-channels property, then we can determine how many channels there by device tree, in addition, we add the pdma versioning scheme for compatible. Signed-off-by: Zong Li Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Acked-by: Conor Dooley --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ++- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 869aaf0d5c06..d8869ec99945 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -187,11 +187,12 @@ plic: interrupt-controller@c000000 { }; dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; + dma-channels = <4>; #dma-cells = <1>; }; diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 3eef52b1a59b..6a3011180846 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -168,11 +168,12 @@ uart0: serial@10010000 { status = "disabled"; }; dma: dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic0>; interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; + dma-channels = <4>; #dma-cells = <1>; }; uart1: serial@10011000 { From patchwork Mon Mar 7 05:44:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12771183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41F2BC433F5 for ; Mon, 7 Mar 2022 05:44:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235394AbiCGFpp (ORCPT ); Mon, 7 Mar 2022 00:45:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235383AbiCGFpj (ORCPT ); Mon, 7 Mar 2022 00:45:39 -0500 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E7094B426 for ; Sun, 6 Mar 2022 21:44:42 -0800 (PST) Received: by mail-pl1-x633.google.com with SMTP id 9so12813750pll.6 for ; Sun, 06 Mar 2022 21:44:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SjzY9j/Keh5kcP1plUzMyATlCp3344jlI/9GvjcvYoo=; b=H3ukiKpOjrWALA8cOGscza/eG7Y9H2VLma85d2rXV3BXdDxL23AADulFiqldBByUvF WT8geB6FfT0goNe7T7/ASGaN1cwQlt950sSp9K3T3FyagkBawU++fkoDTJ2WEYkQ58MI u2zlWVYRjMM4RFgRkJTVEc8HLTG835uxlwm3VLCxckYcnJl5S7+o4cVvSr0Be4cAbixI IojXvz0/AEovaZpUoitVfkC0P1dp3LchCuHwZWp3okcn/ivmURm5SGsScCSuQ2aQHZbg nZHdTH3xFtJOZxWtnStzka2lW4RKhHGLFSyKabTYgkBm1y9JJy1AuXOQ9JhkDlDhwZVO Dkaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SjzY9j/Keh5kcP1plUzMyATlCp3344jlI/9GvjcvYoo=; b=SfuOfbCBahTbgXr0NVQCEtl/1dkKPO+ZWH9yZ4I0n+NMrevYfugFFucEztj/Sg7F6W /iAaxEY2zJ0jKO0Rj3YXLUCZZF0eivFk349Pju0E/HXiILt6KlR6zbgg+SR3fv/TBfS3 bz4INBj9V+fe1d7c5B/JeBB5ikkoEoHQcEgdzrdcEcaKGz9J1fZeE2fDFlfoiyzka/Vj MG2ZJaVkV6BbeGZ9JieBimUim8BBwKOluAdHD7DEftGQbkjBUX56BHgt2jeL7RaP5uWZ I0jglRx2ZVdg2VBileux+YndI/ape/j3s/rVnnY4Y10NJ6dm9BFMVshf1fPOkMTHBv2J pP3g== X-Gm-Message-State: AOAM5322F0luF+M/IgjH7tlJRFa8MO7toDM5142hkyVdr4467sreSE7+ wBgdkhTbNKtB4LPw+gQrLVr/1Q== X-Google-Smtp-Source: ABdhPJwmsg2NvIPGJKgc2QYAjoAgRREp5vq1gE8kB+AJyhWvnd21cTaR/lWtZMx27QIwQX1NVuEHUQ== X-Received: by 2002:a17:90a:950b:b0:1bf:4f9b:710e with SMTP id t11-20020a17090a950b00b001bf4f9b710emr6343302pjo.241.1646631882007; Sun, 06 Mar 2022 21:44:42 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id k1-20020a056a00168100b004e0e45a39c6sm14447385pfc.181.2022.03.06.21.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Mar 2022 21:44:41 -0800 (PST) From: Zong Li To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, krzysztof.kozlowski@canonical.com, conor.dooley@microchip.com, geert@linux-m68k.org, bin.meng@windriver.com, green.wan@sifive.com, vkoul@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Zong Li , Palmer Dabbelt Subject: [PATCH v7 3/3] dmaengine: sf-pdma: Get number of channel by device tree Date: Mon, 7 Mar 2022 13:44:26 +0800 Message-Id: <73fcb88608aa18c02e92f1641441c073a7912ea3.1646631717.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org It currently assumes that there are always four channels, it would cause the error if there is actually less than four channels. Change that by getting number of channel from device tree. For backwards-compatibility, it uses the default value (i.e. 4) when there is no 'dma-channels' information in dts. Signed-off-by: Zong Li Acked-by: Palmer Dabbelt --- drivers/dma/sf-pdma/sf-pdma.c | 24 ++++++++++++++++-------- drivers/dma/sf-pdma/sf-pdma.h | 8 ++------ 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index f12606aeff87..db5a4ef76077 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -482,23 +482,30 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma) static int sf_pdma_probe(struct platform_device *pdev) { struct sf_pdma *pdma; - struct sf_pdma_chan *chan; struct resource *res; - int len, chans; - int ret; + int ret, n_chans; const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES | DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES; - chans = PDMA_NR_CH; - len = sizeof(*pdma) + sizeof(*chan) * chans; - pdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + ret = of_property_read_u32(pdev->dev.of_node, "dma-channels", &n_chans); + if (ret) { + /* backwards-compatibility for no dma-channels property */ + dev_dbg(&pdev->dev, "set number of channels to default value: 4\n"); + n_chans = PDMA_MAX_NR_CH; + } else if (n_chans > PDMA_MAX_NR_CH) { + dev_err(&pdev->dev, "the number of channels exceeds the maximum\n"); + return -EINVAL; + } + + pdma = devm_kzalloc(&pdev->dev, struct_size(pdma, chans, n_chans), + GFP_KERNEL); if (!pdma) return -ENOMEM; - pdma->n_chans = chans; + pdma->n_chans = n_chans; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pdma->membase = devm_ioremap_resource(&pdev->dev, res); @@ -556,7 +563,7 @@ static int sf_pdma_remove(struct platform_device *pdev) struct sf_pdma_chan *ch; int i; - for (i = 0; i < PDMA_NR_CH; i++) { + for (i = 0; i < pdma->n_chans; i++) { ch = &pdma->chans[i]; devm_free_irq(&pdev->dev, ch->txirq, ch); @@ -574,6 +581,7 @@ static int sf_pdma_remove(struct platform_device *pdev) static const struct of_device_id sf_pdma_dt_ids[] = { { .compatible = "sifive,fu540-c000-pdma" }, + { .compatible = "sifive,pdma0" }, {}, }; MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids); diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h index 0c20167b097d..dcb3687bd5da 100644 --- a/drivers/dma/sf-pdma/sf-pdma.h +++ b/drivers/dma/sf-pdma/sf-pdma.h @@ -22,11 +22,7 @@ #include "../dmaengine.h" #include "../virt-dma.h" -#define PDMA_NR_CH 4 - -#if (PDMA_NR_CH != 4) -#error "Please define PDMA_NR_CH to 4" -#endif +#define PDMA_MAX_NR_CH 4 #define PDMA_BASE_ADDR 0x3000000 #define PDMA_CHAN_OFFSET 0x1000 @@ -118,7 +114,7 @@ struct sf_pdma { void __iomem *membase; void __iomem *mappedbase; u32 n_chans; - struct sf_pdma_chan chans[PDMA_NR_CH]; + struct sf_pdma_chan chans[]; }; #endif /* _SF_PDMA_H */