From patchwork Mon Mar 7 08:53:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9577FC433FE for ; Mon, 7 Mar 2022 08:53:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234001AbiCGIyQ (ORCPT ); Mon, 7 Mar 2022 03:54:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233903AbiCGIyP (ORCPT ); Mon, 7 Mar 2022 03:54:15 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38E6817E3E; Mon, 7 Mar 2022 00:53:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643201; x=1678179201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NlMzKT33h6Q6qqc7z4CyhD39p7yWH93N/HDO0fmlpcU=; b=B88QsVAbzPv7IhwKbPHn3PQbq+M5H0fJiV6f8h6G8RRw1dulhqgzpArr Cp2Bs/6GLd5x0+7AefmmWPHFUZLwVON3vNqLwc99WPDKGqw4kxzaDNHdv 1LpIZty7/aFUjRuhBqhZ4WCaXHesZ8ukzzNqb6Atl5+cdQzgMWVH9e7bw MQog/UJ553gt3bIJTb/c4TOUhh6TokmK6EADHhlJLAshyJG0C6fQuYLFE NASOQrH9+RnPoobt/Ng4eY08R1/mJpdsA/g5+ENZ6emeKCYokGU3HaTBr JR2Ggvh4IOoTKdRjvFiPRxrBXfp2mHbXLjeALqrjcqwX5fMXna1RRGe9j Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771776" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771776" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033482" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:16 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 01/10] perf/x86: Fix native_perf_sched_clock_from_tsc() with __sched_clock_offset Date: Mon, 7 Mar 2022 10:53:03 +0200 Message-Id: <20220307085312.1814506-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org native_perf_sched_clock_from_tsc() is used to produce a time value that can be consistent with perf_clock(). Consequently, it should be adjusted by __sched_clock_offset, the same as perf_clock() would be. Fixes: 698eff6355f735 ("sched/clock, x86/perf: Fix perf test tsc") Signed-off-by: Adrian Hunter --- arch/x86/kernel/tsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a698196377be..d9fe277c2471 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -242,7 +242,7 @@ u64 native_sched_clock(void) */ u64 native_sched_clock_from_tsc(u64 tsc) { - return cycles_2_ns(tsc); + return cycles_2_ns(tsc) + __sched_clock_offset; } /* We need to define a real function for sched_clock, to override the From patchwork Mon Mar 7 08:53:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FAA9C433EF for ; Mon, 7 Mar 2022 08:53:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233903AbiCGIyY (ORCPT ); Mon, 7 Mar 2022 03:54:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234149AbiCGIyV (ORCPT ); Mon, 7 Mar 2022 03:54:21 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6907B15A03; Mon, 7 Mar 2022 00:53:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643205; x=1678179205; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=usTsLotS3IpAdfGPpvMJNzmulAHU4pEVranhDE3wmwA=; b=H8e/eyllzvW1EJap/hi2pUrR6Vr6u2Alf00n+QeA20YWB8eVwtuzxMIQ g0oZcswQ58h/eJjvsBqivsPOtUWL6ADHMfWsV+CH+1AdT7nWS40VR0j8O 3+MnLfuUSClsEiEBh8lz5HhTCAAdQZv8B5e5Gx6b/xroWCbr797JwQiTk WXPnD8p6aWRZ4ScdafPwvy8Z4hWezVsMr9LKxpUUFv6HSa85jm4ESlk+m 5V4Ar76iOHgroKy2y1N2BdlgZIIp4XR09Amqs6eOcJMf46V2auqUkt7EX rPLRekjjhsEAPQsI9+ZmdfFR44xQwrAbRo+of7NjhLMiPY3J/S0TmDaZq g==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771793" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771793" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033497" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:21 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 02/10] perf/x86: Add support for TSC as a perf event clock Date: Mon, 7 Mar 2022 10:53:04 +0200 Message-Id: <20220307085312.1814506-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, using Intel PT to trace a VM guest is limited to kernel space because decoding requires side band events such as MMAP and CONTEXT_SWITCH. While these events can be collected for the host, there is not a way to do that yet for a guest. One approach, would be to collect them inside the guest, but that would require being able to synchronize with host timestamps. The motivation for this patch is to provide a clock that can be used within a VM guest, and that correlates to a VM host clock. In the case of TSC, if the hypervisor leaves rdtsc alone, the TSC value will be subject only to the VMCS TSC Offset and Scaling. Adjusting for that would make it possible to inject events from a guest perf.data file, into a host perf.data file. Thus making possible the collection of VM guest side band for Intel PT decoding. There are other potential benefits of TSC as a perf event clock: - ability to work directly with TSC - ability to inject non-Intel-PT-related events from a guest Signed-off-by: Adrian Hunter --- arch/x86/events/core.c | 14 ++++++++++++++ arch/x86/include/asm/perf_event.h | 3 +++ include/uapi/linux/time.h | 11 +++++++++++ kernel/events/core.c | 7 +++++++ 4 files changed, 35 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e686c5e0537b..e2ad3f9cca93 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2728,6 +2728,15 @@ void arch_perf_update_userpage(struct perf_event *event, !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); userpg->pmc_width = x86_pmu.cntval_bits; + if (event->attr.use_clockid && event->attr.clockid == CLOCK_PERF_HW_CLOCK) { + userpg->cap_user_time_zero = 1; + userpg->time_mult = 1; + userpg->time_shift = 0; + userpg->time_offset = 0; + userpg->time_zero = 0; + return; + } + if (!using_native_sched_clock() || !sched_clock_stable()) return; @@ -2980,6 +2989,11 @@ unsigned long perf_misc_flags(struct pt_regs *regs) return misc; } +u64 perf_hw_clock(void) +{ + return rdtsc_ordered(); +} + void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) { cap->version = x86_pmu.version; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 8fc1b5003713..3c75459bdeaf 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -451,6 +451,9 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs); extern unsigned long perf_misc_flags(struct pt_regs *regs); #define perf_misc_flags(regs) perf_misc_flags(regs) +extern u64 perf_hw_clock(void); +#define perf_hw_clock perf_hw_clock + #include /* diff --git a/include/uapi/linux/time.h b/include/uapi/linux/time.h index 4f4b6e48e01c..95602420122e 100644 --- a/include/uapi/linux/time.h +++ b/include/uapi/linux/time.h @@ -67,6 +67,17 @@ struct timezone { #define CLOCKS_MASK (CLOCK_REALTIME | CLOCK_MONOTONIC) #define CLOCKS_MONO CLOCK_MONOTONIC +/* + * If supported, clockid value for use in struct perf_event_attr to select an + * architecture dependent hardware clock. Note this means the unit of time is + * ticks not nanoseconds. WARNING: This clock may not be stable or well-behaved + * in any way, including varying across different CPUs. + * + * On x86, this is provided by the rdtsc instruction, and is not + * paravirtualized. Note the warning above can also apply to TSC. + */ +#define CLOCK_PERF_HW_CLOCK 0x10000000 + /* * The various flags for setting POSIX.1b interval timers: */ diff --git a/kernel/events/core.c b/kernel/events/core.c index 6859229497b1..e2f06384de50 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -12034,6 +12034,13 @@ static int perf_event_set_clock(struct perf_event *event, clockid_t clk_id) event->clock = &ktime_get_clocktai_ns; break; +#ifdef perf_hw_clock + case CLOCK_PERF_HW_CLOCK: + event->clock = &perf_hw_clock; + nmi_safe = true; + break; +#endif + default: return -EINVAL; } From patchwork Mon Mar 7 08:53:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6E53C433EF for ; Mon, 7 Mar 2022 08:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235939AbiCGIy1 (ORCPT ); Mon, 7 Mar 2022 03:54:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235467AbiCGIyY (ORCPT ); Mon, 7 Mar 2022 03:54:24 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C72C41A822; Mon, 7 Mar 2022 00:53:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643209; x=1678179209; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KlA1x9Cb1KblGKd9Hqgo2TLuaRy9LBgMjlsA9b/F7qw=; b=m4IzEZb+nsmAJzl/NK/VRp4p3CR7teLqe+JWlxANsgUd6nP7ZzzCJNPW d6GZRHlq8suL80wjdmmBqPbiPpPOJ92r5q5QkJqPcrIfEajPhOXDzj86D WHZwzIYuvgji3hQfRNCxGCLdeVjMUEe1LI3R2yKJFw6/Bk8Vz68dnEHno /ZuSnNbwF/sfTw3Xdml2zIoozL3eDZWkS/+d4CA0/cuuOcCDXqhCvtTxp 3CLqbySO+CjY0YoROleqHGgGokoCa+ZSFIuMOcdT9yBAWF30rK4lcuEzE 8kGtYsNRvn0I8Cyk1m2+51bK7HheqELgLT0c5rlskFu0uizOQsA0wWrtY A==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771802" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771802" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033514" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:25 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 03/10] perf/x86: Add support for TSC in nanoseconds as a perf event clock Date: Mon, 7 Mar 2022 10:53:05 +0200 Message-Id: <20220307085312.1814506-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, when Intel PT is used within a VM guest, it is not possible to make use of TSC because perf clock is subject to paravirtualization. If the hypervisor leaves rdtsc alone, the TSC value will be subject only to the VMCS TSC Offset and Scaling, the same as the TSC packet from Intel PT. The new clock is based on rdtsc and not subject to paravirtualization. Hence it would be possible to use this new clock for Intel PT decoding within a VM guest. Signed-off-by: Adrian Hunter --- arch/x86/events/core.c | 39 ++++++++++++++++++++----------- arch/x86/include/asm/perf_event.h | 2 ++ include/uapi/linux/time.h | 6 +++++ kernel/events/core.c | 6 +++++ 4 files changed, 40 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e2ad3f9cca93..bd3781fe5faa 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "perf_event.h" @@ -2728,16 +2729,26 @@ void arch_perf_update_userpage(struct perf_event *event, !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); userpg->pmc_width = x86_pmu.cntval_bits; - if (event->attr.use_clockid && event->attr.clockid == CLOCK_PERF_HW_CLOCK) { - userpg->cap_user_time_zero = 1; - userpg->time_mult = 1; - userpg->time_shift = 0; - userpg->time_offset = 0; - userpg->time_zero = 0; - return; + if (event->attr.use_clockid) { + if (event->attr.clockid == CLOCK_PERF_HW_CLOCK) { + userpg->cap_user_time_zero = 1; + userpg->time_mult = 1; + userpg->time_shift = 0; + userpg->time_offset = 0; + userpg->time_zero = 0; + return; + } + if (event->attr.clockid == CLOCK_PERF_HW_CLOCK_NS) + userpg->cap_user_time_zero = 1; + } + + if (using_native_sched_clock() && sched_clock_stable()) { + userpg->cap_user_time = 1; + if (!event->attr.use_clockid) + userpg->cap_user_time_zero = 1; } - if (!using_native_sched_clock() || !sched_clock_stable()) + if (!userpg->cap_user_time && !userpg->cap_user_time_zero) return; cyc2ns_read_begin(&data); @@ -2748,19 +2759,16 @@ void arch_perf_update_userpage(struct perf_event *event, * Internal timekeeping for enabled/running/stopped times * is always in the local_clock domain. */ - userpg->cap_user_time = 1; userpg->time_mult = data.cyc2ns_mul; userpg->time_shift = data.cyc2ns_shift; userpg->time_offset = offset - now; /* * cap_user_time_zero doesn't make sense when we're using a different - * time base for the records. + * time base for the records, except for CLOCK_PERF_HW_CLOCK_NS. */ - if (!event->attr.use_clockid) { - userpg->cap_user_time_zero = 1; + if (userpg->cap_user_time_zero) userpg->time_zero = offset; - } cyc2ns_read_end(); } @@ -2994,6 +3002,11 @@ u64 perf_hw_clock(void) return rdtsc_ordered(); } +u64 perf_hw_clock_ns(void) +{ + return native_sched_clock_from_tsc(perf_hw_clock()); +} + void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) { cap->version = x86_pmu.version; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 3c75459bdeaf..b429b473401e 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -453,6 +453,8 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); extern u64 perf_hw_clock(void); #define perf_hw_clock perf_hw_clock +extern u64 perf_hw_clock_ns(void); +#define perf_hw_clock_ns perf_hw_clock_ns #include diff --git a/include/uapi/linux/time.h b/include/uapi/linux/time.h index 95602420122e..d527c42719f7 100644 --- a/include/uapi/linux/time.h +++ b/include/uapi/linux/time.h @@ -77,6 +77,12 @@ struct timezone { * paravirtualized. Note the warning above can also apply to TSC. */ #define CLOCK_PERF_HW_CLOCK 0x10000000 +/* + * Same as CLOCK_PERF_HW_CLOCK but in nanoseconds. Note support of + * CLOCK_PERF_HW_CLOCK_NS does not necesssarily imply support of + * CLOCK_PERF_HW_CLOCK or vice versa. + */ +#define CLOCK_PERF_HW_CLOCK_NS 0x10000001 /* * The various flags for setting POSIX.1b interval timers: diff --git a/kernel/events/core.c b/kernel/events/core.c index e2f06384de50..284a44b385cf 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -12040,6 +12040,12 @@ static int perf_event_set_clock(struct perf_event *event, clockid_t clk_id) nmi_safe = true; break; #endif +#ifdef perf_hw_clock_ns + case CLOCK_PERF_HW_CLOCK_NS: + event->clock = &perf_hw_clock_ns; + nmi_safe = true; + break; +#endif default: return -EINVAL; From patchwork Mon Mar 7 08:53:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A621C433F5 for ; Mon, 7 Mar 2022 08:53:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236173AbiCGIye (ORCPT ); Mon, 7 Mar 2022 03:54:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235718AbiCGIy3 (ORCPT ); Mon, 7 Mar 2022 03:54:29 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E0071A3BB; Mon, 7 Mar 2022 00:53:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643214; x=1678179214; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=InEJUMEsvt88WaNNj0iD8NVomYggC4uoiXvwBLY4GOQ=; b=UlQh8kSSskaFDdk2x7Sx4vbSCLCt6s7idqqjuwGsv+wdFK+Rcl0sp165 embURodDEoQapM8+QjoHW9BpUAy9NHaTcWDTN2mqmPEGAf98hAiZ1Y71z klux9DYywwV8dq9th+m3VuN9v4AeeQgxGxcPycmEvqZgsVa0oiswfB+3h Xn6xa49U3oCvE+3WFc24lBREhQV+IfRmfqdv87tm52OoSfC1p51ITXJb2 JpTvoYzLWB2cLgsBR5hX83rqvE6vpuSYOEckiITyK2sjqgPw6WF6NePW8 fSzR4NYbubai+V2yuAHWHe1ZhEgQ4uuaT01D7zi7AaS9pl2uLG/Q8k9OP A==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771811" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771811" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033532" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:29 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 04/10] perf tools: Add new perf clock IDs Date: Mon, 7 Mar 2022 10:53:06 +0200 Message-Id: <20220307085312.1814506-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add support for new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. Signed-off-by: Adrian Hunter --- tools/perf/Documentation/perf-record.txt | 11 ++++++++++- tools/perf/builtin-record.c | 2 +- tools/perf/util/clockid.c | 5 +++++ tools/perf/util/clockid.h | 8 ++++++++ 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index 465be4e62a17..d7e609a5f824 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -444,7 +444,16 @@ Record running and enabled time for read events (:S) Sets the clock id to use for the various time fields in the perf_event_type records. See clock_gettime(). In particular CLOCK_MONOTONIC and CLOCK_MONOTONIC_RAW are supported, some events might also allow -CLOCK_BOOTTIME, CLOCK_REALTIME and CLOCK_TAI. +CLOCK_BOOTTIME, CLOCK_REALTIME and CLOCK_TAI. In addition, the kernel might +support CLOCK_PERF_HW_CLOCK to select an architecture dependent hardware +clock, for which the unit of time is ticks not nanoseconds. On x86, +CLOCK_PERF_HW_CLOCK is provided by the rdtsc instruction, and is not +paravirtualized. There is also CLOCK_PERF_HW_CLOCK_NS which is the same as +CLOCK_PERF_HW_CLOCK, but converted to nanoseconds. Note support of +CLOCK_PERF_HW_CLOCK_NS does not necessarily imply support of +CLOCK_PERF_HW_CLOCK or vice versa. Be warned, CLOCK_PERF_HW_CLOCK and +CLOCK_PERF_HW_CLOCK_NS may not be stable or well-behaved in any way, +including varying across different CPUs. That warning can also apply to TSC. -S:: --snapshot:: diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 0b4abed555d8..c17b13528469 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -1973,7 +1973,7 @@ static int record__init_clock(struct record *rec) struct timeval ref_tod; u64 ref; - if (!rec->opts.use_clockid) + if (!rec->opts.use_clockid || rec->opts.clockid >= CLOCK_PERF_HW_CLOCK) return 0; if (rec->opts.use_clockid && rec->opts.clockid_res_ns) diff --git a/tools/perf/util/clockid.c b/tools/perf/util/clockid.c index 74365a5d99c1..380429725df1 100644 --- a/tools/perf/util/clockid.c +++ b/tools/perf/util/clockid.c @@ -49,6 +49,9 @@ static const struct clockid_map clockids[] = { CLOCKID_MAP("real", CLOCK_REALTIME), CLOCKID_MAP("boot", CLOCK_BOOTTIME), + CLOCKID_MAP("perf_hw_clock", CLOCK_PERF_HW_CLOCK), + CLOCKID_MAP("perf_hw_clock_ns", CLOCK_PERF_HW_CLOCK_NS), + CLOCKID_END, }; @@ -57,6 +60,8 @@ static int get_clockid_res(clockid_t clk_id, u64 *res_ns) struct timespec res; *res_ns = 0; + if (clk_id >= CLOCK_PERF_HW_CLOCK) + return 0; if (!clock_getres(clk_id, &res)) *res_ns = res.tv_nsec + res.tv_sec * NSEC_PER_SEC; else diff --git a/tools/perf/util/clockid.h b/tools/perf/util/clockid.h index 9b49b4711c76..af396b14ae8b 100644 --- a/tools/perf/util/clockid.h +++ b/tools/perf/util/clockid.h @@ -8,4 +8,12 @@ int parse_clockid(const struct option *opt, const char *str, int unset); const char *clockid_name(clockid_t clk_id); +#ifndef CLOCK_PERF_HW_CLOCK +#define CLOCK_PERF_HW_CLOCK 0x10000000 +#endif + +#ifndef CLOCK_PERF_HW_CLOCK_NS +#define CLOCK_PERF_HW_CLOCK_NS 0x10000001 +#endif + #endif From patchwork Mon Mar 7 08:53:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 554A0C433EF for ; Mon, 7 Mar 2022 08:53:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236221AbiCGIyh (ORCPT ); Mon, 7 Mar 2022 03:54:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236227AbiCGIyc (ORCPT ); Mon, 7 Mar 2022 03:54:32 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49FD91A39C; Mon, 7 Mar 2022 00:53:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643218; x=1678179218; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NJf6gmZBiPlpFezwWwQIi57qinvlgQu7aMtORWhAzg4=; b=eqOSdDsjlqsZCMheXKKEcjMXsEPWse8Rd7cUqeM3x27L1a8xYD1Gwvpw T4rCkH99knyiY+0VuyKMDfGIVWxwimSMf6NSgLMVl0ySicc+Uxqt/+MqQ /fNNcVEYQTxzx/De9U874utzfvRrpGrXypSzou4EZUcPK/itBIjg7bNQs RnVVYwVTIShlATWXiyuuqe4P/0eMo+nDScRHoKfwx3zcyjOLHzOWAkqbe aneqjKjU6/xw7SW41FXxJx1GTAnKnmiRkDqYdpVxzhwcy9wVCIyZYL6yZ pk97sEBllLPyAAJ/l2adNfHmuz+reD+eNekcX07wptbpByRPMC9ukz2a7 A==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771839" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771839" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033546" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:33 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 05/10] perf tools: Add API probes for new clock IDs Date: Mon, 7 Mar 2022 10:53:07 +0200 Message-Id: <20220307085312.1814506-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add ability to check whether the kernel supports new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. They will be used in a subsequent patch. Signed-off-by: Adrian Hunter --- tools/perf/util/perf_api_probe.c | 23 +++++++++++++++++++++++ tools/perf/util/perf_api_probe.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/tools/perf/util/perf_api_probe.c b/tools/perf/util/perf_api_probe.c index c28dd50bd571..e3004791d45c 100644 --- a/tools/perf/util/perf_api_probe.c +++ b/tools/perf/util/perf_api_probe.c @@ -5,6 +5,7 @@ #include "util/evlist.h" #include "util/evsel.h" #include "util/parse-events.h" +#include "util/clockid.h" #include "util/perf_api_probe.h" #include #include @@ -109,6 +110,18 @@ static void perf_probe_cgroup(struct evsel *evsel) evsel->core.attr.cgroup = 1; } +static void perf_probe_hw_clock(struct evsel *evsel) +{ + evsel->core.attr.use_clockid = 1; + evsel->core.attr.clockid = CLOCK_PERF_HW_CLOCK; +} + +static void perf_probe_hw_clock_ns(struct evsel *evsel) +{ + evsel->core.attr.use_clockid = 1; + evsel->core.attr.clockid = CLOCK_PERF_HW_CLOCK_NS; +} + bool perf_can_sample_identifier(void) { return perf_probe_api(perf_probe_sample_identifier); @@ -195,3 +208,13 @@ bool perf_can_record_cgroup(void) { return perf_probe_api(perf_probe_cgroup); } + +bool perf_can_perf_clock_hw_clock(void) +{ + return perf_probe_api(perf_probe_hw_clock); +} + +bool perf_can_perf_clock_hw_clock_ns(void) +{ + return perf_probe_api(perf_probe_hw_clock_ns); +} diff --git a/tools/perf/util/perf_api_probe.h b/tools/perf/util/perf_api_probe.h index b104168efb15..5b30cbd260cf 100644 --- a/tools/perf/util/perf_api_probe.h +++ b/tools/perf/util/perf_api_probe.h @@ -13,5 +13,7 @@ bool perf_can_record_text_poke_events(void); bool perf_can_sample_identifier(void); bool perf_can_record_build_id(void); bool perf_can_record_cgroup(void); +bool perf_can_perf_clock_hw_clock(void); +bool perf_can_perf_clock_hw_clock_ns(void); #endif // __PERF_API_PROBE_H From patchwork Mon Mar 7 08:53:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A9F9C433F5 for ; Mon, 7 Mar 2022 08:53:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235443AbiCGIyv (ORCPT ); Mon, 7 Mar 2022 03:54:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236237AbiCGIyk (ORCPT ); Mon, 7 Mar 2022 03:54:40 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1068A1AF20; Mon, 7 Mar 2022 00:53:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643224; x=1678179224; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=igIfzl614SJVVpOc/yOTouOngTlxdEUS35ptrQqkkbo=; b=diMuQybr8uaLWWhTqCE+p6W3eg0IU95bszFbqFYTX8sRauKYTly6IHlQ kPXx+kpHIe26IAP3fOwHXG2hbX3rhV4IJUMvymEsedeECh2HiH1jukYMy bkycV0ZNQQsQD33rHQpSDesT222mNSk/VQK1RcKIlPGLfAgOxtVvk3xK3 fKHuJhHNNlJ4jSn2i/4WqatuQtLhIgYuNhn+yxnhL0qyhEJ1LK4uCZcs0 zcVfIgSfuiUjk8VVWmYgOPfdrrO6wxeCRJXpabJtF2uCoOMi4SRoZ4JE2 jQ3T7/JWwYrgY/xJrXRl3JPtwDAUdRtwfyt5zDHWZkJDDStTuNYCH+ULF Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771854" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771854" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033567" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:38 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 06/10] perf tools: Add new clock IDs to "perf time to TSC" test Date: Mon, 7 Mar 2022 10:53:08 +0200 Message-Id: <20220307085312.1814506-7-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The same "Convert perf time to TSC" test can be used with new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. Signed-off-by: Adrian Hunter --- tools/perf/tests/perf-time-to-tsc.c | 42 ++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c index d12d0ad81801..62840ec98cea 100644 --- a/tools/perf/tests/perf-time-to-tsc.c +++ b/tools/perf/tests/perf-time-to-tsc.c @@ -22,6 +22,8 @@ #include "tests.h" #include "pmu.h" #include "pmu-hybrid.h" +#include "clockid.h" +#include "perf_api_probe.h" /* * Except x86_64/i386 and Arm64, other archs don't support TSC in perf. Just @@ -47,15 +49,7 @@ } \ } -/** - * test__perf_time_to_tsc - test converting perf time to TSC. - * - * This function implements a test that checks that the conversion of perf time - * to and from TSC is consistent with the order of events. If the test passes - * %0 is returned, otherwise %-1 is returned. If TSC conversion is not - * supported then then the test passes but " (not supported)" is printed. - */ -static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int subtest __maybe_unused) +static int perf_time_to_tsc_test(bool use_clockid, s32 clockid) { struct record_opts opts = { .mmap_pages = UINT_MAX, @@ -104,6 +98,8 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su evsel->core.attr.comm = 1; evsel->core.attr.disabled = 1; evsel->core.attr.enable_on_exec = 0; + evsel->core.attr.use_clockid = use_clockid; + evsel->core.attr.clockid = clockid; /* * For hybrid "cycles:u", it creates two events. @@ -200,4 +196,32 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su return err; } +/** + * test__perf_time_to_tsc - test converting perf time to TSC. + * + * This function implements a test that checks that the conversion of perf time + * to and from TSC is consistent with the order of events. If the test passes + * %0 is returned, otherwise %-1 is returned. If TSC conversion is not + * supported then the test passes but " (not supported)" is printed. + */ +static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + int err; + + err = perf_time_to_tsc_test(false, 0); + + if (!err && perf_can_perf_clock_hw_clock()) { + pr_debug("Testing CLOCK_PERF_HW_CLOCK\n"); + err = perf_time_to_tsc_test(true, CLOCK_PERF_HW_CLOCK); + } + + if (!err && perf_can_perf_clock_hw_clock_ns()) { + pr_debug("Testing CLOCK_PERF_HW_CLOCK_NS\n"); + err = perf_time_to_tsc_test(true, CLOCK_PERF_HW_CLOCK_NS); + } + + return err; +} + DEFINE_SUITE("Convert perf time to TSC", perf_time_to_tsc); From patchwork Mon Mar 7 08:53:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B01C433EF for ; Mon, 7 Mar 2022 08:54:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236245AbiCGIy6 (ORCPT ); Mon, 7 Mar 2022 03:54:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236249AbiCGIyu (ORCPT ); Mon, 7 Mar 2022 03:54:50 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9BF917E3E; Mon, 7 Mar 2022 00:53:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643226; x=1678179226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tK8YcYd3WE7o/03bsGHBPo57y7a9U/7AOoyubu+SryY=; b=MxrprauOUedSCA40Mute6pgkDIUcz4urAo1ttjt3x4Q8ui+mLTwzNbWD d+4XETTJ8PNSsdhnQ0WKkJxJCJsQL5Pj3eRvEuIb+fmashYjgzOlVt4yt EcB8I0So3oMGtnb6+K61akK9OLVXNJqYiVZkEqpM6ADDq5NcKmRznhbU0 Hc+aQJuEkLHMQa/W34wmnpyHR6owfVC3Xc8mbWGnIE3uKuo3IfFNenljU YKbczfP0c/B7/LkyzWUqOTupaylcMDBvW5btzS4dNTktzT/CMTVn8+L3U fj3oIEUwwBc0GwwKrttOuXuIdNywoGj0l2CMIjy9mjlfPVek4DZMkngcJ w==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771860" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771860" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033595" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:42 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 07/10] perf tools: Add perf_read_tsc_conv_for_clockid() Date: Mon, 7 Mar 2022 10:53:09 +0200 Message-Id: <20220307085312.1814506-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a function to read TSC conversion information for a particular clock ID. It will be used in a subsequent patch. Signed-off-by: Adrian Hunter --- tools/perf/util/tsc.c | 56 +++++++++++++++++++++++++++++++++++++++++++ tools/perf/util/tsc.h | 1 + 2 files changed, 57 insertions(+) diff --git a/tools/perf/util/tsc.c b/tools/perf/util/tsc.c index f19791d46e99..92ae0e75c749 100644 --- a/tools/perf/util/tsc.c +++ b/tools/perf/util/tsc.c @@ -3,6 +3,8 @@ #include #include +#include + #include #include #include @@ -14,6 +16,9 @@ #include "synthetic-events.h" #include "debug.h" #include "tsc.h" +#include "cpumap.h" +#include "perf-sys.h" +#include /* page_size */ u64 perf_time_to_tsc(u64 ns, struct perf_tsc_conversion *tc) { @@ -71,6 +76,57 @@ int perf_read_tsc_conversion(const struct perf_event_mmap_page *pc, return 0; } +static int perf_read_tsc_conv_attr_cpu(struct perf_event_attr *attr, + struct perf_cpu cpu, + struct perf_tsc_conversion *tc) +{ + size_t len = 2 * page_size; + int fd, err = -EINVAL; + void *addr; + + fd = sys_perf_event_open(attr, 0, cpu.cpu, -1, 0); + if (fd == -1) + return -EINVAL; + + addr = mmap(NULL, len, PROT_READ, MAP_SHARED, fd, 0); + if (addr == MAP_FAILED) + goto out_close; + + err = perf_read_tsc_conversion(addr, tc); + + munmap(addr, len); +out_close: + close(fd); + return err; +} + +static struct perf_cpu find_a_cpu(void) +{ + struct perf_cpu_map *cpus; + struct perf_cpu cpu = { .cpu = 0 }; + + cpus = perf_cpu_map__new(NULL); + if (!cpus) + return cpu; + cpu = cpus->map[0]; + perf_cpu_map__put(cpus); + return cpu; +} + +int perf_read_tsc_conv_for_clockid(s32 clockid, struct perf_tsc_conversion *tc) +{ + struct perf_event_attr attr = { + .size = sizeof(attr), + .type = PERF_TYPE_SOFTWARE, + .config = PERF_COUNT_SW_DUMMY, + .exclude_kernel = 1, + .use_clockid = 1, + .clockid = clockid, + }; + + return perf_read_tsc_conv_attr_cpu(&attr, find_a_cpu(), tc); +} + int perf_event__synth_time_conv(const struct perf_event_mmap_page *pc, struct perf_tool *tool, perf_event__handler_t process, diff --git a/tools/perf/util/tsc.h b/tools/perf/util/tsc.h index 7d83a31732a7..ba9a52a9d70f 100644 --- a/tools/perf/util/tsc.h +++ b/tools/perf/util/tsc.h @@ -21,6 +21,7 @@ struct perf_event_mmap_page; int perf_read_tsc_conversion(const struct perf_event_mmap_page *pc, struct perf_tsc_conversion *tc); +int perf_read_tsc_conv_for_clockid(s32 clockid, struct perf_tsc_conversion *tc); u64 perf_time_to_tsc(u64 ns, struct perf_tsc_conversion *tc); u64 tsc_to_perf_time(u64 cyc, struct perf_tsc_conversion *tc); From patchwork Mon Mar 7 08:53:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B93C7C433FE for ; Mon, 7 Mar 2022 08:54:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236263AbiCGIy7 (ORCPT ); Mon, 7 Mar 2022 03:54:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236269AbiCGIyw (ORCPT ); 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07 Mar 2022 00:53:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033604" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:46 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 08/10] perf intel-pt: Add support for new clock IDs Date: Mon, 7 Mar 2022 10:53:10 +0200 Message-Id: <20220307085312.1814506-9-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add support for new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. Mainly this means also keeping TSC conversion information for CLOCK_PERF_HW_CLOCK_NS when CLOCK_PERF_HW_CLOCK is being used, so that conversions from nanoseconds can still be done when the perf event clock is TSC. Signed-off-by: Adrian Hunter --- tools/perf/arch/x86/util/intel-pt.c | 37 ++++++++++++++++++++++++++--- tools/perf/util/intel-pt.c | 24 +++++++++++++++---- tools/perf/util/intel-pt.h | 2 +- 3 files changed, 55 insertions(+), 8 deletions(-) diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index 8c31578d6f4a..5bc05b8dd7f0 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -31,6 +31,7 @@ #include "../../../util/tsc.h" #include // page_size #include "../../../util/intel-pt.h" +#include "../../../util/clockid.h" #define KiB(x) ((x) * 1024) #define MiB(x) ((x) * 1024 * 1024) @@ -290,6 +291,20 @@ static const char *intel_pt_find_filter(struct evlist *evlist, return NULL; } +static bool intel_pt_clockid(struct evlist *evlist, struct perf_pmu *intel_pt_pmu, s32 clockid) +{ + struct evsel *evsel; + + evlist__for_each_entry(evlist, evsel) { + if (evsel->core.attr.type == intel_pt_pmu->type && + evsel->core.attr.use_clockid && + evsel->core.attr.clockid == clockid) + return true; + } + + return false; +} + static size_t intel_pt_filter_bytes(const char *filter) { size_t len = filter ? strlen(filter) : 0; @@ -304,9 +319,11 @@ intel_pt_info_priv_size(struct auxtrace_record *itr, struct evlist *evlist) container_of(itr, struct intel_pt_recording, itr); const char *filter = intel_pt_find_filter(evlist, ptr->intel_pt_pmu); - ptr->priv_size = (INTEL_PT_AUXTRACE_PRIV_MAX * sizeof(u64)) + + ptr->priv_size = (INTEL_PT_AUXTRACE_PRIV_FIXED * sizeof(u64)) + intel_pt_filter_bytes(filter); ptr->priv_size += sizeof(u64); /* Cap Event Trace */ + ptr->priv_size += sizeof(u64); /* ns Time Shift */ + ptr->priv_size += sizeof(u64); /* ns Time Multiplier */ return ptr->priv_size; } @@ -414,6 +431,18 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, *info++ = event_trace; + if (intel_pt_clockid(session->evlist, ptr->intel_pt_pmu, CLOCK_PERF_HW_CLOCK)) { + struct perf_tsc_conversion ns_tc; + + if (perf_read_tsc_conv_for_clockid(CLOCK_PERF_HW_CLOCK_NS, &ns_tc)) + return -EINVAL; + *info++ = ns_tc.time_shift; + *info++ = ns_tc.time_mult; + } else { + *info++ = tc.time_shift; + *info++ = tc.time_mult; + } + return 0; } @@ -664,8 +693,10 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, return -EINVAL; } - if (opts->use_clockid) { - pr_err("Cannot use clockid (-k option) with " INTEL_PT_PMU_NAME "\n"); + if (opts->use_clockid && opts->clockid != CLOCK_PERF_HW_CLOCK_NS && + opts->clockid != CLOCK_PERF_HW_CLOCK) { + pr_err("Cannot use clockid (-k option) with " INTEL_PT_PMU_NAME + " except CLOCK_PERF_HW_CLOCK_NS and CLOCK_PERF_HW_CLOCK\n"); return -EINVAL; } diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index ec43d364d0de..677ad0774464 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -89,6 +89,8 @@ struct intel_pt { struct perf_tsc_conversion tc; bool cap_user_time_zero; + u16 ns_time_shift; + u32 ns_time_mult; struct itrace_synth_opts synth_opts; @@ -1100,10 +1102,10 @@ static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns) { u64 quot, rem; - quot = ns / pt->tc.time_mult; - rem = ns % pt->tc.time_mult; - return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) / - pt->tc.time_mult; + quot = ns / pt->ns_time_mult; + rem = ns % pt->ns_time_mult; + return (quot << pt->ns_time_shift) + (rem << pt->ns_time_shift) / + pt->ns_time_mult; } static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt) @@ -3987,6 +3989,20 @@ int intel_pt_process_auxtrace_info(union perf_event *event, pt->cap_event_trace); } + if ((void *)info < info_end) { + pt->ns_time_shift = *info++; + pt->ns_time_mult = *info++; + if (dump_trace) { + fprintf(stdout, " ns Time Shift %d\n", pt->ns_time_shift); + fprintf(stdout, " ns Time Multiplier %d\n", pt->ns_time_mult); + } + } else { + pt->ns_time_shift = pt->tc.time_shift; + pt->ns_time_mult = pt->tc.time_mult; + } + if (!pt->ns_time_mult) + pt->ns_time_mult = 1; + pt->timeless_decoding = intel_pt_timeless_decoding(pt); if (pt->timeless_decoding && !pt->tc.time_mult) pt->tc.time_mult = 1; diff --git a/tools/perf/util/intel-pt.h b/tools/perf/util/intel-pt.h index c7d6068e3a6b..a2c4474641c0 100644 --- a/tools/perf/util/intel-pt.h +++ b/tools/perf/util/intel-pt.h @@ -27,7 +27,7 @@ enum { INTEL_PT_CYC_BIT, INTEL_PT_MAX_NONTURBO_RATIO, INTEL_PT_FILTER_STR_LEN, - INTEL_PT_AUXTRACE_PRIV_MAX, + INTEL_PT_AUXTRACE_PRIV_FIXED, }; struct auxtrace_record; From patchwork Mon Mar 7 08:53:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFF50C433F5 for ; Mon, 7 Mar 2022 08:54:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236295AbiCGIzQ (ORCPT ); Mon, 7 Mar 2022 03:55:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236274AbiCGIzF (ORCPT ); Mon, 7 Mar 2022 03:55:05 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44F131AF20; Mon, 7 Mar 2022 00:54:03 -0800 (PST) DKIM-Signature: v=1; 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07 Mar 2022 00:53:51 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 09/10] perf intel-pt: Add config variables for timing parameters Date: Mon, 7 Mar 2022 10:53:11 +0200 Message-Id: <20220307085312.1814506-10-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Parameters needed to correctly interpret timing packets might be missing in a virtual machine because the CPUID leaf or MSR is not supported by the hypervisor / KVM. Add perf config variables to overcome that for max_nonturbo_ratio (missing from MSR_PLATFORM_INFO) and tsc_art_ratio (missing from CPUID leaf 0x15), which were seen to be missing from QEMU / KVM. Signed-off-by: Adrian Hunter --- tools/perf/Documentation/perf-config.txt | 18 ++++++++ tools/perf/arch/x86/util/intel-pt.c | 52 +++++++++++++++++++++++- tools/perf/util/intel-pt.c | 6 +++ tools/perf/util/intel-pt.h | 5 +++ 4 files changed, 79 insertions(+), 2 deletions(-) diff --git a/tools/perf/Documentation/perf-config.txt b/tools/perf/Documentation/perf-config.txt index 0420e71698ee..933fc454f988 100644 --- a/tools/perf/Documentation/perf-config.txt +++ b/tools/perf/Documentation/perf-config.txt @@ -709,7 +709,11 @@ stat.*:: intel-pt.*:: + Variables that affect Intel PT. + intel-pt.cache-divisor:: + If set, the decoder instruction cache size is based on DSO size + divided by this number. Default is 64. intel-pt.mispred-all:: If set, Intel PT decoder will set the mispred flag on all @@ -721,6 +725,20 @@ intel-pt.*:: the maximum is exceeded there will be a "Never-ending loop" error. The default is 100000. + intel-pt.max_nonturbo_ratio:: + The kernel provides /sys/bus/event_source/devices/intel_pt/max_nonturbo_ratio + which can be zero in a virtual machine. The decoder needs this + information to correctly interpret timing packets, so the value + can be provided by this variable in that case. Note in the absence + of VMCS TSC Scaling, this is probably the same as the host value. + + intel-pt.tsc_art_ratio:: + The kernel provides /sys/bus/event_source/devices/intel_pt/tsc_art_ratio + which can be 0:0 in a virtual machine. The decoder needs this + information to correctly interpret timing packets, so the value + can be provided by this variable in that case. Note in the absence + of VMCS TSC Scaling, this is probably the same as the host value. + auxtrace.*:: auxtrace.dumpdir:: diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index 5bc05b8dd7f0..16951622ddbf 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -24,6 +24,7 @@ #include "../../../util/parse-events.h" #include "../../../util/pmu.h" #include "../../../util/debug.h" +#include "../../../util/config.h" #include "../../../util/auxtrace.h" #include "../../../util/perf_api_probe.h" #include "../../../util/record.h" @@ -328,15 +329,60 @@ intel_pt_info_priv_size(struct auxtrace_record *itr, struct evlist *evlist) return ptr->priv_size; } +struct tsc_art_ratio { + u32 *n; + u32 *d; +}; + +static int intel_pt_tsc_art_ratio(const char *var, const char *value, void *data) +{ + if (!strcmp(var, "intel-pt.tsc_art_ratio")) { + struct tsc_art_ratio *r = data; + + if (sscanf(value, "%u:%u", r->n, r->d) != 2) + return -EINVAL; + } + return 0; +} + +void intel_pt_tsc_ctc_ratio_from_config(u32 *n, u32 *d) +{ + struct tsc_art_ratio data = { .n = n, .d = d }; + + *n = 0; + *d = 0; + perf_config(intel_pt_tsc_art_ratio, &data); +} + static void intel_pt_tsc_ctc_ratio(u32 *n, u32 *d) { unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; __get_cpuid(0x15, &eax, &ebx, &ecx, &edx); + if (!eax || !ebx) { + intel_pt_tsc_ctc_ratio_from_config(n, d); + return; + } *n = ebx; *d = eax; } +static int intel_pt_max_nonturbo_ratio(const char *var, const char *value, void *data) +{ + if (!strcmp(var, "intel-pt.max_nonturbo_ratio")) { + unsigned int *max_nonturbo_ratio = data; + + if (sscanf(value, "%u", max_nonturbo_ratio) != 1) + return -EINVAL; + } + return 0; +} + +void intel_pt_max_nonturbo_ratio_from_config(unsigned int *max_non_turbo_ratio) +{ + perf_config(intel_pt_max_nonturbo_ratio, max_non_turbo_ratio); +} + static int intel_pt_info_fill(struct auxtrace_record *itr, struct perf_session *session, struct perf_record_auxtrace_info *auxtrace_info, @@ -350,7 +396,7 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, bool cap_user_time_zero = false, per_cpu_mmaps; u64 tsc_bit, mtc_bit, mtc_freq_bits, cyc_bit, noretcomp_bit; u32 tsc_ctc_ratio_n, tsc_ctc_ratio_d; - unsigned long max_non_turbo_ratio; + unsigned int max_non_turbo_ratio; size_t filter_str_len; const char *filter; int event_trace; @@ -374,8 +420,10 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, intel_pt_tsc_ctc_ratio(&tsc_ctc_ratio_n, &tsc_ctc_ratio_d); if (perf_pmu__scan_file(intel_pt_pmu, "max_nonturbo_ratio", - "%lu", &max_non_turbo_ratio) != 1) + "%u", &max_non_turbo_ratio) != 1) max_non_turbo_ratio = 0; + if (!max_non_turbo_ratio) + intel_pt_max_nonturbo_ratio_from_config(&max_non_turbo_ratio); if (perf_pmu__scan_file(intel_pt_pmu, "caps/event_trace", "%d", &event_trace) != 1) event_trace = 0; diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index 677ad0774464..4ed14c920e4e 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -3934,6 +3934,9 @@ int intel_pt_process_auxtrace_info(union perf_event *event, INTEL_PT_CYC_BIT); } + if (!pt->tsc_ctc_ratio_n || !pt->tsc_ctc_ratio_d) + intel_pt_tsc_ctc_ratio_from_config(&pt->tsc_ctc_ratio_n, &pt->tsc_ctc_ratio_d); + if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) { pt->max_non_turbo_ratio = auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO]; @@ -3942,6 +3945,9 @@ int intel_pt_process_auxtrace_info(union perf_event *event, INTEL_PT_MAX_NONTURBO_RATIO); } + if (!pt->max_non_turbo_ratio) + intel_pt_max_nonturbo_ratio_from_config(&pt->max_non_turbo_ratio); + info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1; info_end = (void *)auxtrace_info + auxtrace_info->header.size; diff --git a/tools/perf/util/intel-pt.h b/tools/perf/util/intel-pt.h index a2c4474641c0..99ac73f4a648 100644 --- a/tools/perf/util/intel-pt.h +++ b/tools/perf/util/intel-pt.h @@ -7,6 +7,8 @@ #ifndef INCLUDE__PERF_INTEL_PT_H__ #define INCLUDE__PERF_INTEL_PT_H__ +#include + #define INTEL_PT_PMU_NAME "intel_pt" enum { @@ -44,4 +46,7 @@ int intel_pt_process_auxtrace_info(union perf_event *event, struct perf_event_attr *intel_pt_pmu_default_config(struct perf_pmu *pmu); +void intel_pt_tsc_ctc_ratio_from_config(u32 *n, u32 *d); +void intel_pt_max_nonturbo_ratio_from_config(unsigned int *max_non_turbo_ratio); + #endif From patchwork Mon Mar 7 08:53:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00A94C433F5 for ; Mon, 7 Mar 2022 08:54:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233881AbiCGIzN (ORCPT ); Mon, 7 Mar 2022 03:55:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236224AbiCGIzE (ORCPT ); Mon, 7 Mar 2022 03:55:04 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B34581BE9F; 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d="scan'208";a="537033649" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:55 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 10/10] perf intel-pt: Add documentation for new clock IDs Date: Mon, 7 Mar 2022 10:53:12 +0200 Message-Id: <20220307085312.1814506-11-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add brief documentation for new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS, as well as new config variables intel-pt.max_nonturbo_ratio and intel-pt.tsc_art_ratio. Signed-off-by: Adrian Hunter --- tools/perf/Documentation/perf-intel-pt.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/tools/perf/Documentation/perf-intel-pt.txt b/tools/perf/Documentation/perf-intel-pt.txt index ff58bd4c381b..383126d05577 100644 --- a/tools/perf/Documentation/perf-intel-pt.txt +++ b/tools/perf/Documentation/perf-intel-pt.txt @@ -509,6 +509,29 @@ notnt Disable TNT packets. Without TNT packets, it is not possible to walk "0" otherwise. +perf event clock +~~~~~~~~~~~~~~~~ + +Newer kernel and tools support 2 special clocks: CLOCK_PERF_HW_CLOCK which is +TSC and CLOCK_PERF_HW_CLOCK_NS which is TSC converted to nanoseconds. +CLOCK_PERF_HW_CLOCK_NS is the same as the default perf event clock, but it is +not subject to paravirtualization, so it still works with Intel PT in a VM +guest. Note however, TSC may not be being fully virtualized, so the results +may be unexpected. + + --clockid CLOCK_PERF_HW_CLOCK_NS + +To use TSC instead of nanoseconds, use the option: + + --clockid CLOCK_PERF_HW_CLOCK + +Beware forgetting that the time stamp of events will show TSC ticks +(divided by 1,000,000,000) not seconds. + +Other clocks are not supported for use with Intel PT because they cannot be +converted to/from TSC. + + AUX area sampling option ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1398,6 +1421,28 @@ There were none. :17006 17006 [001] 11500.262869216: ffffffff8220116e error_entry+0xe ([guest.kernel.kallsyms]) pushq %rax +Tracing within a Virtual Machine +-------------------------------- + +When supported, using Intel PT within a virtual machine does not support TSC +because the perf event clock is subject to paravirtualization. That is +overcome by the new CLOCK_PERF_HW_CLOCK_NS clock - refer 'perf event clock' +above. In addition, in a VM, the following might be zero: + + /sys/bus/event_source/devices/intel_pt/max_nonturbo_ratio + /sys/bus/event_source/devices/intel_pt/tsc_art_ratio + +The decoder needs this information to correctly interpret timing packets, +so the values can be provided by config variables in that case. Note in +the absence of VMCS TSC Scaling, this is probably the same as the host values. +The config variables are: + + intel-pt.max_nonturbo_ratio + intel-pt.tsc_art_ratio + +For more information about perf config variables, refer linkperf:perf-config[1] + + Event Trace -----------