From patchwork Tue Mar 8 10:33:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12773462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FF3AC433F5 for ; Tue, 8 Mar 2022 10:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345893AbiCHKfZ (ORCPT ); Tue, 8 Mar 2022 05:35:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245490AbiCHKfX (ORCPT ); Tue, 8 Mar 2022 05:35:23 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A175B42483; Tue, 8 Mar 2022 02:34:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646735667; x=1678271667; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=FlcudMl4wt40GaXEm95OBt7epfsxqnaQwFMkE/EImQI=; b=TIZXuLaR06DMqARdlDW2ZbWEzw2MOIG84x2dPYyWYGtopQAuwnU5zd30 hE//cYiVlhfDUbD4qB/w5QsilMs+iYibOcCEWoCQFeC8X2XW4mqj3M+Hk 1yJTQEicU81xMkLcKL7RtczFZc/EXOUpjBJVXCM/eFf51VB6BJ+rtfR0m 0X7/1+RK5IcY3CHqwY04/4wAimLfw/eIzUuHZqulK0wrm3BLeeoSQNRex GhVrEnyRrbE2MN8Ap4vPh5QGopF/S/mcBgqtHcYl4kKtjrGZlB/KH0P8M dVsiP4WTqdDXEpyMMYlRXrWLH52TA+Yb03sjjSNFPIseMKEEymsiwJWHx g==; X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="234605596" X-IronPort-AV: E=Sophos;i="5.90,164,1643702400"; d="scan'208";a="234605596" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 02:34:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,164,1643702400"; d="scan'208";a="643612232" Received: from srikandan-ilbpg12.png.intel.com ([10.88.229.69]) by orsmga004.jf.intel.com with ESMTP; 08 Mar 2022 02:34:23 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v4 1/3] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC Date: Tue, 8 Mar 2022 18:33:29 +0800 Message-Id: <20220308103331.4116-2-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308103331.4116-1-nandhini.srikandan@intel.com> References: <20220308103331.4116-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add documentation for SPI controller in Intel Thunder Bay SoC. Signed-off-by: Nandhini Srikandan Acked-by: Rob Herring --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index d7e08b03e204..5ecd996ebf33 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -61,6 +61,8 @@ properties: - const: snps,dw-apb-ssi - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi + - description: Intel Thunder Bay SPI Controller + const: intel,thunderbay-ssi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller From patchwork Tue Mar 8 10:33:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12773463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53D27C433EF for ; Tue, 8 Mar 2022 10:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245315AbiCHKf3 (ORCPT ); Tue, 8 Mar 2022 05:35:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345904AbiCHKf2 (ORCPT ); Tue, 8 Mar 2022 05:35:28 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25D8842483; Tue, 8 Mar 2022 02:34:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646735672; x=1678271672; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=JsCodzOmII512dLTHpv/v1yXZod+ZMLo+DfZJQcuPHc=; b=VdwXGtsQHJSNlKSeemaW/nE8TDaSpbAjqG9/WqTAvjiz5ibym3QjGL+r cMKmf/UpaIWQaqyQQwToclb0HJBRKJGsTuoOkAjLilCfQDRpJ57FuW8ks Oxyh52dCIq7eZMqD+YoYFakxM2aAxFRZwge+Va7zfCWDZzJq5xbkKoPTX aSf4InJdMZS+MUUTJvMZJqeMJOfXvl34ezishWn9ECYjiTvRDXk46izlJ mXoFN1pES+xyyninsfhrloRhsHTXQwQpGFBrZ+LWEh5WiCiDUHHD4XqOK YII8VjLcSeghQDzZsZdQm6GOFNs0FdpWCyS4gbkn3KWLbDk42+bcDiNMa A==; X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="234605611" X-IronPort-AV: E=Sophos;i="5.90,164,1643702400"; d="scan'208";a="234605611" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 02:34:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,164,1643702400"; d="scan'208";a="643612241" Received: from srikandan-ilbpg12.png.intel.com ([10.88.229.69]) by orsmga004.jf.intel.com with ESMTP; 08 Mar 2022 02:34:28 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v4 2/3] spi: dw: Add support for Intel Thunder Bay SPI controller Date: Tue, 8 Mar 2022 18:33:30 +0800 Message-Id: <20220308103331.4116-3-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308103331.4116-1-nandhini.srikandan@intel.com> References: <20220308103331.4116-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by: Nandhini Srikandan --- drivers/spi/spi-dw-mmio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 5101c4c6017b..26c40ea6dd12 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev, return 0; } -static int dw_spi_keembay_init(struct platform_device *pdev, - struct dw_spi_mmio *dwsmmio) +static int dw_spi_intel_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) { dwsmmio->dws.ip = DW_HSSI_ID; - dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST; return 0; } @@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init}, { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init}, - { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, + { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init}, + { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, { /* end of table */} From patchwork Tue Mar 8 10:33:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 12773464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B64FC433F5 for ; Tue, 8 Mar 2022 10:34:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345904AbiCHKfi (ORCPT ); Tue, 8 Mar 2022 05:35:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345918AbiCHKfh (ORCPT ); Tue, 8 Mar 2022 05:35:37 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8A004348E; Tue, 8 Mar 2022 02:34:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646735675; x=1678271675; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=818ZiUqupFKx30M4QQyr2CZvlTpag7QHU9v/hFaDbMM=; b=O1JAu2sgxKODjeBJSgX0ggf7LowM4PUNMnn25Bn5o+hVMmPBqTsvx7sV tB9gUwDODtaQBW5cDbfue9mFm1Fbd/9c0g4NKcGEQcFdvJaDXndDun1Xw Tb5+pZJJN1wxNifPLHJOi9Z8bdQGIKRD936Ed2J7PjAEJXwhUOEBcILAi UZ/N99rlG6QxDyhJpLydMdmihLMstshjBWR2M7ELsDTwAvCrSv1fBbHOE A8D3cU6M7autkVg2Os59+C55QTSGhmD26ILXyJ551g2v3Exd9Tk/wnVb4 Jg8KDowC/FLJISQodi+jwSZgwnWVv5Og5TJcxn7Ci7XCPJpmi15bSx+F3 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="234605624" X-IronPort-AV: E=Sophos;i="5.90,164,1643702400"; d="scan'208";a="234605624" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 02:34:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,164,1643702400"; d="scan'208";a="643612251" Received: from srikandan-ilbpg12.png.intel.com ([10.88.229.69]) by orsmga004.jf.intel.com with ESMTP; 08 Mar 2022 02:34:32 -0800 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v4 3/3] spi: dw: Add support for master mode selection for DWC SSI controller Date: Tue, 8 Mar 2022 18:33:31 +0800 Message-Id: <20220308103331.4116-4-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308103331.4116-1-nandhini.srikandan@intel.com> References: <20220308103331.4116-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add support to select the controller mode as master mode by setting Bit 31 of CTRLR0 register. This feature is supported for controller versions above v1.02. Signed-off-by: Nandhini Srikandan --- drivers/spi/spi-dw-core.c | 4 ++-- drivers/spi/spi-dw.h | 7 +++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index ecea471ff42c..68bfdf2c4dc7 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -307,8 +307,8 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) if (spi->mode & SPI_LOOP) cr0 |= DW_HSSI_CTRLR0_SRL; - if (dws->caps & DW_SPI_CAP_KEEMBAY_MST) - cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST; + /* CTRLR0[31] MST */ + cr0 |= DW_HSSI_CTRLR0_MST; } return cr0; diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index d5ee5130601e..2583b7314c41 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -23,7 +23,7 @@ ((_dws)->ip == DW_ ## _ip ## _ID) #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \ - (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ver) + (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver) #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==) @@ -31,8 +31,7 @@ /* DW SPI controller capabilities */ #define DW_SPI_CAP_CS_OVERRIDE BIT(0) -#define DW_SPI_CAP_KEEMBAY_MST BIT(1) -#define DW_SPI_CAP_DFS32 BIT(2) +#define DW_SPI_CAP_DFS32 BIT(1) /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ #define DW_SPI_CTRLR0 0x00 @@ -100,7 +99,7 @@ * 0: SSI is slave * 1: SSI is master */ -#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31) +#define DW_HSSI_CTRLR0_MST BIT(31) /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0)