From patchwork Tue Mar 8 20:49:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11609C433EF for ; Tue, 8 Mar 2022 20:51:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kIDUodxOgwc6A237sez2GZngUBObFo9bqeJCwwm0XE0=; b=P3uxHcKxZE6BKB pRwsgVZ7LT1jOtyZs4mGxNE8T6Iq8f/tpg4RKpH2aGiO+2yTM80jIP1ru9EPa7C1womiCXMJ4qmfY 9/l/kyldt6oyJzm+TCYxMHU0WCpXlK/6Fl4iPN/Sv/QdBadWCf/IGgyV8Aw+IPgN9fTRfPQ7WDGEW eYF8F9o40pCMGHk3oUXkBsxx6q8q/Izra9LJd5X7WDqTDVtQP5iErZCZN39BZU6zDh7rNbiM3HWCy GLEscadrh4XwNgenB7Zx1r0KOGIA+BRXEsmg2UshGef9dEcVIqbmkoJfpx2Ku+/8eFhkG2VITgadf n3565B6rtKgdYxMLFizQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgmn-006BxN-1P; Tue, 08 Mar 2022 20:50:25 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRgmV-006BnO-Pq for linux-arm-kernel@lists.infradead.org; Tue, 08 Mar 2022 20:50:09 +0000 Received: by mail-wm1-x336.google.com with SMTP id c192so189508wma.4 for ; Tue, 08 Mar 2022 12:50:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tkKeTpGeVj1TsD7lgtJxbN6dJOpPm7ZIDu/PMW+d2/s=; b=R3oKdAIGROO1nl4fOdOTEC6Y6ElvV4vaUf0h9EF5Q1a6tdeoQKHA8CkWpHSUNVsgEs ZHznJ5jZZ8GKxjZ2ELfs3+r37otMN+c95llQLujM9jvz2mWWNN2pYDq0a2pE34b/CxXU 6rJFepurHMqRcBEnqRRx4L7DMjnMYHb+gxHaG91CjEneKyPl0cfaHM8gXCa5B9ZK7ICh egqDwxIBpkTXEdtb1JGKu9HQ/Y3zMikdRGOraiJHtf7PgkdeHjcOZI+qpwCGMzN1yDcF 5rupO50giyNJukaFq0ErZUZsGL/9E/7x2tcURZfwEppmaS22VfYyL1tYw8tsPhurAzxB auiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tkKeTpGeVj1TsD7lgtJxbN6dJOpPm7ZIDu/PMW+d2/s=; b=pYPaUrNfIANXwH/CoT+FgHmRUBi2vS6k6rFcwF3jeYB1/hVS1l7xTeLBQ1ZrdZGFrk CE4Y5H8eefX56vWsg0VlGDFudV4zdEnu1gt9Jjryk9AQjFEcvufjrvvH5JxoCHadiznh yOz5pcYrdQh6zvbt+zCyL3SGJQiW5rnS23IYnFUyMvHywVZWhDYZsg7mOd90fxvXRVM2 X/pnXSihWBsZOX0Ep+vnAEY1KN3ZIkAIQCnCK02utjpW7OErMZdOsAnxd6kKpZtPWKv1 kZVG1bzAyHPtzneNvY3F+V//G5Tq/GivEVWbq1K6XNstcYQO2YwDQnMiCRVw6zHYvc0p G0kg== X-Gm-Message-State: AOAM533lRUUC8yNdH+Pm6oOKjCRlsmC7QSnQiN9x+jYbhE/NK7L7IJEJ vCCkuv3GRUsG48vKqNLuNFp+qw== X-Google-Smtp-Source: ABdhPJw8VChYAWgMdUZF0BnRoSIIHmH8w2IlzDcL5mxMB0asBtDYymYVai84TCVfRZXFdq+sUBYuGQ== X-Received: by 2002:a1c:4b0e:0:b0:389:bf16:d8fb with SMTP id y14-20020a1c4b0e000000b00389bf16d8fbmr5094074wma.103.1646772605960; Tue, 08 Mar 2022 12:50:05 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:05 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 01/10] coresight: trace-id: Add API to dynamically assign trace ID values Date: Tue, 8 Mar 2022 20:49:51 +0000 Message-Id: <20220308205000.27646-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125007_880790_47CDDDA3 X-CRM114-Status: GOOD ( 32.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The existing mechanism to assign Trace ID values to sources is limited and does not scale for larger multicore / multi trace source systems. The API introduces functions that reserve IDs based on availabilty represented by a coresight_trace_id_map structure. This records the used and free IDs in a bitmap. CPU bound sources such as ETMs use the coresight_trace_id_get_cpu_id / coresight_trace_id_put_cpu_id pair of functions. The API will record the ID associated with the CPU. This ensures that the same ID will be re-used while perf events are active on the CPU. The put_cpu_id function will pend release of the ID until all perf cs_etm sessions are complete. Non-cpu sources, such as the STM can use coresight_trace_id_get_system_id / coresight_trace_id_put_system_id. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/Makefile | 2 +- .../hwtracing/coresight/coresight-trace-id.c | 222 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 69 ++++++ 3 files changed, 292 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..329a0c704b87 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ coresight-cfg-preload.o coresight-cfg-afdo.o \ - coresight-syscfg-configfs.o + coresight-syscfg-configfs.o coresight-trace-id.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c new file mode 100644 index 000000000000..ce6c7d7b55d6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Linaro Limited, All rights reserved. + * Author: Mike Leach + */ +#include +#include +#include + +#include "coresight-trace-id.h" + +/* need to keep data on ids & association with cpus. */ +struct cpu_id_info { + int id; + bool pend_rel; +}; + +/* maintain a record of the current mapping of cpu IDs */ +static DEFINE_PER_CPU(struct cpu_id_info, cpu_ids); + +/* a list of currently used id_maps */ +static LIST_HEAD(id_map_list); + +/* perf session active flag */ +static int perf_cs_etm_session_active; + +/* lock to protect id_map list and cpu data */ +static DEFINE_SPINLOCK(id_map_lock); + +/* ID 0 is reserved */ +#define CORESIGHT_TRACE_ID_RES_0 0 + +/* ID 0x70 onwards are reserved */ +#define CORESIGHT_TRACE_ID_RES_RANGE_LO 0x70 +#define CORESIGHT_TRACE_ID_RES_RANGE_HI 0x7F + +#define IS_VALID_ID(id) \ + ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_RANGE_LO)) + +static void coresight_trace_id_set_inuse(int id, struct coresight_trace_id_map *id_map) +{ + if (IS_VALID_ID(id)) + set_bit(id, id_map->avail_ids); +} + +static void coresight_trace_id_clear_inuse(int id, struct coresight_trace_id_map *id_map) +{ + if (IS_VALID_ID(id)) + clear_bit(id, id_map->avail_ids); +} + +static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_map *id_map) +{ + if (IS_VALID_ID(id)) + set_bit(id, id_map->pend_rel_ids); +} + +static void coresight_trace_id_clear_pend_rel(int id, struct coresight_trace_id_map *id_map) +{ + if (IS_VALID_ID(id)) + clear_bit(id, id_map->pend_rel_ids); +} + +static int coresight_trace_id_find_new_id(struct coresight_trace_id_map *id_map) +{ + int id; + + id = find_first_zero_bit(id_map->avail_ids, CORESIGHT_TRACE_IDS_MAX); + if (id >= CORESIGHT_TRACE_IDS_MAX) + id = -EINVAL; + return id; +} + +/* release all pending IDs for all current maps & clear CPU associations */ +static void coresight_trace_id_release_all_pending(void) +{ + struct coresight_trace_id_map *id_map; + int cpu, bit; + + list_for_each_entry(id_map, &id_map_list, node) { + for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_IDS_MAX) { + clear_bit(bit, id_map->avail_ids); + clear_bit(bit, id_map->pend_rel_ids); + } + } + + for_each_possible_cpu(cpu) { + if (per_cpu(cpu_ids, cpu).pend_rel) { + per_cpu(cpu_ids, cpu).pend_rel = false; + per_cpu(cpu_ids, cpu).id = 0; + } + } +} + +int coresight_trace_id_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + id = per_cpu(cpu_ids, cpu).id; + if (!id) { + id = coresight_trace_id_find_new_id(id_map); + if (id < 0) + goto get_cpu_id_out; + } + + per_cpu(cpu_ids, cpu).id = id; + per_cpu(cpu_ids, cpu).pend_rel = false; + coresight_trace_id_set_inuse(id, id_map); + coresight_trace_id_clear_pend_rel(id, id_map); + +get_cpu_id_out: + spin_unlock_irqrestore(&id_map_lock, flags); + return id; +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id); + +void coresight_trace_id_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + id = per_cpu(cpu_ids, cpu).id; + if (!id) + goto put_cpu_id_out; + + if (perf_cs_etm_session_active) { + /* set release at pending if perf still active */ + coresight_trace_id_set_pend_rel(id, id_map); + per_cpu(cpu_ids, cpu).pend_rel = true; + } else { + /* otherwise clear id */ + coresight_trace_id_clear_inuse(id, id_map); + per_cpu(cpu_ids, cpu).id = 0; + } + + put_cpu_id_out: + spin_unlock_irqrestore(&id_map_lock, flags); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id); + +int coresight_trace_id_get_system_id(struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + id = coresight_trace_id_find_new_id(id_map); + if (id > 0) + coresight_trace_id_set_inuse(id, id_map); + spin_unlock_irqrestore(&id_map_lock, flags); + + return id; +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id); + +void coresight_trace_id_put_system_id(struct coresight_trace_id_map *id_map, int id) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + coresight_trace_id_clear_inuse(id, id_map); + spin_unlock_irqrestore(&id_map_lock, flags); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); + +void coresight_trace_id_perf_start(void) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + perf_cs_etm_session_active++; + spin_unlock_irqrestore(&id_map_lock, flags); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); + +void coresight_trace_id_perf_stop(void) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + perf_cs_etm_session_active--; + if (!perf_cs_etm_session_active) + coresight_trace_id_release_all_pending(); + spin_unlock_irqrestore(&id_map_lock, flags); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop); + +void coresight_trace_id_init_id_map(struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int bit; + + /* set all reserved bits as in-use */ + set_bit(CORESIGHT_TRACE_ID_RES_0, id_map->avail_ids); + for (bit = CORESIGHT_TRACE_ID_RES_RANGE_LO; + bit <= CORESIGHT_TRACE_ID_RES_RANGE_HI; bit++) + set_bit(bit, id_map->avail_ids); + + spin_lock_irqsave(&id_map_lock, flags); + + /* add id_map to the list */ + list_add(&id_map->node, &id_map_list); + + spin_unlock_irqrestore(&id_map_lock, flags); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_init_id_map); + +void coresight_trace_id_release_id_map(struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + + /* remove id_map from list */ + list_del(&id_map->node); + + spin_unlock_irqrestore(&id_map_lock, flags); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_release_id_map); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h new file mode 100644 index 000000000000..01db2441cee6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(C) 2022 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#ifndef _CORESIGHT_TRACE_ID_H +#define _CORESIGHT_TRACE_ID_H + +/* + * Coresight trace ID allocation API + * + * With multi cpu systems, and more additional trace sources a scalable + * trace ID reservation system is required. + * + * The system will allocate Ids on a demand basis, and allow them to be + * released when done. + * + * In order to ensure that a consistent cpu / ID matching is maintained + * throughout a perf cs_etm event session - a session in progress flag will + * be maintained, and released IDs not cleared until the perf session is + * complete. This allows the same CPU to be re-allocated its prior ID. + * + * + * Trace ID maps will be created and initialised to prevent architecturally + * reserved IDs from being allocated. + * + * API permits multiple maps to be maintained - for large systems where + * different sets of cpus trace into different independent sinks. + */ + +#include +#include + + +/* architecturally we have 128 IDs some of which are reserved */ +#define CORESIGHT_TRACE_IDS_MAX 128 + +/** + * Trace ID map. + * + * @avail_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. + * Initialised so that the reserved IDs are permanently marked as in use. + * @pend_rel_ids: CPU IDs that have been released by the trace source but not yet marked + * as available, to allow re-allocation to the same CPU during a perf session. + * @node: List entry to add to list of managed trace id maps. + */ +struct coresight_trace_id_map { + DECLARE_BITMAP(avail_ids, CORESIGHT_TRACE_IDS_MAX); + DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); + struct list_head node; +}; + +/* Allocate and release IDs */ +int coresight_trace_id_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map); +int coresight_trace_id_get_system_id(struct coresight_trace_id_map *id_map); +void coresight_trace_id_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map); +void coresight_trace_id_put_system_id(struct coresight_trace_id_map *id_map, int id); + +/* initialise ID map - block reserved IDs, add to list of ID maps */ +void coresight_trace_id_init_id_map(struct coresight_trace_id_map *id_map); +/* remove ID maps from list of maps */ +void coresight_trace_id_release_id_map(struct coresight_trace_id_map *id_map); + +/* notifiers for perf session start and stop */ +void coresight_trace_id_perf_start(void); +void coresight_trace_id_perf_stop(void); + +#endif /* _CORESIGHT_TRACE_ID_H */ From patchwork Tue Mar 8 20:49:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7D66C433F5 for ; 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Tue, 08 Mar 2022 12:50:06 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 02/10] coresight: trace-id: Set up source trace ID map for system Date: Tue, 8 Mar 2022 20:49:52 +0000 Message-Id: <20220308205000.27646-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125008_537178_877D30CD X-CRM114-Status: GOOD ( 21.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds in a CoreSight trace ID map for the entire system. This will be used by all source drivers to be allocated their trace IDs. The checks for sources to have unique IDs has been removed - this is now guaranteed by the ID allocation mechanisms, and inappropriate where multiple ID maps are in use in larger systems Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-core.c | 64 ++++++-------------- drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 20 insertions(+), 45 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index af00dca8d1ac..bbf415c252f9 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); @@ -50,6 +51,19 @@ static DEFINE_PER_CPU(struct list_head *, tracer_path); */ static struct list_head *stm_path; +/* + * Set up a global trace ID map. + * We may need a per sink ID map in future for larger / multi sink systems. + */ +static struct coresight_trace_id_map trace_id_map; + +/* Allow drivers to reference ID map when getting trace IDs */ +struct coresight_trace_id_map *coresight_get_trace_id_map(void) +{ + return &trace_id_map; +} +EXPORT_SYMBOL_GPL(coresight_get_trace_id_map); + /* * When losing synchronisation a new barrier packet needs to be inserted at the * beginning of the data collected in a buffer. That way the decoder knows that @@ -84,45 +98,6 @@ struct coresight_device *coresight_get_percpu_sink(int cpu) } EXPORT_SYMBOL_GPL(coresight_get_percpu_sink); -static int coresight_id_match(struct device *dev, void *data) -{ - int trace_id, i_trace_id; - struct coresight_device *csdev, *i_csdev; - - csdev = data; - i_csdev = to_coresight_device(dev); - - /* - * No need to care about oneself and components that are not - * sources or not enabled - */ - if (i_csdev == csdev || !i_csdev->enable || - i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE) - return 0; - - /* Get the source ID for both components */ - trace_id = source_ops(csdev)->trace_id(csdev); - i_trace_id = source_ops(i_csdev)->trace_id(i_csdev); - - /* All you need is one */ - if (trace_id == i_trace_id) - return 1; - - return 0; -} - -static int coresight_source_is_unique(struct coresight_device *csdev) -{ - int trace_id = source_ops(csdev)->trace_id(csdev); - - /* this shouldn't happen */ - if (trace_id < 0) - return 0; - - return !bus_for_each_dev(&coresight_bustype, NULL, - csdev, coresight_id_match); -} - static int coresight_find_link_inport(struct coresight_device *csdev, struct coresight_device *parent) { @@ -431,12 +406,6 @@ static int coresight_enable_source(struct coresight_device *csdev, u32 mode) { int ret; - if (!coresight_source_is_unique(csdev)) { - dev_warn(&csdev->dev, "traceID %d not unique\n", - source_ops(csdev)->trace_id(csdev)); - return -EINVAL; - } - if (!csdev->enable) { if (source_ops(csdev)->enable) { ret = coresight_control_assoc_ectdev(csdev, true); @@ -1763,11 +1732,15 @@ static int __init coresight_init(void) if (ret) goto exit_bus_unregister; + /* initialise the trace ID map */ + coresight_trace_id_init_id_map(coresight_get_trace_id_map()); + /* initialise the coresight syscfg API */ ret = cscfg_init(); if (!ret) return 0; + coresight_trace_id_release_id_map(coresight_get_trace_id_map()); etm_perf_exit(); exit_bus_unregister: bus_unregister(&coresight_bustype); @@ -1776,6 +1749,7 @@ static int __init coresight_init(void) static void __exit coresight_exit(void) { + coresight_trace_id_release_id_map(coresight_get_trace_id_map()); cscfg_exit(); etm_perf_exit(); bus_unregister(&coresight_bustype); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index ff1dd2092ac5..d3032ac545c1 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -166,6 +166,7 @@ int coresight_make_links(struct coresight_device *orig, struct coresight_device *target); void coresight_remove_links(struct coresight_device *orig, struct coresight_connection *conn); +struct coresight_trace_id_map *coresight_get_trace_id_map(void); #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) extern int etm_readl_cp14(u32 off, unsigned int *val); From patchwork Tue Mar 8 20:49:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD8E9C433EF for ; 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Tue, 08 Mar 2022 12:50:07 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 03/10] coresight: stm: Update STM driver to use Trace ID api Date: Tue, 8 Mar 2022 20:49:53 +0000 Message-Id: <20220308205000.27646-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125009_286115_A00F3122 X-CRM114-Status: GOOD ( 20.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Updates the STM driver to use the trace ID allocation API. This uses the _system_id calls to allocate an ID on device poll, and release on device remove. The sysfs access to the STMTRACEIDR register has been changed from RW to RO. Having this value as writable is not appropriate for the new Trace ID scheme - and had potential to cause errors in the previous scheme if values clashed with other sources. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-stm.c | 41 +++++++-------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index bb14a3a8a921..6c2c29ae99fe 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -615,24 +616,7 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid = val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); #define coresight_stm_reg(name, offset) \ coresight_simple_reg32(struct stm_drvdata, name, offset) @@ -819,14 +803,6 @@ static void stm_init_default_data(struct stm_drvdata *drvdata) */ drvdata->stmsper = ~0x0; - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid = 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -854,7 +830,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -938,12 +914,22 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } + trace_id = coresight_trace_id_get_system_id(coresight_get_trace_id_map()); + if (trace_id < 0) { + ret = trace_id; + goto cs_unregister; + } + drvdata->traceid = (u8)trace_id; + pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -953,6 +939,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + coresight_trace_id_put_system_id(coresight_get_trace_id_map(), drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm); From patchwork Tue Mar 8 20:49:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11B4DC433F5 for ; Tue, 8 Mar 2022 20:52:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Tue, 08 Mar 2022 12:50:08 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:07 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 04/10] coresight: etm4x: Use trace ID API to dynamically allocate trace ID Date: Tue, 8 Mar 2022 20:49:54 +0000 Message-Id: <20220308205000.27646-5-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125010_146797_BA503347 X-CRM114-Status: GOOD ( 26.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The trace ID API is now used to allocate trace IDs for ETM4.x / ETE devices. For perf sessions, these will be allocated on enable, and released on disable. For sysfs sessions, these will be allocated on enable, but only released on reset. This allows the sysfs session to interrogate the Trace ID used after the session is over - maintaining functional consistency with the previous allocation scheme. The trace ID will also be allocated on read of the mgmt/trctraceid file. This ensures that if perf or sysfs read this before enabling trace, the value will be the one used for the trace session. Trace ID initialisation is removed from the _probe() function. Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-core.c | 63 +++++++++++++++++-- .../coresight/coresight-etm4x-sysfs.c | 32 +++++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + 3 files changed, 89 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7f416a12000e..aa7ea5ad8b06 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -42,6 +42,7 @@ #include "coresight-etm4x-cfg.h" #include "coresight-self-hosted-trace.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static int boot_enable; module_param(boot_enable, int, 0444); @@ -234,6 +235,36 @@ static int etm4_trace_id(struct coresight_device *csdev) return drvdata->trcid; } +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + if (trace_id > 0) { + spin_lock(&drvdata->spinlock); + drvdata->trcid = (u8)trace_id; + spin_unlock(&drvdata->spinlock); + } else { + pr_err("Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + } + return trace_id; +} + +void etm4_release_trace_id(struct etmv4_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + spin_lock(&drvdata->spinlock); + drvdata->trcid = 0; + spin_unlock(&drvdata->spinlock); +} + struct etm4_enable_arg { struct etmv4_drvdata *drvdata; int rc; @@ -717,9 +748,18 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_parse_event_config(csdev, event); if (ret) goto out; + + /* allocate a trace ID */ + ret = etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + goto out; + /* And enable it */ ret = etm4_enable_hw(drvdata); + /* failed to enable */ + if (ret) + etm4_release_trace_id(drvdata); out: return ret; } @@ -739,6 +779,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) return ret; } + /* allocate a trace ID */ + ret = etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + return ret; + spin_lock(&drvdata->spinlock); /* @@ -756,6 +801,8 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + else + etm4_release_trace_id(drvdata); return ret; } @@ -883,6 +930,9 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9)); + /* release trace ID - this may pend release if perf session is still active */ + etm4_release_trace_id(drvdata); + return 0; } @@ -908,6 +958,13 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); + /* + * unlike for perf session - we only release trace IDs when resetting + * sysfs. This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } @@ -1596,11 +1653,6 @@ static int etm4_dying_cpu(unsigned int cpu) return 0; } -static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) -{ - drvdata->trcid = coresight_get_trace_id(drvdata->cpu); -} - static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret = 0; @@ -2005,7 +2057,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) if (!desc.name) return -ENOMEM; - etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 21687cc1e4e2..bb69a203b833 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -266,10 +266,11 @@ static ssize_t reset_store(struct device *dev, config->vmid_mask0 = 0x0; config->vmid_mask1 = 0x0; - drvdata->trcid = drvdata->cpu + 1; - spin_unlock(&drvdata->spinlock); + /* for sysfs - only release trace id when resetting */ + etm4_release_trace_id(drvdata); + cscfg_csdev_reset_feats(to_coresight_device(dev)); return size; @@ -2355,6 +2356,31 @@ static struct attribute *coresight_etmv4_attrs[] = { NULL, }; +/* + * Trace ID allocated dynamically on enable - but also allocate on read + * in case sysfs or perf read before enable to ensure consistent metadata + * information for trace decode + */ +static ssize_t trctraceid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int trace_id; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + trace_id = etm4_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; + + return scnprintf(buf, PAGE_SIZE, "0x%x\n", trace_id); +} + +/* mgmt group uses extended attributes - no standard macro available */ +static struct dev_ext_attribute dev_attr_trctraceid = { + __ATTR(trctraceid, 0444, trctraceid_show, NULL), + (void *)(unsigned long)TRCTRACEIDR +}; + struct etmv4_reg { struct coresight_device *csdev; u32 offset; @@ -2491,7 +2517,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { coresight_etm4x_reg(trcpidr3, TRCPIDR3), coresight_etm4x_reg(trcoslsr, TRCOSLSR), coresight_etm4x_reg(trcconfig, TRCCONFIGR), - coresight_etm4x_reg(trctraceid, TRCTRACEIDR), + &dev_attr_trctraceid.attr.attr, coresight_etm4x_reg(trcdevarch, TRCDEVARCH), NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 3c4d69b096ca..64976a00c839 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1010,4 +1010,7 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) { return drvdata->arch >= ETM_ARCH_ETE; } + +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); +void etm4_release_trace_id(struct etmv4_drvdata *drvdata); #endif From patchwork Tue Mar 8 20:49:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D0BEC433F5 for ; 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Tue, 08 Mar 2022 12:50:08 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 05/10] coresight: etm3x: Use trace ID API to allocate IDs Date: Tue, 8 Mar 2022 20:49:55 +0000 Message-Id: <20220308205000.27646-6-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125010_243560_B458820C X-CRM114-Status: GOOD ( 21.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use the TraceID API to allocate ETM trace IDs dynamically. As with the etm4x we allocate on enable / disable for perf, allocate on enable / reset for sysfs. Additionally we allocate on sysfs file read as both perf and sysfs can read the ID before enabling the hardware. Remove sysfs option to write trace ID - which is inconsistent with both the dynamic allocation method and the fixed allocation method previously used. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm.h | 2 + .../coresight/coresight-etm3x-core.c | 72 ++++++++++++++++--- .../coresight/coresight-etm3x-sysfs.c | 28 +++----- 3 files changed, 71 insertions(+), 31 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index f3ab96eaf44e..3667428d38b6 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -287,4 +287,6 @@ int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); +void etm_release_trace_id(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 7d413ba8b823..98213503bd09 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -32,6 +32,7 @@ #include "coresight-etm.h" #include "coresight-etm-perf.h" +#include "coresight-trace-id.h" /* * Not really modular but using module_param is the easiest way to @@ -490,18 +491,57 @@ static int etm_trace_id(struct coresight_device *csdev) return etm_get_trace_id(drvdata); } +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + if (trace_id > 0) { + spin_lock(&drvdata->spinlock); + drvdata->traceid = (u8)trace_id; + spin_unlock(&drvdata->spinlock); + } else { + pr_err("Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + } + return trace_id; +} + +void etm_release_trace_id(struct etm_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu, + coresight_get_trace_id_map()); + spin_lock(&drvdata->spinlock); + drvdata->traceid = 0; + spin_unlock(&drvdata->spinlock); +} + static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + return ret; + /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); /* And enable it */ - return etm_enable_hw(drvdata); + ret = etm_enable_hw(drvdata); + + if (ret) + etm_release_trace_id(drvdata); + return ret; } static int etm_enable_sysfs(struct coresight_device *csdev) @@ -510,6 +550,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev) struct etm_enable_arg arg = { }; int ret; + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + return ret; + spin_lock(&drvdata->spinlock); /* @@ -532,6 +576,8 @@ static int etm_enable_sysfs(struct coresight_device *csdev) if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + else + etm_release_trace_id(drvdata); return ret; } @@ -611,6 +657,8 @@ static void etm_disable_perf(struct coresight_device *csdev) coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); + + etm_release_trace_id(drvdata); } static void etm_disable_sysfs(struct coresight_device *csdev) @@ -781,11 +829,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_trace_id(struct etm_drvdata *drvdata) -{ - drvdata->traceid = coresight_get_trace_id(drvdata->cpu); -} - static int __init etm_hp_setup(void) { int ret; @@ -871,7 +914,6 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) if (etm_arch_supported(drvdata->arch) == false) return -EINVAL; - etm_init_trace_id(drvdata); etm_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); @@ -891,10 +933,12 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(drvdata->csdev); ret = etm_perf_symlink(drvdata->csdev, true); - if (ret) { - coresight_unregister(drvdata->csdev); - return ret; - } + if (ret) + goto cs_unregister; + + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + goto cs_unregister; etmdrvdata[drvdata->cpu] = drvdata; @@ -907,6 +951,10 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) } return 0; + +cs_unregister: + coresight_unregister(drvdata->csdev); + return ret; } static void clear_etmdrvdata(void *info) @@ -922,6 +970,8 @@ static void etm_remove(struct amba_device *adev) etm_perf_symlink(drvdata->csdev, false); + etm_release_trace_id(drvdata); + /* * Taking hotplug lock here to avoid racing between etm_remove and * CPU hotplug call backs. diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index e8c7649f123e..3ee70b174240 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -86,6 +86,8 @@ static ssize_t reset_store(struct device *dev, etm_set_default(config); spin_unlock(&drvdata->spinlock); + /* release trace id outside the spinlock as this fn uses it */ + etm_release_trace_id(drvdata); } return size; @@ -1189,30 +1191,16 @@ static DEVICE_ATTR_RO(cpu); static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long val; - struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - val = etm_get_trace_id(drvdata); - - return sprintf(buf, "%#lx\n", val); -} - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; + int trace_id; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; + trace_id = etm_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; - drvdata->traceid = val & ETM_TRACEID_MASK; - return size; + return sprintf(buf, "%#x\n", trace_id); } -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); static struct attribute *coresight_etm_attrs[] = { &dev_attr_nr_addr_cmp.attr, From patchwork Tue Mar 8 20:49:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 477D3C433F5 for ; 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Tue, 08 Mar 2022 12:50:09 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 06/10] coresight: perf: traceid: Add perf notifiers for trace ID Date: Tue, 8 Mar 2022 20:49:56 +0000 Message-Id: <20220308205000.27646-7-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125011_110309_E96EDF45 X-CRM114-Status: GOOD ( 17.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds in notifier calls to the trace ID allocator that perf events are starting and stopping. This ensures that Trace IDs associated with CPUs remain the same throughout the perf session, and are only release when all perf sessions are complete. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index c039b6ae206f..008f9dac429d 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static struct pmu etm_pmu; static bool etm_perf_up; @@ -223,11 +224,21 @@ static void free_event_data(struct work_struct *work) struct list_head **ppath; ppath = etm_event_cpu_path_ptr(event_data, cpu); - if (!(IS_ERR_OR_NULL(*ppath))) + if (!(IS_ERR_OR_NULL(*ppath))) { coresight_release_path(*ppath); + /* + * perf may have read a trace id for a cpu, but never actually + * executed code on that cpu - which means the trace id would + * not release on disable. Re-release here to be sure. + */ + coresight_trace_id_put_cpu_id(cpu, coresight_get_trace_id_map()); + } *ppath = NULL; } + /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(); + free_percpu(event_data->path); kfree(event_data); } @@ -314,6 +325,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); } + /* tell the trace ID allocator that a perf event is starting up */ + coresight_trace_id_perf_start(); + /* check if user wants a coresight configuration selected */ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) { From patchwork Tue Mar 8 20:49:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 391FBC433F5 for ; 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Tue, 08 Mar 2022 12:50:10 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 07/10] perf: cs-etm: Update event to read trace ID from sysfs Date: Tue, 8 Mar 2022 20:49:57 +0000 Message-Id: <20220308205000.27646-8-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125012_541994_3AAABA70 X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Read the current trace ID values associated with a CPU from sysfs. Previously used the static association algorithm that is no longer used as it did not scale and was broken for larger core counts. Signed-off-by: Mike Leach --- tools/perf/arch/arm/util/cs-etm.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 2e8b2c4365a0..f48087d07bcb 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -43,11 +43,13 @@ struct cs_etm_recording { }; static const char *metadata_etmv3_ro[CS_ETM_PRIV_MAX] = { + [CS_ETM_ETMTRACEIDR] = "traceid", [CS_ETM_ETMCCER] = "mgmt/etmccer", [CS_ETM_ETMIDR] = "mgmt/etmidr", }; static const char * const metadata_etmv4_ro[] = { + [CS_ETMV4_TRCTRACEIDR] = "mgmt/trctraceid", [CS_ETMV4_TRCIDR0] = "trcidr/trcidr0", [CS_ETMV4_TRCIDR1] = "trcidr/trcidr1", [CS_ETMV4_TRCIDR2] = "trcidr/trcidr2", @@ -629,8 +631,9 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, /* Get trace configuration register */ data[CS_ETMV4_TRCCONFIGR] = cs_etmv4_get_config(itr); - /* Get traceID from the framework */ - data[CS_ETMV4_TRCTRACEIDR] = coresight_get_trace_id(cpu); + /* Get traceID from the sysfs */ + data[CS_ETMV4_TRCTRACEIDR] = cs_etm_get_ro(cs_etm_pmu, cpu, + metadata_etmv4_ro[CS_ETMV4_TRCTRACEIDR]); /* Get read-only information from sysFS */ data[CS_ETMV4_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]); @@ -677,9 +680,10 @@ static void cs_etm_get_metadata(int cpu, u32 *offset, magic = __perf_cs_etmv3_magic; /* Get configuration register */ info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr); - /* Get traceID from the framework */ + /* Get traceID from sysfs */ info->priv[*offset + CS_ETM_ETMTRACEIDR] = - coresight_get_trace_id(cpu); + cs_etm_get_ro(cs_etm_pmu, cpu, + metadata_etmv3_ro[CS_ETM_ETMTRACEIDR]); /* Get read-only information from sysFS */ info->priv[*offset + CS_ETM_ETMCCER] = cs_etm_get_ro(cs_etm_pmu, cpu, From patchwork Tue Mar 8 20:49:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FECCC433EF for ; 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Tue, 08 Mar 2022 12:50:11 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 08/10] coresight: Remove legacy Trace ID allocation mechanism Date: Tue, 8 Mar 2022 20:49:58 +0000 Message-Id: <20220308205000.27646-9-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125014_679727_DFB1DF9E X-CRM114-Status: GOOD ( 12.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This static 'cpu * 2 + seed' was outdated and broken for systems with high core counts (>46). This has been replaced by a dynamic allocation system. Signed-off-by: Mike Leach --- include/linux/coresight-pmu.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 4ac5c081af93..bb4eb4de3c77 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -8,7 +8,6 @@ #define _LINUX_CORESIGHT_PMU_H #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 /* * Below are the definition of bit offsets for perf option, and works as @@ -32,15 +31,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif From patchwork Tue Mar 8 20:49:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12774378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3061C433F5 for ; Tue, 8 Mar 2022 20:54:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 08 Mar 2022 12:50:12 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:11 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 09/10] coresight: etmX.X: stm: Remove unused legacy source trace ID ops Date: Tue, 8 Mar 2022 20:49:59 +0000 Message-Id: <20220308205000.27646-10-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125015_632115_A66D9D0E X-CRM114-Status: GOOD ( 18.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CoreSight sources provide a callback (.trace_id) in the standard source ops which returns the ID to the core code. This was used to check that sources all had a unique Trace ID. Uniqueness is now gauranteed by the Trace ID allocation system, and the check code has been removed from the core. This patch removes the unneeded and unused .trace_id source ops from the ops structure and implementations in etm3x, etm4x and stm. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm.h | 1 - .../coresight/coresight-etm3x-core.c | 37 ------------------- .../coresight/coresight-etm4x-core.c | 8 ---- drivers/hwtracing/coresight/coresight-stm.c | 8 ---- include/linux/coresight.h | 3 -- 5 files changed, 57 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 3667428d38b6..9a0d08b092ae 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -283,7 +283,6 @@ static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) } extern const struct attribute_group *coresight_etm_groups[]; -int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 98213503bd09..4cfb8ed699df 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -455,42 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -int etm_get_trace_id(struct etm_drvdata *drvdata) -{ - unsigned long flags; - int trace_id = -1; - struct device *etm_dev; - - if (!drvdata) - goto out; - - etm_dev = drvdata->csdev->dev.parent; - if (!local_read(&drvdata->mode)) - return drvdata->traceid; - - pm_runtime_get_sync(etm_dev); - - spin_lock_irqsave(&drvdata->spinlock, flags); - - CS_UNLOCK(drvdata->base); - trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); - CS_LOCK(drvdata->base); - - spin_unlock_irqrestore(&drvdata->spinlock, flags); - pm_runtime_put(etm_dev); - -out: - return trace_id; - -} - -static int etm_trace_id(struct coresight_device *csdev) -{ - struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return etm_get_trace_id(drvdata); -} - int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) { int trace_id; @@ -719,7 +683,6 @@ static void etm_disable(struct coresight_device *csdev, static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, - .trace_id = etm_trace_id, .enable = etm_enable, .disable = etm_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index aa7ea5ad8b06..565947de702a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -228,13 +228,6 @@ static int etm4_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -static int etm4_trace_id(struct coresight_device *csdev) -{ - struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return drvdata->trcid; -} - int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) { int trace_id; @@ -998,7 +991,6 @@ static void etm4_disable(struct coresight_device *csdev, static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, - .trace_id = etm4_trace_id, .enable = etm4_enable, .disable = etm4_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 6c2c29ae99fe..6aa6eb9e4090 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -281,15 +281,7 @@ static void stm_disable(struct coresight_device *csdev, } } -static int stm_trace_id(struct coresight_device *csdev) -{ - struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return drvdata->traceid; -} - static const struct coresight_ops_source stm_source_ops = { - .trace_id = stm_trace_id, .enable = stm_enable, .disable = stm_disable, }; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 9f445f09fcfe..247147c11231 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -314,14 +314,11 @@ struct coresight_ops_link { * Operations available for sources. * @cpu_id: returns the value of the CPU number this component * is associated to. - * @trace_id: returns the value of the component's trace ID as known - * to the HW. * @enable: enables tracing for a source. * @disable: disables tracing for a source. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); - int (*trace_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, u32 mode); void (*disable)(struct coresight_device *csdev, From patchwork Tue Mar 8 20:50:00 2022 Content-Type: text/plain; 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Tue, 08 Mar 2022 12:50:12 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id p26-20020a1c741a000000b00389ab9a53c8sm3245758wmc.36.2022.03.08.12.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 12:50:12 -0800 (PST) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, Mike Leach Subject: [PATCH 10/10] coresight: trace-id: Add debug & test macros to trace id allocation Date: Tue, 8 Mar 2022 20:50:00 +0000 Message-Id: <20220308205000.27646-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> References: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_125015_723797_70D0118E X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds in a number of pr_debug macros to allow the debugging and test of the trace ID allocation system. Signed-off-by: Mike Leach --- .../hwtracing/coresight/coresight-trace-id.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c index ce6c7d7b55d6..8dcb698b8899 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -71,6 +71,27 @@ static int coresight_trace_id_find_new_id(struct coresight_trace_id_map *id_map) return id; } +/* #define TRACE_ID_DEBUG 1 */ +#ifdef TRACE_ID_DEBUG +static void coresight_trace_id_dump_table(struct coresight_trace_id_map *id_map, + const char *func_name) +{ + /* currently 2 u64s are sufficient to hold all the ids */ + pr_debug("%s id_map::\n", func_name); + pr_debug("Avial= 0x%016lx%016lx\n", id_map->avail_ids[1], id_map->avail_ids[0]); + pr_debug("Pend = 0x%016lx%016lx\n", id_map->pend_rel_ids[1], id_map->pend_rel_ids[0]); +} +#define DUMP_ID_MAP(map) coresight_trace_id_dump_table(map, __func__) +#define DUMP_ID_CPU(cpu, id) pr_debug("%s called; cpu=%d, id=%d\n", __func__, cpu, id) +#define DUMP_ID(id) pr_debug("%s called; id=%d\n", __func__, id) +#define PERF_SESSION(n) pr_debug("%s perf count %d\n", __func__, n) +#else +#define DUMP_ID_MAP(map) +#define DUMP_ID(id) +#define DUMP_ID_CPU(cpu, id) +#define PERF_SESSION(n) +#endif + /* release all pending IDs for all current maps & clear CPU associations */ static void coresight_trace_id_release_all_pending(void) { @@ -82,6 +103,7 @@ static void coresight_trace_id_release_all_pending(void) clear_bit(bit, id_map->avail_ids); clear_bit(bit, id_map->pend_rel_ids); } + DUMP_ID_MAP(id_map); } for_each_possible_cpu(cpu) { @@ -112,6 +134,8 @@ int coresight_trace_id_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map get_cpu_id_out: spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); return id; } EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id); @@ -138,6 +162,8 @@ void coresight_trace_id_put_cpu_id(int cpu, struct coresight_trace_id_map *id_ma put_cpu_id_out: spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); } EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id); @@ -152,6 +178,8 @@ int coresight_trace_id_get_system_id(struct coresight_trace_id_map *id_map) coresight_trace_id_set_inuse(id, id_map); spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID(id); + DUMP_ID_MAP(id_map); return id; } EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id); @@ -163,6 +191,9 @@ void coresight_trace_id_put_system_id(struct coresight_trace_id_map *id_map, int spin_lock_irqsave(&id_map_lock, flags); coresight_trace_id_clear_inuse(id, id_map); spin_unlock_irqrestore(&id_map_lock, flags); + + DUMP_ID(id); + DUMP_ID_MAP(id_map); } EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); @@ -172,6 +203,7 @@ void coresight_trace_id_perf_start(void) spin_lock_irqsave(&id_map_lock, flags); perf_cs_etm_session_active++; + PERF_SESSION(perf_cs_etm_session_active); spin_unlock_irqrestore(&id_map_lock, flags); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); @@ -182,6 +214,7 @@ void coresight_trace_id_perf_stop(void) spin_lock_irqsave(&id_map_lock, flags); perf_cs_etm_session_active--; + PERF_SESSION(perf_cs_etm_session_active); if (!perf_cs_etm_session_active) coresight_trace_id_release_all_pending(); spin_unlock_irqrestore(&id_map_lock, flags);