From patchwork Wed Mar 9 10:08:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12774886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06CC1C433EF for ; Wed, 9 Mar 2022 10:08:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=bjSbRl0mWyJq1B5eJe1XGy/DRZXAn78jGLO/Dse8/QY=; b=ItPTQF4v2z7UyE sQnv/UG215rifIM4SMkNtVSp02/QGzHRcaVDytOwuDr8YP7PJW2h3KyH3YBlb+OlaLlheGjZaqrji OCOzuC6MzK0HEt0/KGli2pjV83v7kGXS4dw04FNJA9jgUHj2HYFMbs6jiMUXsHQLTTDIo6zrrzm39 h8+ycS8zc28vHTaaA5CcdKdyH/KAZvhgcqqFqgMxt9iOzmaaFXJmSKW/npJWsD/hO/HOvhWUan0L4 spN51ltsmlVkiiL6SPgdodA2Y8cdtv3CmNbDX33ZIM68JpWFJ0mS1aQ2J9VF6WgWpX10lsR5cT9O/ dLRVQVLinhtI3cG2IqtA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRtE0-0084r3-2f; Wed, 09 Mar 2022 10:07:20 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRtDq-0084or-DB for linux-arm-kernel@lists.infradead.org; Wed, 09 Mar 2022 10:07:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646820431; x=1678356431; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=OgkXGpZYo7BvkpR/FYU9AJidJxqpmQ20r41+loe2PsA=; b=bK7YuN64bu22oR3wSd9mOSrjmWFE83ta5dAn91qu3pS4kWSsuVVCdVPW mDBOJM5kIJMFz1VL0aBO99q3wTXFKmYMD6NyVBPqBWyQ66j94SgGbYttg SJgsor4UbqbI6d8BpY9i9hzK+rhkSzMSOEFxBf3Qh5+96D5G8Xja5t+ix Fk2cEDgPnxrxjWzWSVDI/sRHjLaQIjd/xhe4pwm5UGgUME+PBRZpCPgvM 1mCo0QBk1S1XwTLtTyWDN+aUEcmBJm5waxY0csTS9k+6c1PxhN4jA3U9Y eprxoxTouW0ZuIxI8a1JX6mp7t3BG9yWUSpNYu3jrncx3FgmKqSnx228C Q==; X-IronPort-AV: E=Sophos;i="5.90,167,1643698800"; d="scan'208";a="148595292" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Mar 2022 03:07:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 9 Mar 2022 03:07:07 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 9 Mar 2022 03:07:05 -0700 From: Claudiu Beznea To: , , , CC: , , Claudiu Beznea Subject: [PATCH] ARM: at91: Kconfig: implement PIT64B selection Date: Wed, 9 Mar 2022 12:08:02 +0200 Message-ID: <20220309100802.3610259-1-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_020710_563804_613135B7 X-CRM114-Status: GOOD ( 10.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Implement PIT64B selection thus it will be available for the necessary targets (at the moment SAM9X60 and SAMA7G5) w/o the necessity to specify it via defconfig. With this the current CONFIG_TIMER_OF dependency of PIT64B driver could be removed. Along with changes on AT91 Kconfig removed CONFIG_MICROCHIP_PIT64B from defconfigs. Signed-off-by: Claudiu Beznea --- arch/arm/configs/at91_dt_defconfig | 1 - arch/arm/configs/multi_v7_defconfig | 1 - arch/arm/configs/sama7_defconfig | 1 - arch/arm/mach-at91/Kconfig | 9 +++++++++ 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 549d01be0b47..04f71dac9c97 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -195,7 +195,6 @@ CONFIG_RTC_DRV_AT91SAM9=y CONFIG_DMADEVICES=y CONFIG_AT_HDMAC=y CONFIG_AT_XDMAC=y -CONFIG_MICROCHIP_PIT64B=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=y CONFIG_AT91_ADC=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 8863fa969ede..bec62d5aa3c6 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -989,7 +989,6 @@ CONFIG_APQ_MMCC_8084=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y -CONFIG_MICROCHIP_PIT64B=y CONFIG_BCM2835_MBOX=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_TEGRA_IOMMU_GART=y diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 07b0494ef743..2b0f020a18eb 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -182,7 +182,6 @@ CONFIG_RTC_DRV_AT91SAM9=y CONFIG_DMADEVICES=y CONFIG_AT_XDMAC=y CONFIG_STAGING=y -CONFIG_MICROCHIP_PIT64B=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=y CONFIG_IIO_SW_TRIGGER=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 279810381256..1531b4625c76 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -165,6 +165,15 @@ config ATMEL_CLOCKSOURCE_TCB to make a single 32-bit timer. It can also be used as a clock event device supporting oneshot mode. +config MICROCHIP_CLOCKSOURCE_PIT64B + bool "64-bit Periodic Interval Timer (PIT64B) support" + default SOC_SAM9X60 || SOC_SAMA7 + select MICROCHIP_PIT64B + help + Select this to get a high resolution clockevent (SAM9X60) or + clocksource and clockevent (SAMA7G5) based on Microchip 64-bit + Periodic Interval Timer. + config HAVE_AT91_UTMI bool