From patchwork Mon Mar 14 16:13:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dixit, Ashutosh" X-Patchwork-Id: 12780358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53FD5C433F5 for ; Mon, 14 Mar 2022 16:13:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7CC1610E375; Mon, 14 Mar 2022 16:13:21 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7DAE510E36D for ; Mon, 14 Mar 2022 16:13:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647274399; x=1678810399; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=K6cn8eAtloBZzTIoqa/JzrkfAc3L5r9EMlLdZf+nUbM=; b=l8ugbfRhA1cN6vloOywwLU+x6kEaDG9svClM7t+jTvSg9KcehxEJG99f cLIKS0vj87bDGHrVmwruQ5fBTMItTgNojVx50CdebVzStPwH+RzLWQVu2 8hzi4T+TaBzsh5NbN27i+hhmaw3U9RiPjIiLyRDEvPG2BJb8hLOcXFbsP +E1UzidA+JniDCbhBb3ce4aD/D2BCOZu+86fMxjLOZf3ZQDKEv+G8NkA2 wxaW4iygjBpFTvWsJz7V/UoRs1Uflf8aH57GLYToOxCLEwWeWzP+dy4av AX15pXcgyEU1p5g1XNykxGEQUoBq0pHXL8LkGHVhqwGW7Y4tjsGtdFwo/ Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10285"; a="255802074" X-IronPort-AV: E=Sophos;i="5.90,181,1643702400"; d="scan'208";a="255802074" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 09:13:18 -0700 X-IronPort-AV: E=Sophos;i="5.90,181,1643702400"; d="scan'208";a="634252913" Received: from orsosgc001.jf.intel.com (HELO unerlige-ril-10.165.21.154.com) ([10.165.21.154]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 09:13:18 -0700 From: Ashutosh Dixit To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Mar 2022 09:13:10 -0700 Message-Id: <20220314161310.6468-1-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Because VLV_GT_RENDER_RC6 == GEN6_GT_GFX_RC6, the IS_VALLEYVIEW() check is not needed. Neither is the check present in other code paths which call intel_rc6_residency_ns() (in functions gen6_drpc(), rc6_residency() and rc6_residency_ms_show()). v2: Elimintate VLV_GT_RENDER_RC6 #define (Jani) Cc: Jani Nikula Signed-off-by: Ashutosh Dixit Reviewed-by: Badal Nilawar --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 - drivers/gpu/drm/i915/i915_pmu.c | 5 +---- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 4a1c74b8de05..437e96bb3b93 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -113,7 +113,7 @@ static int vlv_drpc(struct seq_file *m) seq_printf(m, "Media Power Well: %s\n", (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); - print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); + print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6); print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); return fw_domains_show(m, NULL); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 19cd34f24263..201b507c9dde 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1440,7 +1440,6 @@ #define VLV_MEDIA_RC6_COUNT_EN (1 << 1) #define VLV_RENDER_RC6_COUNT_EN (1 << 0) #define GEN6_GT_GFX_RC6 _MMIO(0x138108) -#define VLV_GT_RENDER_RC6 _MMIO(0x138108) #define VLV_GT_MEDIA_RC6 _MMIO(0x13810c) #define GEN6_GT_GFX_RC6p _MMIO(0x13810c) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index cfc21042499d..3e3b09588fd3 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -148,10 +148,7 @@ static u64 __get_rc6(struct intel_gt *gt) struct drm_i915_private *i915 = gt->i915; u64 val; - val = intel_rc6_residency_ns(>->rc6, - IS_VALLEYVIEW(i915) ? - VLV_GT_RENDER_RC6 : - GEN6_GT_GFX_RC6); + val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6); if (HAS_RC6p(i915)) val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);