From patchwork Tue Mar 15 01:22:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12780944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 408CCC433EF for ; Tue, 15 Mar 2022 01:22:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235931AbiCOBXe (ORCPT ); Mon, 14 Mar 2022 21:23:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232197AbiCOBXe (ORCPT ); Mon, 14 Mar 2022 21:23:34 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3CA9473AD for ; Mon, 14 Mar 2022 18:22:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647307343; x=1678843343; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PKszj6CAu8MoHMDEAuVMKAqw3WQzc+XKu47yhB2+r6k=; b=T2p0LN1K9irzxHtILAr9YD4J8S3A2E8Y6XIEKKTkzaC1ELt/NXY4JPpG KA4YKMFEwCTd7nn5yzJMGcyXu7AIs0UeHkC69B5SkK/s2tVFYCTey+u1Z U6g2DL37ah/ANNsj8elEjbsJkMKI+/4GX2pKkF2IXLpW4pEl8SNUNeeTr WsDutlX0yU096eZeyTnLaz2GX6IonBIQV6adp2nYQYaRV9YmA3Us7nv4G ++z9SQ8Kq3Qu5mUBTiHJely0v0Bj6ocfnJHIpTqb5w4qf0gW4vjjFNA0I CA0L0BPw5WXusDjH5d7mPaW5LBLOPKrMqh1UnZoCSnbn4Z530jeP/C44M Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10286"; a="238353707" X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="238353707" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:23 -0700 X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="634418536" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:22 -0700 Subject: [PATCH v2 1/6] cxl/mem: Drop DVSEC vs EFI Memory Map sanity check From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , ben.widawsky@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Mon, 14 Mar 2022 18:22:22 -0700 Message-ID: <164730734246.3806189.13995924771963139898.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> References: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org When the driver finds legacy DVSEC ranges active on a CXL Memory Expander it indicates that platform firmware is not aware of, or is deliberately disabling common CXL 2.0 operation. In this case Linux generally has no choice, but to leave the device alone. The driver attempts to validate that the DVSEC range is in the EFI memory map. Remove that logic since there is no requirement that the BIOS publish DVSEC ranges in the EFI Memory Map. In the future the driver will want to permanently reserve this capacity out of the available CFMWS capacity and hide it from request_free_mem_region(), but it serves no purpose to warn about the range not appearing in the EFI Memory Map. Reviewed-by: Davidlohr Bueso Signed-off-by: Dan Williams Reviewed-by: Ben Widawsky Reviewed-by: Jonathan Cameron --- drivers/cxl/mem.c | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 49a4b1c47299..cd4e8bba82aa 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -158,30 +158,8 @@ static int cxl_mem_probe(struct device *dev) * is no use in trying to manage those. */ if (!cxl_dvsec_decode_init(cxlds)) { - struct cxl_endpoint_dvsec_info *info = &cxlds->info; - int i; - - /* */ - for (i = 0; i < 2; i++) { - u64 base, size; - - /* - * Give a nice warning to the user that BIOS has really - * botched things for them if it didn't place DVSEC - * ranges in the memory map. - */ - base = info->dvsec_range[i].start; - size = range_len(&info->dvsec_range[i]); - if (size && !region_intersects(base, size, - IORESOURCE_SYSTEM_RAM, - IORES_DESC_NONE)) { - dev_err(dev, - "DVSEC range %#llx-%#llx must be reserved by BIOS, but isn't\n", - base, base + size - 1); - } - } dev_err(dev, - "Active DVSEC range registers in use. Will not bind.\n"); + "Legacy range registers configuration prevents HDM operation.\n"); return -EBUSY; } From patchwork Tue Mar 15 01:22:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12780945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1DFDC433F5 for ; Tue, 15 Mar 2022 01:22:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239092AbiCOBXk (ORCPT ); Mon, 14 Mar 2022 21:23:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232197AbiCOBXj (ORCPT ); Mon, 14 Mar 2022 21:23:39 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06731473B5 for ; Mon, 14 Mar 2022 18:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647307349; x=1678843349; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ekg3QkenQ6oQU9t/hc85Ktv8B5R0T7HshHJ+qzqcGxk=; b=VYLK649QrbG7RKTbfhE06LsSzkQelUEi3YRrVbWrrsuxhXPISBvJ4TJt syC9eO2DXC3cXAqQqgmQCr/jJMefoITUujm1d2ezVfQ/maqPevqvBVMqk X8g5qcSKIAwxloV7ugWxjYFxTxGRA6OUCMWWaATGJZBM68bwA1CpjdYZ5 pQr4TsPuZVbRvzKU9Z1MRtnEDYXly1OkLJ0VYjiq2GwPWa0gZklQ167j9 Oal7cB7Iz6eG4JLXxAPwlHpM0zg+36PRJKvGdRj+XCQw/fKOPwwzfLBej Egb+dv6hXP6+uIWy/cjEq1/g2eVD30mUwiMiu5DGFyU50w2TNodyItG3Y g==; X-IronPort-AV: E=McAfee;i="6200,9189,10286"; a="255914710" X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="255914710" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:28 -0700 X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="540225755" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:28 -0700 Subject: [PATCH v2 2/6] cxl/pci: Add debug for DVSEC range init failures From: Dan Williams To: linux-cxl@vger.kernel.org Cc: ben.widawsky@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Mon, 14 Mar 2022 18:22:28 -0700 Message-ID: <164730734812.3806189.2726330688692684104.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> References: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org In preparation for not treating DVSEC range initialization failures as fatal to cxl_pci_probe() add individual dev_dbg() statements for each of the major failure reasons in cxl_dvsec_ranges(). The rationale for cxl_dvsec_ranges() failure not being fatal is that there is still value for cxl_pci to enable mailbox operations even if CXL.mem operation is disabled. Signed-off-by: Dan Williams Reviewed-by: Ben Widawsky Reviewed-by: Jonathan Cameron --- drivers/cxl/pci.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 8a7267d116b7..257cf735505d 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -467,12 +467,15 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) { struct cxl_endpoint_dvsec_info *info = &cxlds->info; struct pci_dev *pdev = to_pci_dev(cxlds->dev); + struct device *dev = &pdev->dev; int d = cxlds->cxl_dvsec; int hdm_count, rc, i; u16 cap, ctrl; - if (!d) + if (!d) { + dev_dbg(dev, "No DVSEC Capability\n"); return -ENXIO; + } rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); if (rc) @@ -482,8 +485,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) if (rc) return rc; - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) + if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { + dev_dbg(dev, "Not MEM Capable\n"); return -ENXIO; + } /* * It is not allowed by spec for MEM.capable to be set and have 0 legacy @@ -496,8 +501,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) return -EINVAL; rc = wait_for_valid(cxlds); - if (rc) + if (rc) { + dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc); return rc; + } info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); From patchwork Tue Mar 15 01:22:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12780946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E530CC433F5 for ; Tue, 15 Mar 2022 01:22:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232197AbiCOBXp (ORCPT ); Mon, 14 Mar 2022 21:23:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240675AbiCOBXo (ORCPT ); Mon, 14 Mar 2022 21:23:44 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72099473AD for ; Mon, 14 Mar 2022 18:22:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647307354; x=1678843354; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Y8/1HRUjhcJVTtZMWkAf15PXRh7NExiq21R5cHxxQ4o=; b=NHBCD/cDQiK4wrlV7bSIcmV5rqqVlB3ajQouEmrRvUWek4xoOe5e5emL pyO8ejyNy+uVIKr6EdcNxexLzAccTbPZLVuRBac4OFZ/fsL5KgkmiknJW G1Aj5n8k6n8lUIop/QUpe1U5t3bpOdvek20s+avDKmfVOuNUBX/80pa43 Zm5ts6CFyymhbfXV8RGXFSzmPCanTE0ebebB0oBeR5AFtZfX0ETCdLauo hxvrBOz2zCgH/1hAdTXahWcK4RosRtD9y5CtCB6YdAbzzlJg+T+chNBlP 9/BmQEURMLzzGDiu0jmAbUSug9UAAtOBBdMgZhdkyj1B0PMJI4+xhedND w==; X-IronPort-AV: E=McAfee;i="6200,9189,10286"; a="256137493" X-IronPort-AV: E=Sophos;i="5.90,181,1643702400"; d="scan'208";a="256137493" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:33 -0700 X-IronPort-AV: E=Sophos;i="5.90,181,1643702400"; d="scan'208";a="690031974" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:33 -0700 Subject: [PATCH v2 3/6] cxl/mem: Make cxl_dvsec_range() init failure fatal From: Dan Williams To: linux-cxl@vger.kernel.org Cc: ben.widawsky@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Mon, 14 Mar 2022 18:22:33 -0700 Message-ID: <164730735324.3806189.4167509857771192422.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> References: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org In preparation for the cxl_pci driver to continue operation after cxl_dvsec_range() failure, update cxl_mem to check for negative error codes in info->ranges. Treat that condition as fatal regardless of the state of the HDM configuration since cxl_mem needs positive confirmation that legacy ranges were not established by platform firmware or another agent. Signed-off-by: Dan Williams Reviewed-by: Ben Widawsky Reviewed-by: Jonathan Cameron ranges < 0) + return false; + /* map hdm decoder */ crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE); if (!crb) { From patchwork Tue Mar 15 01:22:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12780947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7DD2C433EF for ; Tue, 15 Mar 2022 01:22:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240675AbiCOBXv (ORCPT ); Mon, 14 Mar 2022 21:23:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241657AbiCOBXu (ORCPT ); Mon, 14 Mar 2022 21:23:50 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9DDF473B2 for ; Mon, 14 Mar 2022 18:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647307359; x=1678843359; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gEcZs4d1EX/UWX70naqyxJMPT2UTtp/Atn0rM70ynIY=; b=k3+MMBJUURbZzpVeWQMANtwqXLv9O9pvjpkS14jKSxUZM8ZuBVFNRHUk z2NpiHKTJSRbKkRDJtT58+udJND0u9+rulw+wKaNChfKlgS8x0jtAbc6h nCxcP+gV4Jr5snmJ5Tqu8ZLVvzjdwc87ZE/0U3SOU16Vg38kJO7X5+7q3 qkPfN4MUT1siqiDEwljRhptSPD6H7BASHmyOM3LYry5bci7PFVIdqNnPU UDs0sd+I96nHqYymcxCpC+EyMo1V6rjytV/Ru2Um501fuLAQspU1tKaCH FFs14qlnRbLtBXTQzxDVQt19m+nllPZv6YmjohrDIW7IOG5O3+hmJgPbt g==; X-IronPort-AV: E=McAfee;i="6200,9189,10286"; a="238353731" X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="238353731" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:39 -0700 X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="549430520" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:39 -0700 Subject: [PATCH v2 4/6] cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pci From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Krzysztof Zach , ben.widawsky@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Mon, 14 Mar 2022 18:22:38 -0700 Message-ID: <164730735869.3806189.4032428192652531946.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> References: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org cxl_dvsec_ranges(), the helper for enumerating the presence of an active legacy CXL.mem configuration on a CXL 2.0 Memory Expander, is not fatal for cxl_pci because there is still value to enable mailbox operations even if CXL.mem operation is disabled. Recall that the reason cxl_pci does this initialization and not cxl_mem is to preserve the useful property (for unit testing) that cxl_mem is cxl_memdev + mmio generic, and does not require access to a 'struct pci_dev' to issue config cycles. Update 'struct cxl_endpoint_dvsec_info' to carry either a positive number of non-zero size legacy CXL DVSEC ranges, or the negative error code from __cxl_dvsec_ranges() in its @ranges member. Reported-by: Krzysztof Zach Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info") Signed-off-by: Dan Williams Reviewed-by: Jonathan Cameron --- drivers/cxl/pci.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 257cf735505d..994c79bf6afd 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -463,13 +463,18 @@ static int wait_for_media_ready(struct cxl_dev_state *cxlds) return 0; } -static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) +/* + * Return positive number of non-zero ranges on success and a negative + * error code on failure. The cxl_mem driver depends on ranges == 0 to + * init HDM operation. + */ +static int __cxl_dvsec_ranges(struct cxl_dev_state *cxlds, + struct cxl_endpoint_dvsec_info *info) { - struct cxl_endpoint_dvsec_info *info = &cxlds->info; struct pci_dev *pdev = to_pci_dev(cxlds->dev); + int hdm_count, rc, i, ranges = 0; struct device *dev = &pdev->dev; int d = cxlds->cxl_dvsec; - int hdm_count, rc, i; u16 cap, ctrl; if (!d) { @@ -546,10 +551,17 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) }; if (size) - info->ranges++; + ranges++; } - return 0; + return ranges; +} + +static void cxl_dvsec_ranges(struct cxl_dev_state *cxlds) +{ + struct cxl_endpoint_dvsec_info *info = &cxlds->info; + + info->ranges = __cxl_dvsec_ranges(cxlds, info); } static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) @@ -618,10 +630,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) return rc; - rc = cxl_dvsec_ranges(cxlds); - if (rc) - dev_warn(&pdev->dev, - "Failed to get DVSEC range information (%d)\n", rc); + cxl_dvsec_ranges(cxlds); cxlmd = devm_cxl_add_memdev(cxlds); if (IS_ERR(cxlmd)) From patchwork Tue Mar 15 01:22:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12780948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40511C433F5 for ; Tue, 15 Mar 2022 01:22:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242860AbiCOBX4 (ORCPT ); Mon, 14 Mar 2022 21:23:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241657AbiCOBX4 (ORCPT ); Mon, 14 Mar 2022 21:23:56 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCC8FC16 for ; Mon, 14 Mar 2022 18:22:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647307364; x=1678843364; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hb6dl8PX7NGSKgQvwoUymTUVDfyh8lyKKNolQsunB30=; b=kbSSuhBY5Z3t4yQt0PaOaqxTE+bTG/QjgzADb7USNWeVKLRz7hpp4PKv hVPDbN8pAh/HZEq1Wsp6RHi9cR2hgTKV/7ueMMpyukIjas00HH/wnUpD1 8dO5XdtySa1MCIOFbuQzOZ0cpcZGW1HffhL5VJ5TEj5TvQmaCaVb6xhmP pgpZmTTZMGuLavqQ7Fc9Dxef14UeM738oUiy9T78XIh4Ib0e7Wy8drn3e dTVYDu67VoKJLukOE+x9zKv2DhTTlD8oyjuxQQqWViIosKaSCK5ZzntAy ccgctSZneGXIHJROPgecIgYzhNKDOnJ5AX8uu8zrZlKmhqaujJnz/9a0f w==; X-IronPort-AV: E=McAfee;i="6200,9189,10286"; a="255914753" X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="255914753" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:44 -0700 X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="580334429" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:44 -0700 Subject: [PATCH v2 5/6] cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init() From: Dan Williams To: linux-cxl@vger.kernel.org Cc: ben.widawsky@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Mon, 14 Mar 2022 18:22:44 -0700 Message-ID: <164730736435.3806189.2537160791687837469.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> References: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org cxl_dvsec_decode_init() is tasked with checking whether legacy DVSEC range based decode is in effect, or whether HDM can be enabled / already is enabled. As such it either succeeds or fails and that result is the return value. The @do_hdm_init variable is misleading in the case where HDM operation is already found to be active, so just call it @retval. Signed-off-by: Dan Williams Reviewed-by: Jonathan Cameron --- drivers/cxl/mem.c | 12 ++++++------ tools/testing/cxl/mock_mem.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 50704deb2ff0..3baae1332760 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -68,7 +68,7 @@ static int create_endpoint(struct cxl_memdev *cxlmd, } /** - * cxl_dvsec_decode_init() - Setup HDM decoding for the endpoint + * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint * @cxlds: Device state * * Additionally, enables global HDM decoding. Warning: don't call this outside @@ -79,12 +79,12 @@ static int create_endpoint(struct cxl_memdev *cxlmd, * decoders, or if it can not be determined if DVSEC Ranges are in use. * Otherwise, returns true. */ -__mock bool cxl_dvsec_decode_init(struct cxl_dev_state *cxlds) +__mock bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds) { struct cxl_endpoint_dvsec_info *info = &cxlds->info; struct cxl_register_map map; struct cxl_component_reg_map *cmap = &map.component_map; - bool global_enable, do_hdm_init = false; + bool global_enable, retval = false; void __iomem *crb; u32 global_ctrl; @@ -113,7 +113,7 @@ __mock bool cxl_dvsec_decode_init(struct cxl_dev_state *cxlds) goto out; } - do_hdm_init = true; + retval = true; /* * Permanently (for this boot at least) opt the device into HDM @@ -129,7 +129,7 @@ __mock bool cxl_dvsec_decode_init(struct cxl_dev_state *cxlds) out: iounmap(crb); - return do_hdm_init; + return retval; } static int cxl_mem_probe(struct device *dev) @@ -160,7 +160,7 @@ static int cxl_mem_probe(struct device *dev) * If DVSEC ranges are being used instead of HDM decoder registers there * is no use in trying to manage those. */ - if (!cxl_dvsec_decode_init(cxlds)) { + if (!cxl_hdm_decode_init(cxlds)) { dev_err(dev, "Legacy range registers configuration prevents HDM operation.\n"); return -EBUSY; diff --git a/tools/testing/cxl/mock_mem.c b/tools/testing/cxl/mock_mem.c index d1dec5845139..69946f678cfa 100644 --- a/tools/testing/cxl/mock_mem.c +++ b/tools/testing/cxl/mock_mem.c @@ -4,7 +4,7 @@ #include struct cxl_dev_state; -bool cxl_dvsec_decode_init(struct cxl_dev_state *cxlds) +bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds) { return true; } From patchwork Tue Mar 15 01:22:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12780949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB3BDC433EF for ; Tue, 15 Mar 2022 01:22:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241657AbiCOBYD (ORCPT ); Mon, 14 Mar 2022 21:24:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244594AbiCOBYC (ORCPT ); Mon, 14 Mar 2022 21:24:02 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53E3D25F2 for ; Mon, 14 Mar 2022 18:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647307370; x=1678843370; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qN9p5xk/WTDkF0MZWYCxJPoJ4gEUABCCaka9eqvWLf4=; b=HgkqF10HA2rfFk6curRavQaO3b1+vNud0rkXk1fnEBCSOgnVo96T7FjC J+7vXZ076A1o9wKGowidvbLickKWGcCd1ANKLOeTg2dF5FWeu0PvHSJZN FxVcxD+sRQoV6BrQJQpNS6WBIZWzdVKRnulOWQY8bz/R2aiGUZqqJ0WFv 4Q1jPBzfDbzIha8ruu/Utg7OI4gS4tASFoKSk8poyEjp8WP9Lbcr6zP78 1drtmuw2dhIrQNdBMo1/RFuo3v7nYi+/syqMSn0lVU1rkYGkSl7ctJsgJ bFYUfNJl4nlj88PLOkuw1DiHB4vkY20Xb9s1CGyui8QAzg1UCadweMAQA g==; X-IronPort-AV: E=McAfee;i="6200,9189,10286"; a="319408179" X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="319408179" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:49 -0700 X-IronPort-AV: E=Sophos;i="5.90,182,1643702400"; d="scan'208";a="512432574" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 18:22:49 -0700 Subject: [PATCH v2 6/6] cxl/mem: Replace redundant debug message with a comment From: Dan Williams To: linux-cxl@vger.kernel.org Cc: ben.widawsky@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Mon, 14 Mar 2022 18:22:49 -0700 Message-ID: <164730736948.3806189.17828261054974867700.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> References: <164730733718.3806189.9721916820488234094.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org cxl_mem_probe() already emits a log message when HDM operation can not be established. Delete the similar one in cxl_hdm_decode_init(). What is less obvious is why global_ctrl being enabled makes positive values of info->ranges irrelevant. Signed-off-by: Dan Williams Reviewed-by: Jonathan Cameron --- drivers/cxl/mem.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 3baae1332760..6def7d7b6bfd 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -107,11 +107,16 @@ __mock bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds) global_ctrl = readl(crb + cmap->hdm_decoder.offset + CXL_HDM_DECODER_CTRL_OFFSET); global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE; - if (!global_enable && info->ranges) { - dev_dbg(cxlds->dev, - "DVSEC ranges already programmed and HDM decoders not enabled.\n"); + + /* + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base + * [High,Low] when HDM operation is enabled the range register values + * are ignored by the device, but the spec also recommends matching the + * DVSEC Range 1,2 to HDM Decoder Range 0,1 so, non-zero info->ranges + * are expected. + */ + if (!global_enable && info->ranges) goto out; - } retval = true;