From patchwork Tue Mar 15 07:48:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12781169 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFA34C433EF for ; Tue, 15 Mar 2022 07:56:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237754AbiCOH5e (ORCPT ); Tue, 15 Mar 2022 03:57:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235395AbiCOH5d (ORCPT ); Tue, 15 Mar 2022 03:57:33 -0400 X-Greylist: delayed 465 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 15 Mar 2022 00:56:21 PDT Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 077134BBA6 for ; Tue, 15 Mar 2022 00:56:20 -0700 (PDT) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4KHlrw4G1Pz9sR2; Tue, 15 Mar 2022 08:48:32 +0100 (CET) From: Stefan Roese To: netdev@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" Subject: [PATCH] net: phy: marvell: Add errata section 5.1 for Alaska PHY Date: Tue, 15 Mar 2022 08:48:27 +0100 Message-Id: <20220315074827.1439941-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Leszek Polak As per Errata Section 5.1, if EEE is intended to be used, some register writes must be done once after every hardware reset. This patch now adds the necessary register writes as listed in the Marvell errata. Without this fix we experience ethernet problems on some of our boards equipped with a new version of this ethernet PHY (different supplier). The fix applies to Marvell Alaska 88E1510/88E1518/88E1512/88E1514 Rev. A0. Signed-off-by: Leszek Polak Signed-off-by: Stefan Roese Cc: Andrew Lunn Cc: Heiner Kallweit Cc: Russell King Cc: David S. Miller Reviewed-by: Andrew Lunn --- drivers/net/phy/marvell.c | 42 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 2429db614b59..0f4a3ab4a415 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -1179,6 +1179,48 @@ static int m88e1510_config_init(struct phy_device *phydev) { int err; + /* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/ + * 88E1514 Rev A0, Errata Section 5.1: + * If EEE is intended to be used, the following register writes + * must be done once after every hardware reset. + */ + err = marvell_set_page(phydev, 0x00FF); + if (err < 0) + return err; + err = phy_write(phydev, 17, 0x214B); + if (err < 0) + return err; + err = phy_write(phydev, 16, 0x2144); + if (err < 0) + return err; + err = phy_write(phydev, 17, 0x0C28); + if (err < 0) + return err; + err = phy_write(phydev, 16, 0x2146); + if (err < 0) + return err; + err = phy_write(phydev, 17, 0xB233); + if (err < 0) + return err; + err = phy_write(phydev, 16, 0x214D); + if (err < 0) + return err; + err = phy_write(phydev, 17, 0xCC0C); + if (err < 0) + return err; + err = phy_write(phydev, 16, 0x2159); + if (err < 0) + return err; + err = marvell_set_page(phydev, 0x00FB); + if (err < 0) + return err; + err = phy_write(phydev, 07, 0xC00D); + if (err < 0) + return err; + err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE); + if (err < 0) + return err; + /* SGMII-to-Copper mode initialization */ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { /* Select page 18 */