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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2022 16:25:59.0151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c7cf218c-92d3-4b8b-ef47-08da06a07d3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4559 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Bit 1 of the IVFS IVInfo field indicates that IOMMU has been used for pre-boot DMA protection. Export this information to the kernel to allow other drivers to use it. Link: https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf Signed-off-by: Mario Limonciello Reported-by: kernel test robot --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/init.c | 18 ++++++++++++++++++ include/linux/amd-iommu.h | 5 +++++ 3 files changed, 24 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 47108ed44fbb..68e51213f119 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -407,6 +407,7 @@ /* IOMMU IVINFO */ #define IOMMU_IVINFO_OFFSET 36 #define IOMMU_IVINFO_EFRSUP BIT(0) +#define IOMMU_IVINFO_DMA_REMAP BIT(1) /* IOMMU Feature Reporting Field (for IVHD type 10h */ #define IOMMU_FEAT_GASUP_SHIFT 6 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 7bfe37e52e21..e9b669592dfc 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -182,6 +182,7 @@ u32 amd_iommu_max_pasid __read_mostly = ~0; bool amd_iommu_v2_present __read_mostly; static bool amd_iommu_pc_present __read_mostly; +static bool amdr_ivrs_remap_support __read_mostly; bool amd_iommu_force_isolation __read_mostly; @@ -326,6 +327,8 @@ static void __init early_iommu_features_init(struct amd_iommu *iommu, { if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) iommu->features = h->efr_reg; + if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) + amdr_ivrs_remap_support = true; } /* Access to l1 and l2 indexed register spaces */ @@ -3269,6 +3272,21 @@ struct amd_iommu *get_amd_iommu(unsigned int idx) return NULL; } +/* + * ivrs_remap_support - Is %IOMMU_IVINFO_DMA_REMAP set in IVRS table + * + * Returns true if the platform has %IOMMU_IVINFO_DMA_REMAP% set in the IOMMU + * IVRS IVInfo field. + * Presence of this flag indicates to the OS/HV that the IOMMU is used for + * Preboot DMA protection and device accessed memory should be remapped after + * the OS has loaded. + */ +bool amd_ivrs_remap_support(void) +{ + return amdr_ivrs_remap_support; +} +EXPORT_SYMBOL_GPL(amd_ivrs_remap_support); + /**************************************************************************** * * IOMMU EFR Performance Counter support functionality. This code allows diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 58e6c3806c09..d07b9fed6474 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -170,6 +170,7 @@ amd_iommu_update_ga(int cpu, bool is_run, void *data); extern int amd_iommu_activate_guest_mode(void *data); extern int amd_iommu_deactivate_guest_mode(void *data); +extern bool amd_ivrs_remap_support(void); #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ @@ -194,6 +195,10 @@ static inline int amd_iommu_deactivate_guest_mode(void *data) { return 0; } +static inline bool amd_ivrs_remap_support(void) +{ + return false; +} #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ int amd_iommu_get_num_iommus(void); From patchwork Tue Mar 15 16:24:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 12781637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C6D9C433FE for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2022 16:26:01.5579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 472eb2b1-7116-4328-ef7a-08da06a07ec0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3228 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The information is exported from the IOMMU driver whether or not pre-boot DMA protection has been enabled on AMD systems. Use this information to properly set iomma_dma_protection. Link: https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/oem-kernel-dma-protection Link: https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf Signed-off-by: Mario Limonciello Reported-by: kernel test robot --- drivers/thunderbolt/domain.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/thunderbolt/domain.c b/drivers/thunderbolt/domain.c index 7018d959f775..e03790735c12 100644 --- a/drivers/thunderbolt/domain.c +++ b/drivers/thunderbolt/domain.c @@ -6,6 +6,7 @@ * Author: Mika Westerberg */ +#include #include #include #include @@ -259,11 +260,15 @@ static ssize_t iommu_dma_protection_show(struct device *dev, { /* * Kernel DMA protection is a feature where Thunderbolt security is - * handled natively using IOMMU. It is enabled when IOMMU is - * enabled and ACPI DMAR table has DMAR_PLATFORM_OPT_IN set. + * handled natively using IOMMU. It is enabled when the IOMMU is + * enabled and either: + * ACPI DMAR table has DMAR_PLATFORM_OPT_IN set + * or + * ACPI IVRS table has DMA_REMAP bitset */ return sprintf(buf, "%d\n", - iommu_present(&pci_bus_type) && dmar_platform_optin()); + iommu_present(&pci_bus_type) && + (dmar_platform_optin() || amd_ivrs_remap_support())); } static DEVICE_ATTR_RO(iommu_dma_protection);