From patchwork Wed Mar 16 06:17:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12782302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3715C433FE for ; Wed, 16 Mar 2022 06:18:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353881AbiCPGTO (ORCPT ); Wed, 16 Mar 2022 02:19:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353868AbiCPGTF (ORCPT ); Wed, 16 Mar 2022 02:19:05 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5FE9DA5; Tue, 15 Mar 2022 23:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411469; x=1678947469; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ZOgr/touExLgastvk8G90GV7x9m0NeDf7OI5FkKHr5k=; b=ElcIjLp9Mdz3eWIDafcfExyrlgoMF6X1Ma8fK2bTMRIJ2wnOrcNN94QG Zamn+LgSoZt8IEq44HGqeGkQz0kdZcbWRc3cxYZtU9ZZ+cXUKpatXwO7E LphqltdvtN8ApK7c1KnNeh+K9kxbzEdYypIXKyi5vVRe2VK376LFXL0ir w=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:49 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:48 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:35 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id C3AC54495; Wed, 16 Mar 2022 11:47:34 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 1/6] ARM: dts: qcom: sdx65: Add spmi node Date: Wed, 16 Mar 2022 11:47:22 +0530 Message-Id: <1647411447-25249-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SPMI node to SDX65 dtsi. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 1457912..ba7b6c5 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -91,6 +91,25 @@ status = "disabled"; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sdx65-tlmm"; reg = <0xf100000 0x300000>; From patchwork Wed Mar 16 06:17:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12782306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C38B5C433FE for ; Wed, 16 Mar 2022 06:18:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353893AbiCPGTT (ORCPT ); Wed, 16 Mar 2022 02:19:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353879AbiCPGTO (ORCPT ); Wed, 16 Mar 2022 02:19:14 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C11D82183; Tue, 15 Mar 2022 23:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411471; x=1678947471; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=FIrvkil500o1PdSCRXvsNurD8KwexitS8f+fJQNePe8=; b=eigEuQv8DFsIvpSHxWQ6IIpd1becHWNsP0r4zFntRj0ZcdeWsEq3epsN IVuMnh+oQXaZgwAcVjY4o3Uh1klsWisIG+UcYBr/uDvmN8rBzp5D4kPjO Dhw4TGgLeBVpbbE8kap0pKqIwOKcoe9V5jxDYcYPsnTXt9OKgi3soVwEw c=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:50 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:36 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 3AC16478E; Wed, 16 Mar 2022 11:47:35 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 2/6] ARM: dts: qcom: sdx65-mtp: Add pmk8350b and pm8150b pmic Date: Wed, 16 Mar 2022 11:47:23 +0530 Message-Id: <1647411447-25249-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SDX65-mtp features PMK8350b and PM8150B pmic, so include the dts as well Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 59457da..9fa251a 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -5,6 +5,8 @@ /dts-v1/; #include "qcom-sdx65.dtsi" +#include +#include / { model = "Qualcomm Technologies, Inc. SDX65 MTP"; From patchwork Wed Mar 16 06:17:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12782305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22B64C4321E for ; Wed, 16 Mar 2022 06:18:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353909AbiCPGTS (ORCPT ); Wed, 16 Mar 2022 02:19:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353873AbiCPGTH (ORCPT ); Wed, 16 Mar 2022 02:19:07 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96A2A10F9; Tue, 15 Mar 2022 23:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411472; x=1678947472; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=fqpBGQKZ6UkUBYAv3Wglxp17UCjEC7sPUNPfOQbJYnY=; b=X2ZwU4wbn9eU+l0PoSb3s1ZTAIOo5MM0M87xq/PKfKotlSf14nIFufm6 VIu5W+TUyZKA4R/Zumep0kTeKOra96n7jg8HfV9fn6CLAXW7vm8No3Ft7 8plCOGYgVajnuZaTDKzN5O99TEYLecQob0hbGIgVSlyawYtFeMOqF2AUL k=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:50 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:36 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 9A6B34791; Wed, 16 Mar 2022 11:47:35 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 3/6] ARM: dts: qcom: sdx65-mtp: Add pmx65 pmic Date: Wed, 16 Mar 2022 11:47:24 +0530 Message-Id: <1647411447-25249-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SDX65-mtp features PMX65 pmic, so include the dts as well. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 9fa251a..408d30e 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -7,6 +7,7 @@ #include "qcom-sdx65.dtsi" #include #include +#include "qcom-pmx65.dtsi" / { model = "Qualcomm Technologies, Inc. SDX65 MTP"; From patchwork Wed Mar 16 06:17:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12782304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F130C433FE for ; Wed, 16 Mar 2022 06:18:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353904AbiCPGTQ (ORCPT ); Wed, 16 Mar 2022 02:19:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353872AbiCPGTH (ORCPT ); Wed, 16 Mar 2022 02:19:07 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E9931019; Tue, 15 Mar 2022 23:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411471; x=1678947471; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=maD+51x3NWHkFgFw6Zs9N4k7N1djcuz3El25dj6wKtM=; b=PjsPtFPNuNsfd2oSuYZDiJ/xUQ2QliHCgNEcSlnDPDTyBaPDs42wmyuB KezMIze0qeCvn2+KPSg0jLi0SGa2QUKp2l0jEYzxKkP9u/TFazaOwqlOX kIMPldlVZBKlOByKpq0RvdllxsTjS8UwQHqyw3gV+NdNDDhwZcXqOq4qE c=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:49 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:36 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 0B0F34495; Wed, 16 Mar 2022 11:47:36 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 4/6] ARM: dts: qcom: sdx65: Add rpmpd node Date: Wed, 16 Mar 2022 11:47:25 +0530 Message-Id: <1647411447-25249-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add rpmpd node and opps for this node to the SDX65 dts. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 51 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index ba7b6c5..7e2697f 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -244,6 +245,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx65-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; }; From patchwork Wed Mar 16 06:17:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12782303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86BF8C433EF for ; Wed, 16 Mar 2022 06:18:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353891AbiCPGTP (ORCPT ); Wed, 16 Mar 2022 02:19:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353871AbiCPGTH (ORCPT ); Wed, 16 Mar 2022 02:19:07 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC2A6E97; Tue, 15 Mar 2022 23:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411470; x=1678947470; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=GUK4JIE654NZxV1pFo5SaB16H7zXCfmo7RTrkPYh/S0=; b=dP1FW+AlJ3T0n9Q7JUc8gnMYGyZC9v58iKFX6dFSbdOqj1PZD45qFfdx CqfEnJuEdKZ4KaObjcDbElRIeTRQqNUV74VwEqKKkM6GiHEIaidZJHBOy LygJiGRf1XB1ooSL4yGc4rRy8IWYfkpNuyEOAPYhEx7t+0j6Morfu8ZzR M=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:50 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:48 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:37 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 8CB5F478E; Wed, 16 Mar 2022 11:47:36 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 5/6] ARM: dts: qcom: Add PMIC pmx65 dts Date: Wed, 16 Mar 2022 11:47:26 +0530 Message-Id: <1647411447-25249-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DTS for PMIC PMX65 found in Qualcomm platforms. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-pmx65.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-pmx65.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi new file mode 100644 index 0000000..5411b83 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + pmic@1 { + compatible = "qcom,pmx65", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx65_temp: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx65_gpios: pinctrl@8800 { + compatible = "qcom,pmx65-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Mar 16 06:17:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12782300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25C36C433F5 for ; Wed, 16 Mar 2022 06:17:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353856AbiCPGTC (ORCPT ); Wed, 16 Mar 2022 02:19:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240985AbiCPGTC (ORCPT ); Wed, 16 Mar 2022 02:19:02 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24FF7B3A; Tue, 15 Mar 2022 23:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411466; x=1678947466; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=lA3ekFHYJvDhRnQv+/S9aUMCren8dJhIW7h4IQb4LpE=; b=s6WqUfgfECKEFamKXecitKW0HmeSds2fzf4q4tASa5/fF5URTsrKnhH4 /fd9HUz97FMzHfpHveVeiPVkH9b882cFg2Ljssnzuf81KzVS/EiSFjCvj uQMaeDmNVqlEOKjHZjDzNJCWKeLxWX3qu3CBjDdwFKvk8Yrh/HegeZhYL 8=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:46 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:44 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:37 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 42D2E4495; Wed, 16 Mar 2022 11:47:37 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Add regulator nodes Date: Wed, 16 Mar 2022 11:47:27 +0530 Message-Id: <1647411447-25249-7-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the regulators found on SDX65 MTP. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 197 +++++++++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 408d30e..ad99f56 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "qcom-sdx65.dtsi" +#include #include #include #include "qcom-pmx65.dtsi" @@ -21,8 +22,204 @@ chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx65_bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; }; &blsp1_uart3 { status = "ok"; }; + +&apps_rsc { + pmx65-rpmh-regulators { + compatible = "qcom,pmx65-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-supply = <&vreg_s2b_1p224>; + vdd-l2-l18-supply = <&vreg_s2b_1p224>; + vdd-l3-supply = <&vreg_s8b_0p824>; + vdd-l4-supply = <&vreg_s7b_0p936>; + vdd-l5-l6-l16-supply = <&vreg_s4b_1p824>; + vdd-l7-supply = <&vreg_s3b_0p776>; + vdd-l8-l9-supply = <&vreg_s8b_0p824>; + vdd-l10-supply = <&vreg_bob_3p3>; + vdd-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l12-supply = <&vreg_s2b_1p224>; + vdd-l14-supply = <&vreg_s3b_0p776>; + vdd-l15-supply = <&vreg_s2b_1p224>; + vdd-l17-supply = <&vreg_s8b_0p824>; + vdd-l19-supply = <&vreg_s3b_0p776>; + vdd-l20-supply = <&vreg_s7b_0p936>; + vdd-l21-supply = <&vreg_s7b_0p936>; + + vreg_s2b_1p224: smps2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3b_0p776: smps3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s4b_1p824: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s7b_0p936: smps7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s8b_0p824: smps8 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1300000>; + }; + + ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + ldo3 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + ldo4 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo7 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + ldo8 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo16 { + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + regulator-initial-mode = ; + }; + + ldo17 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + ldo19 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + ldo20 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + ldo21 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; +};