From patchwork Fri Jan 4 21:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 10748865 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0D5891E for ; Fri, 4 Jan 2019 21:45:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C08CA287CD for ; Fri, 4 Jan 2019 21:45:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B4BE4287D1; Fri, 4 Jan 2019 21:45:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D7DAC287CD for ; Fri, 4 Jan 2019 21:45:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726253AbfADVpU (ORCPT ); Fri, 4 Jan 2019 16:45:20 -0500 Received: from avon.wwwdotorg.org ([104.237.132.123]:47944 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726094AbfADVpT (ORCPT ); Fri, 4 Jan 2019 16:45:19 -0500 Received: from swarren-lx1.nvidia.com (unknown [216.228.112.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id EF6511C0144; Fri, 4 Jan 2019 14:45:16 -0700 (MST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.2 at avon.wwwdotorg.org From: Stephen Warren To: Jingoo Han , Gustavo Pimentel Cc: Lorenzo Pieralisi , Bjorn Helgaas , linux-pci@vger.kernel.org, Stephen Warren , Arnd Bergmann , Faiz Abbas , Harro Haan , Jingoo Han , Joao Pinto , Juergen Beisert , Marek Vasut , Matthias Mann , Mohit Kumar , Pratyush Anand , Richard Zhu , Sean Cross , Shawn Guo , Siva Reddy Kallam , Srikanth T Shivanand , Tim Harvey Subject: [PATCH] PCI: dwc: fix MSI IRQ handler ordering Date: Fri, 4 Jan 2019 14:45:09 -0700 Message-Id: <20190104214509.16891-1-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-NVConfidentiality: public Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Warren The current code does this when handling MSI IRQs: a) Process the irq. b) Clear the latched IRQ status. If a new IRQ occurs any time after (a) has read the IRQ status for the last time and before (b), it will be lost. For example, this occurs in practice when using a Marvell 9171 AHCI controller with NCQ enabled; many command timeouts occur with certain disk access patterns. Fix the code to do the following instead, so that if any new IRQs are raised during the processing of the IRQ, the IRQ status is not cleared, so that the IRQ is not lost. a) Clear the latched IRQ status. b) Process the IRQ. This change reverts commit 8c934095fa2f ("PCI: dwc: Clear MSI interrupt status after it is handled, not before") This change re-applies commit ca1658921b63 ("PCI: designware: Fix missing MSI IRQs") Signed-off-by: Stephen Warren Cc: Arnd Bergmann Cc: Bjorn Helgaas Cc: Faiz Abbas Cc: Harro Haan Cc: Jingoo Han Cc: Joao Pinto Cc: Juergen Beisert Cc: Marek Vasut Cc: Matthias Mann Cc: Mohit Kumar Cc: Pratyush Anand Cc: Richard Zhu Cc: Sean Cross Cc: Shawn Guo Cc: Siva Reddy Kallam Cc: Srikanth T Shivanand Cc: Tim Harvey --- Note: This issue was found in downstream NVIDIA 4.9 and 4.14 kernels. However, the exact same code structure is present in mainline and I have no reason to believe the problem would not reproduce there. I have compile tested but not runtime tested it in mainline, since my board is not yet supported in mainline. --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 692dd1b264fb..7fd6c56a6f35 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -98,10 +98,10 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) irq = irq_find_mapping(pp->irq_domain, (i * MAX_MSI_IRQS_PER_CTRL) + pos); - generic_handle_irq(irq); dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + (i * MSI_REG_CTRL_BLOCK_SIZE), 4, 1 << pos); + generic_handle_irq(irq); pos++; } }