From patchwork Thu Mar 17 06:12:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09EABC433EF for ; Thu, 17 Mar 2022 06:22:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229876AbiCQGX2 (ORCPT ); Thu, 17 Mar 2022 02:23:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbiCQGW3 (ORCPT ); Thu, 17 Mar 2022 02:22:29 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D14311CF7C; Wed, 16 Mar 2022 23:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497563; x=1679033563; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=BT3ij+o+RNqqmo+4+LR+KXAEY8VWuAd61fJQJ8OAeq8=; b=LffZ1kSaLsU4L+CcP4gCB0EoI0eKzrnYrY/yPC/t4kNUhTW5y2NB0yKt 9eC6AjDyvKwctcir5Fy3JqQX3Vdu4f1xS5aR1w9/al6oAG+ai7EcJ6Im4 0nRFNJHuihH4eW4XofT3JFm1fWMCwNxCSZD+Z24Ena3iQHESoYIlK1WPm U=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 16 Mar 2022 23:12:42 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:42 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:42 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:39 -0700 From: Fenglin Wu To: , , CC: , , , , , Abhijeet Dharmapurikar Subject: [PATCH v6 01/10] spmi: pmic-arb: add a print in cleanup_irq Date: Thu, 17 Mar 2022 14:12:06 +0800 Message-ID: <1647497535-32151-2-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhijeet Dharmapurikar The cleanup_irq() was meant to clear and mask interrupts that were left enabled in the hardware but there was no interrupt handler registered for it. Add an error print when it gets invoked. Signed-off-by: Abhijeet Dharmapurikar Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 2113be4..5a99723 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -590,6 +590,8 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) u8 per = ppid & 0xFF; u8 irq_mask = BIT(id); + dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", + __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, From patchwork Thu Mar 17 06:12:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95C89C433F5 for ; Thu, 17 Mar 2022 06:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230031AbiCQGXZ (ORCPT ); Thu, 17 Mar 2022 02:23:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229952AbiCQGWb (ORCPT ); Thu, 17 Mar 2022 02:22:31 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6AEA124C31; Wed, 16 Mar 2022 23:12:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497565; x=1679033565; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=g3rY4bpEO25fMFkUyVjEe7VfSZehXBwtx/lekwobvxU=; b=rXlrHRHmzQnU3ht4Bxiy29SY8IystGc47XfhacjmpOSI/Vu6H2r/jN8R 0ZZ8RAdodDK1t+16dwalONmpTpA4P9ldSdAMtQHLyN6tdh0PlWRz4lpWi XstydSevZ9xb2p+BAuTmFDBhTHk8tJ/NMEx7uRn8CGx65YRg75eAhIKOx Y=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 16 Mar 2022 23:12:45 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:45 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:45 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:42 -0700 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v6 02/10] spmi: pmic-arb: handle spurious interrupt Date: Thu, 17 Mar 2022 14:12:07 +0800 Message-ID: <1647497535-32151-3-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Call handle_bad_irq() when the summary interrupt is fired spuriously. Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 5a99723..719bd73 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -605,10 +605,11 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) irq_mask, ppid); } -static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) +static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) { unsigned int irq; u32 status, id; + int handled = 0; u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF; u8 per = pmic_arb->apid_data[apid].ppid & 0xFF; @@ -623,7 +624,10 @@ static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) continue; } generic_handle_irq(irq); + handled++; } + + return handled; } static void pmic_arb_chained_irq(struct irq_desc *desc) @@ -634,7 +638,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) int first = pmic_arb->min_apid >> 5; int last = pmic_arb->max_apid >> 5; u8 ee = pmic_arb->ee; - u32 status, enable; + u32 status, enable, handled = 0; int i, id, apid; chained_irq_enter(chip, desc); @@ -649,10 +653,14 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) enable = readl_relaxed( ver_ops->acc_enable(pmic_arb, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) - periph_interrupt(pmic_arb, apid); + if (periph_interrupt(pmic_arb, apid) != 0) + handled++; } } + if (handled == 0) + handle_bad_irq(desc); + chained_irq_exit(chip, desc); } From patchwork Thu Mar 17 06:12:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91CE0C433F5 for ; Thu, 17 Mar 2022 06:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230021AbiCQGWl (ORCPT ); Thu, 17 Mar 2022 02:22:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229921AbiCQGWd (ORCPT ); Thu, 17 Mar 2022 02:22:33 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F7B7126F80; Wed, 16 Mar 2022 23:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497569; x=1679033569; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=OhR72xqFkzDx/cOjDRLsolT9JZibeLMb3xt2MB4DjB8=; b=ntq4Tk/6g3xEtCt3TPN91zsWRBCAOOPb8Y8VP0b9j5SU+SzysNoLyIT6 mAseXIWtTTCxtAaPBQSHmeMNCZAH/3pLAbb3Xr70QTvCZLjIl1TNaSO1n eFisc5x3XucReoWAp6p+ziqts3PyyhLA01GuOJ0IMKQ3hZ2YfJLs429W2 k=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 16 Mar 2022 23:12:49 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:48 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:48 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:45 -0700 From: Fenglin Wu To: , , , Greg Kroah-Hartman , Abhijeet Dharmapurikar , Kiran Gunda CC: , , , , Subject: [PATCH v6 03/10] spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq Date: Thu, 17 Mar 2022 14:12:08 +0800 Message-ID: <1647497535-32151-4-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Subbaraman Narayanamurthy Currently, cleanup_irq() is invoked when a peripheral's interrupt fires and there is no mapping present in the interrupt domain of spmi interrupt controller. The cleanup_irq clears the arbiter bit, clears the pmic interrupt and disables it at the pmic in that order. The last disable in cleanup_irq races with request_irq() in that it stomps over the enable issued by request_irq. Fix this by not writing to the pmic in cleanup_irq. The latched bit will be left set in the pmic, which will not send us more interrupts even if the enable bit stays enabled. When a client wants to request an interrupt, use the activate callback on the irq_domain to clear latched bit. This ensures that the latched, if set due to the above changes in cleanup_irq or when the bootloader leaves it set, gets cleaned up, paving way for upcoming interrupts to trigger. With this, there is a possibility of unwanted triggering of interrupt right after the latched bit is cleared - the interrupt may be left enabled too. To avoid that, clear the enable first followed by clearing the latched bit in the activate callback. Fixes: 6bc546e71e50 ("spmi: pmic-arb: cleanup unrequested irqs") Fixes: 02abec3616c1 ("spmi: pmic-arb: rename pa_xx to pmic_arb_xx and other cleanup") Signed-off-by: Subbaraman Narayanamurthy [collinsd@codeaurora.org: fix merge conflict] Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 719bd73..2bc3b88 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -593,16 +593,6 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); } static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) @@ -780,6 +770,7 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, u16 apid = hwirq_to_apid(d->hwirq); u16 sid = hwirq_to_sid(d->hwirq); u16 irq = hwirq_to_irq(d->hwirq); + u8 buf; if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", @@ -788,6 +779,10 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, return -ENODEV; } + buf = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); + return 0; } From patchwork Thu Mar 17 06:12:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFC22C433EF for ; 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Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 16 Mar 2022 23:12:51 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:51 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:50 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:48 -0700 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v6 04/10] spmi: pmic-arb: check apid against limits before calling irq handler Date: Thu, 17 Mar 2022 14:12:09 +0800 Message-ID: <1647497535-32151-5-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Check that the apid for an SPMI interrupt falls between the min_apid and max_apid that can be handled by the APPS processor before invoking the per-apid interrupt handler: periph_interrupt(). This avoids an access violation in rare cases where the status bit is set for an interrupt that is not owned by the APPS processor. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 2bc3b88..e19eaec 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -625,21 +625,26 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc); const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; struct irq_chip *chip = irq_desc_get_chip(desc); - int first = pmic_arb->min_apid >> 5; - int last = pmic_arb->max_apid >> 5; + int first = pmic_arb->min_apid; + int last = pmic_arb->max_apid; u8 ee = pmic_arb->ee; u32 status, enable, handled = 0; int i, id, apid; chained_irq_enter(chip, desc); - for (i = first; i <= last; ++i) { + for (i = first >> 5; i <= last >> 5; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); while (status) { id = ffs(status) - 1; status &= ~BIT(id); apid = id + i * 32; + if (apid < first || apid > last) { + WARN_ONCE(true, "spurious spmi irq received for apid=%d\n", + apid); + continue; + } enable = readl_relaxed( ver_ops->acc_enable(pmic_arb, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) From patchwork Thu Mar 17 06:12:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78AFBC433F5 for ; Thu, 17 Mar 2022 06:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbiCQGXH (ORCPT ); Thu, 17 Mar 2022 02:23:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229713AbiCQGWl (ORCPT ); Thu, 17 Mar 2022 02:22:41 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C117FCF4AC; Wed, 16 Mar 2022 23:12:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497574; x=1679033574; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=vFm/1iPltzV2y4DMijEhe5IyJTZ/LWY1V45aTZ9IiEs=; b=aQcM4w8+4W9fCZi4c+uNp+vdYori5WDUzAiOoT6iVPtwQ+I3MNa7M2OV tMF4MM0RbMjsNIWxP+qqjjjKNmxiPqkGJencPz11y/njKOHAGnf3L8oQh XcY6nm3i6oABkHn7N9UJh7o4b1Fj+goX26H7j4+j6KvycfEWRp2JMWVLk g=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 16 Mar 2022 23:12:54 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:54 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:53 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:51 -0700 From: Fenglin Wu To: , , CC: , , , , , "Ashay Jaiswal" Subject: [PATCH v6 05/10] spmi: pmic-arb: add support to dispatch interrupt based on IRQ status Date: Thu, 17 Mar 2022 14:12:10 +0800 Message-ID: <1647497535-32151-6-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Ashay Jaiswal Current implementation of SPMI arbiter dispatches interrupt based on the Arbiter's accumulator status, in some cases the accumulator status may remain zero and the interrupt remains un-handled. Add logic to dispatch interrupts based Arbiter's IRQ status if the accumulator status is zero. Signed-off-by: Ashay Jaiswal Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index e19eaec..56f2294 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -630,12 +630,18 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) u8 ee = pmic_arb->ee; u32 status, enable, handled = 0; int i, id, apid; + /* status based dispatch */ + bool acc_valid = false; + u32 irq_status = 0; chained_irq_enter(chip, desc); for (i = first >> 5; i <= last >> 5; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); + if (status) + acc_valid = true; + while (status) { id = ffs(status) - 1; status &= ~BIT(id); @@ -653,6 +659,29 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) } } + /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ + if (!acc_valid) { + for (i = first; i <= last; i++) { + /* skip if APPS is not irq owner */ + if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee) + continue; + + irq_status = readl_relaxed( + ver_ops->irq_status(pmic_arb, i)); + if (irq_status) { + enable = readl_relaxed( + ver_ops->acc_enable(pmic_arb, i)); + if (enable & SPMI_PIC_ACC_ENABLE_BIT) { + dev_dbg(&pmic_arb->spmic->dev, + "Dispatching IRQ for apid=%d status=%x\n", + i, irq_status); + if (periph_interrupt(pmic_arb, i) != 0) + handled++; + } + } + } + } + if (handled == 0) handle_bad_irq(desc); From patchwork Thu Mar 17 06:12:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F13EC433F5 for ; Thu, 17 Mar 2022 06:22:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229632AbiCQGXM (ORCPT ); Thu, 17 Mar 2022 02:23:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229754AbiCQGWp (ORCPT ); Thu, 17 Mar 2022 02:22:45 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D11EDEB9D; Wed, 16 Mar 2022 23:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497577; x=1679033577; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=HlBrxxqz8GrpwuEBJfdNjgmehq5A3syFPfEQuqOMWpg=; b=XLCipfRTarQlsU6Prs5bOXNwfTOIUkr8SveD7zWsPGsVgpspLq4PlD3j oyLAyqVyWH3GJOUH6bukirZDeOol7wQUcLQd33guJcva8CQh7LkTbjZFG Rbg+belRMpIF+EgPObfAf+5ane4VRZ3yrjRZ/yCvvNVyNg7w2Rp9uUbOw I=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 16 Mar 2022 23:12:57 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:57 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:56 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:54 -0700 From: Fenglin Wu To: , , , Greg Kroah-Hartman , "Kiran Gunda" , David Collins CC: , , , Subject: [PATCH v6 06/10] spmi: pmic-arb: correct duplicate APID to PPID mapping logic Date: Thu, 17 Mar 2022 14:12:11 +0800 Message-ID: <1647497535-32151-7-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Correct the way that duplicate PPID mappings are handled for PMIC arbiter v5. The final APID mapped to a given PPID should be the one which has write owner = APPS EE, if it exists, or if not that, then the first APID mapped to the PPID, if it exists. Fixes: 40f318f0ed67 ("spmi: pmic-arb: add support for HW version 5") Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 56f2294..cf92abc 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1031,7 +1031,8 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) * version 5, there is more than one APID mapped to each PPID. * The owner field for each of these mappings specifies the EE which is * allowed to write to the APID. The owner of the last (highest) APID - * for a given PPID will receive interrupts from the PPID. + * which has the IRQ owner bit set for a given PPID will receive + * interrupts from the PPID. */ for (i = 0; ; i++, apidd++) { offset = pmic_arb->ver_ops->apid_map_offset(i); @@ -1054,16 +1055,16 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; prev_apidd = &pmic_arb->apid_data[apid]; - if (valid && is_irq_ee && - prev_apidd->write_ee == pmic_arb->ee) { + if (!valid || apidd->write_ee == pmic_arb->ee) { + /* First PPID mapping or one for this EE */ + pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; + } else if (valid && is_irq_ee && + prev_apidd->write_ee == pmic_arb->ee) { /* * Duplicate PPID mapping after the one for this EE; * override the irq owner */ prev_apidd->irq_ee = apidd->irq_ee; - } else if (!valid || is_irq_ee) { - /* First PPID mapping or duplicate for another EE */ - pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; } apidd->ppid = ppid; From patchwork Thu Mar 17 06:12:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0606C433EF for ; Thu, 17 Mar 2022 06:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229605AbiCQGXU (ORCPT ); Thu, 17 Mar 2022 02:23:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230138AbiCQGWz (ORCPT ); Thu, 17 Mar 2022 02:22:55 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 091E1F845C; Wed, 16 Mar 2022 23:13:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497580; x=1679033580; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=C/nKcvGohh66HEoXJpfjN/wkXoY3VldhRoiyN4/ZYtg=; b=fyzuMzVlr1mwqq2SnFj4WeFpLYB7XCEz0IaPHEXb/S9k2q9ag1gnPeCD NgK5LcmK7ci2fCT8ij6M0bRDwh+wdm9xMtitQxxfoAjA8ffYcdYftL05c e5muzDz39B60B2cUyQ0Qj+0zA4+sGIYh4lwTRxJBMlgpGdBj0VljUw1on c=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 16 Mar 2022 23:12:59 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:12:59 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:59 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:57 -0700 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v6 07/10] spmi: pmic-arb: block access for invalid PMIC arbiter v5 SPMI writes Date: Thu, 17 Mar 2022 14:12:12 +0800 Message-ID: <1647497535-32151-8-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins The system crashes due to an access permission violation when writing to a PMIC peripheral which is not owned by the current ee. Add a check for PMIC arbiter version 5 for such invalid write requests and return an error instead of crashing the system. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index cf92abc..39f25bc 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1133,6 +1133,11 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr, offset = 0x10000 * pmic_arb->ee + 0x80 * apid; break; case PMIC_ARB_CHANNEL_RW: + if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) { + dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", + sid, addr); + return -EPERM; + } offset = 0x10000 * apid; break; } From patchwork Thu Mar 17 06:12:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C568C43217 for ; Thu, 17 Mar 2022 06:22:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229921AbiCQGXR (ORCPT ); Thu, 17 Mar 2022 02:23:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230186AbiCQGW5 (ORCPT ); Thu, 17 Mar 2022 02:22:57 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A172D10DA6D; Wed, 16 Mar 2022 23:13:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497583; x=1679033583; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ETtu/JXolCZgtw04vL8fJdMG86c05ohO0c9rbBE7X5M=; b=gNuqpOdtd1irsiZiMiCBWGa8z+VYJP8L4n6GS5Uzf1/J/XKgjpl/tetV DWqINVlth6j0YQg9Pz0tLla7GehZBvbLLtOcPTHiqnzRWNQAO7bsKrGGw wx0dC/1xxoVMnMjVLcbZujoZbTqx66F/4fXQNhVqZcIQN2XoheupQdamQ o=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 16 Mar 2022 23:13:03 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:13:03 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:13:02 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:12:59 -0700 From: Fenglin Wu To: , , , Andy Gross , Bjorn Andersson , Rob Herring , CC: , , , , Subject: [PATCH v6 08/10] dt-bindings: spmi: spmi-pmic-arb: make interrupt properties as optional Date: Thu, 17 Mar 2022 14:12:13 +0800 Message-ID: <1647497535-32151-9-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Make all interrupt related properties as optional instead of required. Some boards do not required PMIC IRQ support and it isn't needed to handle SPMI bus transactions, so specify it as optional. Signed-off-by: David Collins Signed-off-by: Fenglin Wu Acked-by: Rob Herring --- Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml index 55d379c..fee4f0e 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml @@ -88,9 +88,6 @@ properties: required: - compatible - reg-names - - interrupts - - interrupt-names - - '#interrupt-cells' - qcom,ee - qcom,channel From patchwork Thu Mar 17 06:12:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3E89C4332F for ; Thu, 17 Mar 2022 06:22:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229751AbiCQGXQ (ORCPT ); Thu, 17 Mar 2022 02:23:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230197AbiCQGW5 (ORCPT ); Thu, 17 Mar 2022 02:22:57 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84DB511BE49; Wed, 16 Mar 2022 23:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497586; x=1679033586; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=9W8MONWCB3nHa5cG39eCdoNQ68ZRf4zFDKZRUOobOfU=; b=S6d8EjiAmOws4OPCZCiKjsmCNcWPrmWy+l96LMuavGTkmh7wNHQyu31r MT7CRNVXY4/l0y9pwEjxFVV/LQ5OLSye1YdrlUA9Obe0Z3Euo7y5qlt2I A76Qn+HSfaCUNH4NJRTJhKYgd6f85frSK7M9CbknJ8/HW53Fn2gAzEVz6 w=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 16 Mar 2022 23:13:06 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:13:06 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:13:05 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:13:03 -0700 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v6 09/10] spmi: pmic-arb: make interrupt support optional Date: Thu, 17 Mar 2022 14:12:14 +0800 Message-ID: <1647497535-32151-10-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Make the support of PMIC peripheral interrupts optional for spmi-pmic-arb devices. This is useful in situations where SPMI address mapping is required without the need for IRQ support. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 45 +++++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 39f25bc..0496e5d 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1386,10 +1386,12 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) goto err_put_ctrl; } - pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq"); - if (pmic_arb->irq < 0) { - err = pmic_arb->irq; - goto err_put_ctrl; + if (of_find_property(pdev->dev.of_node, "interrupt-controller", NULL)) { + pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq"); + if (pmic_arb->irq < 0) { + err = pmic_arb->irq; + goto err_put_ctrl; + } } err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); @@ -1449,17 +1451,22 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) } } - dev_dbg(&pdev->dev, "adding irq domain\n"); - pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node, - &pmic_arb_irq_domain_ops, pmic_arb); - if (!pmic_arb->domain) { - dev_err(&pdev->dev, "unable to create irq_domain\n"); - err = -ENOMEM; - goto err_put_ctrl; + if (pmic_arb->irq > 0) { + dev_dbg(&pdev->dev, "adding irq domain\n"); + pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node, + &pmic_arb_irq_domain_ops, pmic_arb); + if (!pmic_arb->domain) { + dev_err(&pdev->dev, "unable to create irq_domain\n"); + err = -ENOMEM; + goto err_put_ctrl; + } + + irq_set_chained_handler_and_data(pmic_arb->irq, + pmic_arb_chained_irq, pmic_arb); + } else { + dev_dbg(&pdev->dev, "not supporting PMIC interrupts\n"); } - irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq, - pmic_arb); err = spmi_controller_add(ctrl); if (err) goto err_domain_remove; @@ -1467,8 +1474,10 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) return 0; err_domain_remove: - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + if (pmic_arb->irq > 0) { + irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); + irq_domain_remove(pmic_arb->domain); + } err_put_ctrl: spmi_controller_put(ctrl); return err; @@ -1479,8 +1488,10 @@ static int spmi_pmic_arb_remove(struct platform_device *pdev) struct spmi_controller *ctrl = platform_get_drvdata(pdev); struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); spmi_controller_remove(ctrl); - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + if (pmic_arb->irq > 0) { + irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); + irq_domain_remove(pmic_arb->domain); + } spmi_controller_put(ctrl); return 0; } From patchwork Thu Mar 17 06:12:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12783576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2959EC4332F for ; Thu, 17 Mar 2022 06:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229637AbiCQGXK (ORCPT ); Thu, 17 Mar 2022 02:23:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230233AbiCQGW7 (ORCPT ); Thu, 17 Mar 2022 02:22:59 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FCA910C53E; Wed, 16 Mar 2022 23:13:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647497589; x=1679033589; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Ht5tFAx/b0oY9oX+FB+kzZOocBM2sta/Sgzs8nZLw/o=; b=Cnr8lFPSq1BUf0+e7W3cBHskgEU2BYHYrketixJZWhcOZrvopVhY8UIg cJN8wQdMa4ALdOSfRo/FDytRKtlf0trdsSc6R6sisliwziukXfdVeqLuD B0olus5/jl8AXqrmo1Dp7jxs6wQuUgDlNN0YH0oRZPvYOk/5cg90C//C9 s=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 16 Mar 2022 23:13:09 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 23:13:08 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:13:08 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 23:13:06 -0700 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v6 10/10] spmi: pmic-arb: increase SPMI transaction timeout delay Date: Thu, 17 Mar 2022 14:12:15 +0800 Message-ID: <1647497535-32151-11-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> References: <1647497535-32151-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Increase the SPMI transaction timeout delay from 100 us to 1000 us in order to account for the slower execution time found on some simulator targets. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 0496e5d..45f9344 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -91,7 +91,7 @@ enum pmic_arb_channel { /* Maximum number of support PMIC peripherals */ #define PMIC_ARB_MAX_PERIPHS 512 -#define PMIC_ARB_TIMEOUT_US 100 +#define PMIC_ARB_TIMEOUT_US 1000 #define PMIC_ARB_MAX_TRANS_BYTES (8) #define PMIC_ARB_APID_MASK 0xFF