From patchwork Fri Mar 18 01:54:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 12784754 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D595C15C0 for ; Fri, 18 Mar 2022 01:54:54 +0000 (UTC) Received: by mail-pf1-f170.google.com with SMTP id t2so8287266pfj.10 for ; Thu, 17 Mar 2022 18:54:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U+oN2PkESqB41nkMUnSgEXHs7aUpmXvqHqu6nMf9ygI=; b=e9WddNIUJiPhK0Y81FA/RAxuWrUeVracIXuSi3Py1u61KIblEyW1HbOKaisIMnBTi8 TDwzciOOyCOYx0UUy/P3oZnZ7JJRHI6lzJskdLBCaZK0+h7qSdeVxqLbgaNpoQELVCkU 0zwHRWxvBUzUMAQFsx6V+6ZI0gsKLXAUjhI7g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U+oN2PkESqB41nkMUnSgEXHs7aUpmXvqHqu6nMf9ygI=; b=Cu+hEj0y6021rFIQNivbLKnhLU5q6cg49OpOhxmn+ZUWl34B00F9ICt0vALqwLW2XI DfgaJuaqBehqpdgv10YsFQVoBJnDSqU5aFZFZEKCfU3Fxw2ojJiYcVrNB3wOYT2Y+AZv 4D5kE4uJV3n24qGG88fJft9iffhuTaI50yAdL2mWu6DAohp7uN8BJE/u4qNBn9isl3mW XOqNDd1W5HMvx7rR25TYPxo7x9XYz1FB8zQFO0YDxSiN95tERArwf3zLZ078cBhJ3uym B4FsFn45pXcypznPyyaz8FS1RnAIyUG14hkVk9WiV/iCvy0I7NRBYZ0QDLRIFC/iRKfH bcyg== X-Gm-Message-State: AOAM532EQTCUmbLXdMUktxVhJHXoe3fRVYXDeogI8P8x1s2QS3Dh7Mm2 5d+XvRusoeelgd4e7mjR2h92tA== X-Google-Smtp-Source: ABdhPJw+tLB09E1yBm6TENEEbz+loQSPysQXCshfbFNSGsjCJDorbQbkjCs89FjWuc0TJkwWng5j9Q== X-Received: by 2002:a65:45c8:0:b0:380:352e:825b with SMTP id m8-20020a6545c8000000b00380352e825bmr5937245pgr.509.1647568494348; Thu, 17 Mar 2022 18:54:54 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:201:49cf:7701:359e:b28f]) by smtp.gmail.com with ESMTPSA id u10-20020a056a00124a00b004f783abfa0esm8050201pfi.28.2022.03.17.18.54.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 18:54:53 -0700 (PDT) From: Stephen Boyd To: Benson Leung Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, Rob Herring , devicetree@vger.kernel.org, Guenter Roeck , Douglas Anderson , Craig Hesling , Tom Hughes , Alexandru M Stan , Tzung-Bi Shih , Matthias Kaehlcke Subject: [PATCH v3 1/3] dt-bindings: chrome: Add ChromeOS fingerprint binding Date: Thu, 17 Mar 2022 18:54:48 -0700 Message-Id: <20220318015451.2869388-2-swboyd@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220318015451.2869388-1-swboyd@chromium.org> References: <20220318015451.2869388-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a binding to describe the fingerprint processor found on Chromebooks with a fingerprint sensor. Cc: Rob Herring Cc: Cc: Guenter Roeck Cc: Douglas Anderson Cc: Craig Hesling Cc: Tom Hughes Cc: Alexandru M Stan Cc: Tzung-Bi Shih Cc: Matthias Kaehlcke Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson --- .../bindings/chrome/google,cros-ec-fp.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/chrome/google,cros-ec-fp.yaml diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-fp.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-fp.yaml new file mode 100644 index 000000000000..b7fbaaa94d65 --- /dev/null +++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-fp.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/chrome/google,cros-ec-fp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChromeOS Embedded Fingerprint Controller + +description: + Google's ChromeOS embedded fingerprint controller is a device which + implements fingerprint functionality such as unlocking a Chromebook + without typing a password. + +maintainers: + - Tom Hughes + +properties: + compatible: + const: google,cros-ec-fp + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 3000000 + + interrupts: + maxItems: 1 + + reset-gpios: true + boot0-gpios: + maxItems: 1 + description: Assert for bootloader mode. + + vdd-supply: true + +required: + - compatible + - reg + - interrupts + - reset-gpios + - boot0-gpios + - vdd-supply + - spi-max-frequency + +additionalProperties: false + +examples: + - | + #include + #include + spi { + #address-cells = <0x1>; + #size-cells = <0x0>; + ec@0 { + compatible = "google,cros-ec-fp"; + reg = <0>; + interrupt-parent = <&gpio_controller>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <3000000>; + reset-gpios = <&gpio_controller 5 GPIO_ACTIVE_LOW>; + boot0-gpios = <&gpio_controller 10 GPIO_ACTIVE_HIGH>; + vdd-supply = <&pp3300_fp_mcu>; + }; + }; +... From patchwork Fri Mar 18 01:54:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 12784755 Received: from mail-pg1-f171.google.com (mail-pg1-f171.google.com [209.85.215.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D243215AC for ; Fri, 18 Mar 2022 01:54:55 +0000 (UTC) Received: by mail-pg1-f171.google.com with SMTP id c11so4034698pgu.11 for ; Thu, 17 Mar 2022 18:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yclMSQyOdfMOQoKpzUaRMtJg5TrGLXT/don6YL5wL2c=; b=d2lwOh30lYLmGIksygfZa83/YPhubrVDgBVn0fNS04CVQG9Tclhpai24uavY85z+0J Iu7l9uz+mGGWxjO+FK235uTwQZAgNCd88OJaVGQhXiarlj5laEa8IiJWDMiU8wgj4IWG 6YlOzrKY21jKVAnvlEtJ83EZ9wrW3o4esVGL4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yclMSQyOdfMOQoKpzUaRMtJg5TrGLXT/don6YL5wL2c=; b=spebLVgXu2IpmwjUos3Jb/KOXkQb8dTfrD3uDtIbLf+Ybcm5NwM8IcG1EGNadueApD WT6L4CYltBRBg/Yoj7f4fz9r4SRarIDVTg2z1hPtP9sgDqdLoIkjUyij8PMFaoCl8sDB x0geXOq8/TZywXwLXEVXbXt8RaTMYOhsYFv2B+U34NELDPOH9zmcvwOa2w4lSHSNsGYM SxBTGEe4ADEuFgOzAQ3LGdS/AIfu7oNkR/yvIXLKtJQ+7lbkk3b0qSUCE05jE7oTDmF+ KY+nDr7mU/wQUoK1IImXgt2sQ9u5u4MmbxXf2Z10Ubz009BEGr2b/eYFue78rcRaiVwr rDmQ== X-Gm-Message-State: AOAM531hMhJcTcAXKRVVMJ79tpmFFG3gduDNIg3ViGacMT6cy0il7N5b f6A/0fdKLna4fmgVzbuCgS/Trg== X-Google-Smtp-Source: ABdhPJy3Ad1i05NYrMrhjpdEuaAZPN9G/qb30grnL6HPiiVjTdRz0jeLpRhropCPVAl3vnQ+yWwAHg== X-Received: by 2002:a65:4789:0:b0:374:8b11:fb47 with SMTP id e9-20020a654789000000b003748b11fb47mr5909016pgs.325.1647568495413; Thu, 17 Mar 2022 18:54:55 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:201:49cf:7701:359e:b28f]) by smtp.gmail.com with ESMTPSA id u10-20020a056a00124a00b004f783abfa0esm8050201pfi.28.2022.03.17.18.54.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 18:54:55 -0700 (PDT) From: Stephen Boyd To: Benson Leung Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, Guenter Roeck , Douglas Anderson , Craig Hesling , Tom Hughes , Alexandru M Stan , Tzung-Bi Shih , Matthias Kaehlcke Subject: [PATCH v3 2/3] platform/chrome: cros_ec_spi: Match cros-ec-fp compatible Date: Thu, 17 Mar 2022 18:54:49 -0700 Message-Id: <20220318015451.2869388-3-swboyd@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220318015451.2869388-1-swboyd@chromium.org> References: <20220318015451.2869388-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the fingerprint cros-ec compatible and spi_device_id so that we can probe fingerprint devices. Cc: Guenter Roeck Cc: Douglas Anderson Cc: Craig Hesling Cc: Tom Hughes Cc: Alexandru M Stan Cc: Tzung-Bi Shih Reviewed-by: Matthias Kaehlcke Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson --- drivers/platform/chrome/cros_ec_spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrome/cros_ec_spi.c index 14c4046fa04d..d0f9496076d6 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -813,12 +813,14 @@ static SIMPLE_DEV_PM_OPS(cros_ec_spi_pm_ops, cros_ec_spi_suspend, cros_ec_spi_resume); static const struct of_device_id cros_ec_spi_of_match[] = { + { .compatible = "google,cros-ec-fp", }, { .compatible = "google,cros-ec-spi", }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, cros_ec_spi_of_match); static const struct spi_device_id cros_ec_spi_id[] = { + { "cros-ec-fp", 0 }, { "cros-ec-spi", 0 }, { } }; From patchwork Fri Mar 18 01:54:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 12784756 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F111715C0 for ; Fri, 18 Mar 2022 01:54:56 +0000 (UTC) Received: by mail-pj1-f51.google.com with SMTP id mr5-20020a17090b238500b001c67366ae93so4751012pjb.4 for ; Thu, 17 Mar 2022 18:54:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rxw3CHXEYejW4ccJG856QD+F55RYD67woHuYROci7qY=; b=gdTMA0vCi7X9A9ohLapQh8US+e2d60RkEr7Ib9edeaFroKoB6x/9n4A2lU7+WQAyHN RG3T/kFfoEUYbF+516owpmIn1SCozFbWiENSEdpZZy9ic7B3fct2h/MsymuMu6CSprIN vvMEKt/rUdC02qRyHrDTf7YBzfefl9DjJ/0Pc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rxw3CHXEYejW4ccJG856QD+F55RYD67woHuYROci7qY=; b=S8HoFM6cX/1SiE8noVy0eAnAhTwo7gDX5KPgHGMjawpG4LVx7dwVZR3B277KIcCDXB BIjt/YKhNY88txrl6gJxNnEfrsTLC01dqwsreYeasoQi8uYXDxdMQpx326K4IZlXowzc +8flHtn+iW28F+r04VGRykokZEuvE9vu282oV2fxnX8QU+NgRtQEWKuLyeHmQnEmLcGm rCGWCtKakFc2vTYOa7nyl56ArkbHg4t7fA/uvyFL8dltW5Xb5UG/VrpKxFiDH1HHJkCm kkP6vCiDE3Fr0MTNSj5rsN1E7ydRqtbRqcTmGfxDSeLFCmI69kEusrjF9XxVLfGu4Q16 Rg7Q== X-Gm-Message-State: AOAM531sBNted1DEMaHFDXh39A0nXV6an+Xq/80phf5T5I+xgcgbNEM/ 9W3eaq4SM0PExtA6aMtB23VqKA== X-Google-Smtp-Source: ABdhPJzsh0bkMdgCWzUa/NDTDzi6Tr0Yq5+hHOgXzbSg+iFkiCEFp5CxVi6Hfu8LOVgcVvbVf8NmmA== X-Received: by 2002:a17:902:f686:b0:151:d866:f657 with SMTP id l6-20020a170902f68600b00151d866f657mr7708777plg.112.1647568496456; Thu, 17 Mar 2022 18:54:56 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:201:49cf:7701:359e:b28f]) by smtp.gmail.com with ESMTPSA id u10-20020a056a00124a00b004f783abfa0esm8050201pfi.28.2022.03.17.18.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 18:54:56 -0700 (PDT) From: Stephen Boyd To: Benson Leung Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, Guenter Roeck , Douglas Anderson , Craig Hesling , Tom Hughes , Alexandru M Stan , Tzung-Bi Shih , Matthias Kaehlcke Subject: [PATCH v3 3/3] platform/chrome: cros_ec_spi: Boot fingerprint processor during probe Date: Thu, 17 Mar 2022 18:54:50 -0700 Message-Id: <20220318015451.2869388-4-swboyd@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220318015451.2869388-1-swboyd@chromium.org> References: <20220318015451.2869388-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add gpio control to this driver so that the fingerprint device can be booted if the BIOS isn't doing it already. This eases bringup of new hardware as we don't have to wait for the BIOS to be ready, supports kexec where the GPIOs may not be configured by the previous boot stage, and is all around good hygiene because we control GPIOs for this device from the device driver. Cc: Guenter Roeck Cc: Douglas Anderson Cc: Craig Hesling Cc: Tom Hughes Cc: Alexandru M Stan Cc: Tzung-Bi Shih Reviewed-by: Matthias Kaehlcke Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_ec_spi.c | 42 +++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrome/cros_ec_spi.c index d0f9496076d6..13d413a2fe46 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -4,6 +4,7 @@ // Copyright (C) 2012 Google, Inc #include +#include #include #include #include @@ -77,6 +78,8 @@ struct cros_ec_spi { unsigned int start_of_msg_delay; unsigned int end_of_msg_delay; struct kthread_worker *high_pri_worker; + struct gpio_desc *boot0; + struct gpio_desc *reset; }; typedef int (*cros_ec_xfer_fn_t) (struct cros_ec_device *ec_dev, @@ -690,7 +693,7 @@ static int cros_ec_cmd_xfer_spi(struct cros_ec_device *ec_dev, return cros_ec_xfer_high_pri(ec_dev, ec_msg, do_cros_ec_cmd_xfer_spi); } -static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device *dev) +static int cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device *dev) { struct device_node *np = dev->of_node; u32 val; @@ -703,6 +706,37 @@ static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device *dev) ret = of_property_read_u32(np, "google,cros-ec-spi-msg-delay", &val); if (!ret) ec_spi->end_of_msg_delay = val; + + if (!of_device_is_compatible(np, "google,cros-ec-fp")) + return 0; + + ec_spi->boot0 = devm_gpiod_get(dev, "boot0", 0); + if (IS_ERR(ec_spi->boot0)) + return PTR_ERR(ec_spi->boot0); + + ec_spi->reset = devm_gpiod_get(dev, "reset", 0); + if (IS_ERR(ec_spi->reset)) + return PTR_ERR(ec_spi->reset); + + /* + * Take the FPMCU out of reset and wait for it to boot if it's in + * bootloader mode or held in reset. This isn't the normal flow because + * typically the BIOS has already powered on the device to avoid the + * multi-second delay waiting for the FPMCU to boot and be responsive. + */ + if (gpiod_get_value(ec_spi->boot0) || gpiod_get_value(ec_spi->reset)) { + /* Boot0 is sampled on reset deassertion */ + gpiod_set_value(ec_spi->boot0, 0); + gpiod_set_value(ec_spi->reset, 1); + usleep_range(1000, 2000); + gpiod_set_value(ec_spi->reset, 0); + + /* Wait for boot; there isn't a "boot done" signal */ + dev_info(dev, "Waiting for FPMCU to boot\n"); + msleep(2000); + } + + return 0; } static void cros_ec_spi_high_pri_release(void *worker) @@ -754,8 +788,10 @@ static int cros_ec_spi_probe(struct spi_device *spi) if (!ec_dev) return -ENOMEM; - /* Check for any DT properties */ - cros_ec_spi_dt_probe(ec_spi, dev); + /* Check for any DT properties and boot FPMCU if applicable */ + err = cros_ec_spi_dt_probe(ec_spi, dev); + if (err) + return err; spi_set_drvdata(spi, ec_dev); ec_dev->dev = dev;