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Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 01/12] interval-tree: Add a utility to iterate over spans in an interval tree Date: Fri, 18 Mar 2022 14:27:26 -0300 Message-Id: <1-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR15CA0020.namprd15.prod.outlook.com (2603:10b6:208:1b4::33) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4e5850a0-9132-4058-0e71-08da0904999a X-MS-TrafficTypeDiagnostic: MN2PR12MB3630:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZlhYNXXqJcp5v0+IE+f6TACfLw5or5LfYW0h5u8Ul1qcj0uGxVv2UTqC47/72lwYv1rvrHg3+NzuqN8lGLvvzZghS4Ah9VIPMWGkzInAUKV6kD6jQf0E22zn+A69KLyBXOUXqZBO8CjBv6TLy3ZqxugYg1l55a53a7SvL3BzFLGAQvYnvP+YbtqX4H2kvfM3B6uAy6JXDqHYVOeCDaWeRAapOba91P0IIyIfploIVon0f6JJGvPBEiAi6Z2jQ+ZCkg5K7U9AdcsAcUqgM/cOk9SUpQEfx/7FPezKzUb8vTC9GcIfnq6lwwwVYCTmgfk+Sbk7a/LLNYnSb8zQpsPOPpW06CUUyEIlI35BkcI86AsJvrFeUE27UlVyRlUCpiw+rIXg3eyTDwxorNIGHasdtQwoKT8Zc8ulv6lNEurwkBMSwoevV/sRXK8NTfZFUq+RV8/5WgXUhFjK4D+C2sDl9o4xaA3fIA2cq4HZclAXeQuf7ZVws1Qlrn+1hENaxZVmwmmiZ2znH8TKI1jvyNb6tvePHyrJYk1lk56KNh5cOVRDjO2C/ZTq7L54qDYkbXqO3qIcwzdDFDJy6kRn148/frECsCWTi3QGnrkHH+VlqcwrNc3r3G5+oP5kupy0zQuXqXtzApGTh9FZD2c5I6eWzQF3S4s8YRVwQnA+Gy7bz+Hf0DkeWQGik/jh2vUR+jH7UpXqX/voUnOi6PVSY6o73w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(26005)(508600001)(186003)(6666004)(8676002)(4326008)(8936002)(6486002)(83380400001)(7416002)(66946007)(5660300002)(66476007)(66556008)(6512007)(109986005)(54906003)(2906002)(316002)(38100700002)(6506007)(2616005)(36756003)(86362001)(4216001)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qIA4mMqPP30tbSWtlBzHe8M3xfTdr39iBTabjbHngzU13gKjf7nsDt6cl/gwBzVPjIstL7GY4XnQknvliImE3qt/EVv00FhgMXlvHpPlTcnBogsfhwgn32WQOfZUkcNLBn0Nu1iT2u8ZU50R01AUE0ztpJrDIpEVPfuro18J9exdQedJsCXTCSg/uyjysdZTQreddZplu/bhMxozc5vwgjwEcbqTrs6LELcnJ0l/qBCBRDnOQe0gbG5BPJf4ZWE9c2tf4rrGjxsQ5ei6gI0aiWQMPeH6HEdylhcnkJiQ6UYp4MSeGJnVEjOcWdPQj+FzHRRza8EAp9EMcM5TJIOpE/ZPftsw71xIVy0V2DTFWHGY85l11sr1maZ2N83cF1qI0MbLaajGrzvdH+RNJzvHgRFP6dDnaimR6nHzthPxiCi8IdNITSrehvJVP31K8Pggyvgw7fglxjVEP/57l7mWcobIgBAnvroTMID+NeHGumoXKjNvqhQ1OuDOvaIKBEjeLC38gj0BviHzdGH5rcT4bRXBeAGfUQ2Ofbl5+r2hAxFHfHTFiBjPee/Xd8Hh0/y2sHMG6eb3pSPO+2QydZlF411LJ2odkpj1FZDITLNbwylQk9lsgc88m9y80K6NrCKJeq30wbobBJIBIFlS7n/V+lF+gacq77pM2QrgFOPOHOssTvj0tSxEb5dqJPkMNe3/pAXJYxfzniULZFlFFZiwY5zmtcTDPqTnkOT/JnT4fdtT0rM902Iu84Um1fyj0XA9Hn1NEe0fUYyvv45o0rdiSeILObKfOUNO1dZdylecbI6Z8qXWZOedKFKEEpEgL3L8X3TzWrn8s1nHOTrA6o0/khfaAXQAwNuWFBC77G1pHzKZUiQwmpLsYsG6xyV5O//xry0tW/ctc5rhAseSlM6fInBrjsiri9D+j/O0jPbnn57MvoO5mxeWkcXv9DDrVwLPo5j2rAeTdHGJ3e14Mm+BKVKr42GefwyuNPGyVQLrrjqKzT5GrYX2DkNXjYoJUXz6v+5z5hecv8zHzqlBwblbKhvNG7VZoSyTPcZorqNR9Wedk+LycWYoAUOfJ5VGqViD9nXdUqAP0+nRLhZC7Uxc07bfXQVysgTYO+KDkGgrsoW/8aMozw6uP18OGVFtm3G2EAKohjWzbJa3N73RP+ro8JOM5Q9kO+BMLtUUtJOElXybdyTmeLllbp+4yoY4SXGxTizdzy5fvcuHWiV5jV1l0JCLTkOFQS0fzgoX7djEs62eAeZ5wT3nq17QcDfgkzQ6aWf2ugHk/Rgc+V/WK3tUEToFXB17RCBaq5dQl+BvxdA/w/zuPSCq+E+n37zSxT6GddrlW+bL7rTaEiq8jQOB+rBEMz2LL2JuV2aOuYqgviD7t54Z9BfZPmg6/BTR9olXfcP3XLMM5voNkEgWgWZ0DYtku7TMs8CeX/ovWiS095pNl3KqCu7+bFbvwyWqtVJR X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e5850a0-9132-4058-0e71-08da0904999a X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:38.9594 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: P4y3CmgBVqt+t2aZcv2+K1tbHeS1pFAJkcSrJoeaMa+1uDBqOqHqkKxeMNba2TpK X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3630 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The span iterator travels over the indexes of the interval_tree, not the nodes, and classifies spans of indexes as either 'used' or 'hole'. 'used' spans are fully covered by nodes in the tree and 'hole' spans have no node intersecting the span. This is done greedily such that spans are maximally sized and every iteration step switches between used/hole. As an example a trivial allocator can be written as: for (interval_tree_span_iter_first(&span, itree, 0, ULONG_MAX); !interval_tree_span_iter_done(&span); interval_tree_span_iter_next(&span)) if (span.is_hole && span.last_hole - span.start_hole >= allocation_size - 1) return span.start_hole; With all the tricky boundary conditions handled by the library code. The following iommufd patches have several algorithms for two of its overlapping node interval trees that are significantly simplified with this kind of iteration primitive. As it seems generally useful, put it into lib/. Signed-off-by: Jason Gunthorpe --- include/linux/interval_tree.h | 41 +++++++++++++++ lib/interval_tree.c | 98 +++++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+) diff --git a/include/linux/interval_tree.h b/include/linux/interval_tree.h index 288c26f50732d7..3817af0fa54028 100644 --- a/include/linux/interval_tree.h +++ b/include/linux/interval_tree.h @@ -27,4 +27,45 @@ extern struct interval_tree_node * interval_tree_iter_next(struct interval_tree_node *node, unsigned long start, unsigned long last); +/* + * This iterator travels over spans in an interval tree. It does not return + * nodes but classifies each span as either a hole, where no nodes intersect, or + * a used, which is fully covered by nodes. Each iteration step toggles between + * hole and used until the entire range is covered. The returned spans always + * fully cover the requested range. + * + * The iterator is greedy, it always returns the largest hole or used possible, + * consolidating all consecutive nodes. + * + * Only is_hole, start_hole/used and last_hole/used are part of the external + * interface. + */ +struct interval_tree_span_iter { + struct interval_tree_node *nodes[2]; + unsigned long first_index; + unsigned long last_index; + union { + unsigned long start_hole; + unsigned long start_used; + }; + union { + unsigned long last_hole; + unsigned long last_used; + }; + /* 0 == used, 1 == is_hole, -1 == done iteration */ + int is_hole; +}; + +void interval_tree_span_iter_first(struct interval_tree_span_iter *state, + struct rb_root_cached *itree, + unsigned long first_index, + unsigned long last_index); +void interval_tree_span_iter_next(struct interval_tree_span_iter *state); + +static inline bool +interval_tree_span_iter_done(struct interval_tree_span_iter *state) +{ + return state->is_hole == -1; +} + #endif /* _LINUX_INTERVAL_TREE_H */ diff --git a/lib/interval_tree.c b/lib/interval_tree.c index 593ce56ece5050..5dff0da020923f 100644 --- a/lib/interval_tree.c +++ b/lib/interval_tree.c @@ -15,3 +15,101 @@ EXPORT_SYMBOL_GPL(interval_tree_insert); EXPORT_SYMBOL_GPL(interval_tree_remove); EXPORT_SYMBOL_GPL(interval_tree_iter_first); EXPORT_SYMBOL_GPL(interval_tree_iter_next); + +static void +interval_tree_span_iter_next_gap(struct interval_tree_span_iter *state) +{ + struct interval_tree_node *cur = state->nodes[1]; + + /* + * Roll nodes[1] into nodes[0] by advancing nodes[1] to the end of a + * contiguous span of nodes. This makes nodes[0]->last the end of that + * contiguous span of valid indexes that started at the original + * nodes[1]->start. nodes[1] is now the next node and a hole is between + * nodes[0] and [1]. + */ + state->nodes[0] = cur; + do { + if (cur->last > state->nodes[0]->last) + state->nodes[0] = cur; + cur = interval_tree_iter_next(cur, state->first_index, + state->last_index); + } while (cur && (state->nodes[0]->last >= cur->start || + state->nodes[0]->last + 1 == cur->start)); + state->nodes[1] = cur; +} + +void interval_tree_span_iter_first(struct interval_tree_span_iter *iter, + struct rb_root_cached *itree, + unsigned long first_index, + unsigned long last_index) +{ + iter->first_index = first_index; + iter->last_index = last_index; + iter->nodes[0] = NULL; + iter->nodes[1] = + interval_tree_iter_first(itree, first_index, last_index); + if (!iter->nodes[1]) { + /* No nodes intersect the span, whole span is hole */ + iter->start_hole = first_index; + iter->last_hole = last_index; + iter->is_hole = 1; + return; + } + if (iter->nodes[1]->start > first_index) { + /* Leading hole on first iteration */ + iter->start_hole = first_index; + iter->last_hole = iter->nodes[1]->start - 1; + iter->is_hole = 1; + interval_tree_span_iter_next_gap(iter); + return; + } + + /* Starting inside a used */ + iter->start_used = first_index; + iter->is_hole = 0; + interval_tree_span_iter_next_gap(iter); + iter->last_used = iter->nodes[0]->last; + if (iter->last_used >= last_index) { + iter->last_used = last_index; + iter->nodes[0] = NULL; + iter->nodes[1] = NULL; + } +} +EXPORT_SYMBOL_GPL(interval_tree_span_iter_first); + +void interval_tree_span_iter_next(struct interval_tree_span_iter *iter) +{ + if (!iter->nodes[0] && !iter->nodes[1]) { + iter->is_hole = -1; + return; + } + + if (iter->is_hole) { + iter->start_used = iter->last_hole + 1; + iter->last_used = iter->nodes[0]->last; + if (iter->last_used >= iter->last_index) { + iter->last_used = iter->last_index; + iter->nodes[0] = NULL; + iter->nodes[1] = NULL; + } + iter->is_hole = 0; + return; + } + + if (!iter->nodes[1]) { + /* Trailing hole */ + iter->start_hole = iter->nodes[0]->last + 1; + iter->last_hole = iter->last_index; + iter->nodes[0] = NULL; + iter->is_hole = 1; + return; + } + + /* must have both nodes[0] and [1], interior hole */ + iter->start_hole = iter->nodes[0]->last + 1; + iter->last_hole = iter->nodes[1]->start - 1; + iter->is_hole = 1; + interval_tree_span_iter_next_gap(iter); +} +EXPORT_SYMBOL_GPL(interval_tree_span_iter_next); From patchwork Fri Mar 18 17:27:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50377C43217 for ; Fri, 18 Mar 2022 17:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239621AbiCRR3F (ORCPT ); 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Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 02/12] iommufd: Overview documentation Date: Fri, 18 Mar 2022 14:27:27 -0300 Message-Id: <2-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: BL1PR13CA0220.namprd13.prod.outlook.com (2603:10b6:208:2bf::15) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ffba083b-65ee-46d6-d2e7-08da0904999e X-MS-TrafficTypeDiagnostic: MN2PR12MB3630:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xD81PL0OgG+cQhJXaXdLL3lXI0jeQjFHJ5oAppBafE+nPM5IPKNQf1QYPKymuFcXQhNKEClqkAsIoJmEDq5ig6okhX90WTJsAdw1yBwfzv1LJfjIyRRwXb+aXrnEqip4BJ8jaPHEp9nRrsCI8DK6Hwi6Wwj3BOVWdZTwfjkYRSi6buaMwvJowpoAZ9cvxYZDPEFuSyZF5pT/CM6Z2tmsEm2gs0iFDL7ch9FlezpLZ3THC6u0ZhJej2nnkbGKL5L6dMmT31DjWF1EP4hnhqznXXliioo/RUDPwG1/tOW9TyN8uwGyC5gDHf0kRiDxauJHguTpY6L5YpZTuV7kyhE6wrRRjhBrQpQkQuaWvOYoSb5ClfAYuets33m/DmpJf9BP4315GOXop0u02ebVttrcejUfdQ3F/tmcIWpSY2i6KxGnk2cyu9AYK1epCUPIwk/PI8iBdidFiJ3qdV2rmFYkHq6Rj156XNyG3pFQ+TB3VFCRyYvMrpY8B8BroGkqMaaZgUtlQpck2q8gRPy/xB7a3qk+u9bV56vQprtBWPc2kJMAi4bmQC1Zb7pzlmuajrykz+DKvzp3/H95VQaWFO5tTVS2BQoehgBU3QOafdf/Kntw/GD3rWub1YjHmOEuaEBXBbZio7Rsqj3x3Ku2V13eVPrJc0fz9ftq+37QYDoWQmeFfdeSyJ+Uy3oT7WI6/szrrakBBNBZzlzg0zV5alnShw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(26005)(508600001)(186003)(6666004)(8676002)(4326008)(8936002)(6486002)(83380400001)(7416002)(66946007)(5660300002)(66476007)(66556008)(6512007)(109986005)(54906003)(2906002)(316002)(38100700002)(6506007)(2616005)(36756003)(86362001)(4216001)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: faWJOWldlKxztok7y4MjKg4fSyyf+vf/fPqlkiTq5PK6JBteeWoGKMkzryHWT0bX7MaE36qiNe3KeREHkiuf01YPezzaBRDPUrov/NBxYvnUTqb3fiWvgKyuJuAEY4zcoJZQPUQiXLn5+V34jZ3JT1paDhav6M1MRUzh71ddD3JgOIOW6uKT2JQq/7/B0CUSP4ti5Bc8RxXRv8Ru9/jQfpAmE/5Ia4Oa7LOLkPc1LvsqNIm/95aivST4lyGu8Bw3Pr6k6HbORrwuX4enWaOm98olDpGYN8CH/cNYLCeV8ZrjOGhHHmeECNvZytTOiDr0/zNwd0qULeiY4oohOiagIPH51/vAPW5fsPwUazs5FcQnMh+xMGBJubNaytinfY4CCd3FbnPAEfoaauxjBzwLdlZRn9GA0CffsYO5cx1O86YCCiOhBK7GYoejMD8ZgRfeVV1FQSRx6RqPu+QGwVOYMJpLZmwQ6RS9vp+9PGQ3c7MJthVZ3A2QHhBEAn2vHwx//0cVHQQ2TeVAXgC7tr3bXnUXQypVp7lWem/rF0AxojjHu0RJDRzPBaMjtEbdf9u8bQd6+E2SzFcRwgDmguGXCFukubyn6NUhale+KKCxKH1InIr7jlZltK+Plu8VJb6AsyfxutDRofV3kKuq7Wp2r0lvKPXGoOlEgdMcMM8tMFkfhDVteqv9VX2/q0915tgsyNbJWyhYY0pz/tObFWY/Ozve7X/9yKsjMMiF5ze9sjF+8I9V7P/WU1+RwPptWRepq2kdikSdHhyyvVsN83ARyyd3J3EAVkL9ji1lfnmAlATcu1C+rK7Qz7bvGf6jWM96jAp3jmgvjcHwdU7VcXViNZ7i6VGmcuf6g/AtB7oEzzHm+FBz++wwcBghQUklpD0T4dJhElduOUyBPCMAx4JyKsc2T8SBqFnKvlPmvcvFVeUqZANEn6vmfCS+4xrSbUFET9FSRhnSs9NtHywq2Mz566jTqmBiss8TOpb4xKJaNbAZRSXjv9doVmkWNRxMxpNsuW/t0aKz9qT+vQpu8JNgELHtUuFr1cUYJIijtu/IBYCxMWfEPcbOZ8DQy4IPBkrvP+GEUXDJpZ5xMjb0sEU2HJaDhzGQooreTycpu0V0n4Jqtv62MhhQm4UorGoSKYkC9B1mA8hVUKXXVVgIWqErZCEc7SOTEl3sLuMKXx0+znXugcknhW87MT9MUCGZOLV+NBV4rwyoevH1KELZh1TIXKof3VE1fmIdJBp+4Kfa3lLgQFuwG1fUDjOoghtQ0cx2KMFNU4cW51VdY3Bc3VRlP0SgjhYzmmzG9Dy9thLR6WZZxeYIMSfOvWoKJXnAt9LtDeoeOFIABJQlzb0p1rxKF8VlGugzw3GOwZZUzXWTd/AqrxJVkRu13JDAxFJuVFP9KB4f3+dw9ozs22oJ3FJgagCowlffpeMezhRhTLgMLYH9wWBzLvfHGzajuor7Q/xG X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ffba083b-65ee-46d6-d2e7-08da0904999e X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:39.0063 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: v3eMAEAVu/sphERuecjPjOxKQHYM5jnxPZgJBQ/5vJt82pKWWTAf0Tgkq9uCOtp1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3630 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Kevin Tian Add iommufd to the documentation tree. Signed-off-by: Kevin Tian Signed-off-by: Jason Gunthorpe --- Documentation/userspace-api/index.rst | 1 + Documentation/userspace-api/iommufd.rst | 224 ++++++++++++++++++++++++ 2 files changed, 225 insertions(+) create mode 100644 Documentation/userspace-api/iommufd.rst diff --git a/Documentation/userspace-api/index.rst b/Documentation/userspace-api/index.rst index a61eac0c73f825..3815f013e4aebd 100644 --- a/Documentation/userspace-api/index.rst +++ b/Documentation/userspace-api/index.rst @@ -25,6 +25,7 @@ place where this information is gathered. ebpf/index ioctl/index iommu + iommufd media/index sysfs-platform_profile vduse diff --git a/Documentation/userspace-api/iommufd.rst b/Documentation/userspace-api/iommufd.rst new file mode 100644 index 00000000000000..38035b3822fd23 --- /dev/null +++ b/Documentation/userspace-api/iommufd.rst @@ -0,0 +1,224 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +======= +IOMMUFD +======= + +:Author: Jason Gunthorpe +:Author: Kevin Tian + +Overview +======== + +IOMMUFD is the user API to control the IOMMU subsystem as it relates to managing +IO page tables that point at user space memory. It intends to be general and +consumable by any driver that wants to DMA to userspace. Those drivers are +expected to deprecate any proprietary IOMMU logic, if existing (e.g. +vfio_iommu_type1.c). + +At minimum iommufd provides a universal support of managing I/O address spaces +and I/O page tables for all IOMMUs, with room in the design to add non-generic +features to cater to specific hardware functionality. + +In this context the capital letter (IOMMUFD) refers to the subsystem while the +small letter (iommufd) refers to the file descriptors created via /dev/iommu to +run the user API over. + +Key Concepts +============ + +User Visible Objects +-------------------- + +Following IOMMUFD objects are exposed to userspace: + +- IOMMUFD_OBJ_IOAS, representing an I/O address space (IOAS) allowing map/unmap + of user space memory into ranges of I/O Virtual Address (IOVA). + + The IOAS is a functional replacement for the VFIO container, and like the VFIO + container copies its IOVA map to a list of iommu_domains held within it. + +- IOMMUFD_OBJ_DEVICE, representing a device that is bound to iommufd by an + external driver. + +- IOMMUFD_OBJ_HW_PAGETABLE, wrapping an actual hardware I/O page table (i.e. a + single struct iommu_domain) managed by the iommu driver. + + The IOAS has a list of HW_PAGETABLES that share the same IOVA mapping and the + IOAS will synchronize its mapping with each member HW_PAGETABLE. + +All user-visible objects are destroyed via the IOMMU_DESTROY uAPI. + +Linkage between user-visible objects and external kernel datastructures are +reflected by dotted line arrows below, with numbers referring to certain +operations creating the objects and links:: + + _________________________________________________________ + | iommufd | + | [1] | + | _________________ | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | | + | | | [3] [2] | + | | | ____________ __________ | + | | IOAS |<--| |<------| | | + | | | |HW_PAGETABLE| | DEVICE | | + | | | |____________| |__________| | + | | | | | | + | | | | | | + | | | | | | + | | | | | | + | | | | | | + | |_________________| | | | + | | | | | + |_________|___________________|___________________|_______| + | | | + | _____v______ _______v_____ + | PFN storage | | | | + |------------>|iommu_domain| |struct device| + |____________| |_____________| + +1. IOMMUFD_OBJ_IOAS is created via the IOMMU_IOAS_ALLOC uAPI. One iommufd can + hold multiple IOAS objects. IOAS is the most generic object and does not + expose interfaces that are specific to single IOMMU drivers. All operations + on the IOAS must operate equally on each of the iommu_domains that are inside + it. + +2. IOMMUFD_OBJ_DEVICE is created when an external driver calls the IOMMUFD kAPI + to bind a device to an iommufd. The external driver is expected to implement + proper uAPI for userspace to initiate the binding operation. Successful + completion of this operation establishes the desired DMA ownership over the + device. The external driver must set driver_managed_dma flag and must not + touch the device until this operation succeeds. + +3. IOMMUFD_OBJ_HW_PAGETABLE is created when an external driver calls the IOMMUFD + kAPI to attach a bound device to an IOAS. Similarly the external driver uAPI + allows userspace to initiate the attaching operation. If a compatible + pagetable already exists then it is reused for the attachment. Otherwise a + new pagetable object (and a new iommu_domain) is created. Successful + completion of this operation sets up the linkages among an IOAS, a device and + an iommu_domain. Once this completes the device could do DMA. + + Every iommu_domain inside the IOAS is also represented to userspace as a + HW_PAGETABLE object. + + NOTE: Future additions to IOMMUFD will provide an API to create and + manipulate the HW_PAGETABLE directly. + +One device can only bind to one iommufd (due to DMA ownership claim) and attach +to at most one IOAS object (no support of PASID yet). + +Currently only PCI device is allowed. + +Kernel Datastructure +-------------------- + +User visible objects are backed by following datastructures: + +- iommufd_ioas for IOMMUFD_OBJ_IOAS. +- iommufd_device for IOMMUFD_OBJ_DEVICE. +- iommufd_hw_pagetable for IOMMUFD_OBJ_HW_PAGETABLE. + +Several terminologies when looking at these datastructures: + +- Automatic domain, referring to an iommu domain created automatically when + attaching a device to an IOAS object. This is compatible to the semantics of + VFIO type1. + +- Manual domain, referring to an iommu domain designated by the user as the + target pagetable to be attached to by a device. Though currently no user API + for userspace to directly create such domain, the datastructure and algorithms + are ready for that usage. + +- In-kernel user, referring to something like a VFIO mdev that is accessing the + IOAS and using a 'struct page \*' for CPU based access. Such users require an + isolation granularity smaller than what an iommu domain can afford. They must + manually enforce the IOAS constraints on DMA buffers before those buffers can + be accessed by mdev. Though no kernel API for an external driver to bind a + mdev, the datastructure and algorithms are ready for such usage. + +iommufd_ioas serves as the metadata datastructure to manage how IOVA ranges are +mapped to memory pages, composed of: + +- struct io_pagetable holding the IOVA map +- struct iopt_areas representing populated portions of IOVA +- struct iopt_pages representing the storage of PFNs +- struct iommu_domain representing the IO page table in the IOMMU +- struct iopt_pages_user representing in-kernel users of PFNs +- struct xarray pinned_pfns holding a list of pages pinned by + in-kernel Users + +The iopt_pages is the center of the storage and motion of PFNs. Each iopt_pages +represents a logical linear array of full PFNs. PFNs are stored in a tiered +scheme: + + 1) iopt_pages::pinned_pfns xarray + 2) An iommu_domain + 3) The origin of the PFNs, i.e. the userspace pointer + +PFN have to be copied between all combinations of tiers, depending on the +configuration (i.e. attached domains and in-kernel users). + +An io_pagetable is composed of iopt_areas pointing at iopt_pages, along with a +list of iommu_domains that mirror the IOVA to PFN map. + +Multiple io_pagetable's, through their iopt_area's, can share a single +iopt_pages which avoids multi-pinning and double accounting of page consumption. + +iommufd_ioas is sharable between subsystems, e.g. VFIO and VDPA, as long as +devices managed by different subsystems are bound to a same iommufd. + +IOMMUFD User API +================ + +.. kernel-doc:: include/uapi/linux/iommufd.h + +IOMMUFD Kernel API +================== + +The IOMMUFD kAPI is device-centric with group-related tricks managed behind the +scene. This allows the external driver calling such kAPI to implement a simple +device-centric uAPI for connecting its device to an iommufd, instead of +explicitly imposing the group semantics in its uAPI (as VFIO does). + +.. kernel-doc:: drivers/iommu/iommufd/device.c + :export: + +VFIO and IOMMUFD +---------------- + +Connecting VFIO device to iommufd can be done in two approaches. + +First is a VFIO compatible way by directly implementing the /dev/vfio/vfio +container IOCTLs by mapping them into io_pagetable operations. Doing so allows +the use of iommufd in legacy VFIO applications by symlinking /dev/vfio/vfio to +/dev/iommufd or extending VFIO to SET_CONTAINER using an iommufd instead of a +container fd. + +The second approach directly extends VFIO to support a new set of device-centric +user API based on aforementioned IOMMUFD kernel API. It requires userspace +change but better matches the IOMMUFD API semantics and easier to support new +iommufd features when comparing it to the first approach. + +Currently both approaches are still work-in-progress. + +There are still a few gaps to be resolved to catch up with VFIO type1, as +documented in iommufd_vfio_check_extension(). + +Future TODOs +============ + +Currently IOMMUFD supports only kernel-managed I/O page table, similar to VFIO +type1. New features on the radar include: + + - Binding iommu_domain's to PASID/SSID + - Userspace page tables, for ARM, x86 and S390 + - Kernel bypass'd invalidation of user page tables + - Re-use of the KVM page table in the IOMMU + - Dirty page tracking in the IOMMU + - Runtime Increase/Decrease of IOPTE size + - PRI support with faults resolved in userspace From patchwork Fri Mar 18 17:27:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D3D7C433F5 for ; Fri, 18 Mar 2022 17:27:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239646AbiCRR3O (ORCPT ); Fri, 18 Mar 2022 13:29:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239640AbiCRR3N (ORCPT ); Fri, 18 Mar 2022 13:29:13 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2790C393E0 for ; Fri, 18 Mar 2022 10:27:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GMpQe1SSTGq/Q62l6FS4zaLZs6j3GEQd6AzbEepu1m39nBEIgX4gBTaKCke7z6quLs5iAY6ZVfC83LVv7zj9Ord+ivqLQ3zPqlbp8lvWOt1e8DIRJfahlNnTmfOJj/W3QwfmyJYrWDEpsv9VKSMyf+3zd/41/h9fkivhWHUYkBNq6gHP8BdnR3lpLBQO6m6egaaSmVxUo5KsA8t0MXJBPn3QGpc5jOit0b2T3z5hbNH+RGqKH8kSRbyZxAZ6t7E47rnwoG9PWcAWsSD89sDTrC8jpfdF0kr3ENkdRx5wj7u/vvo4ugSjPzBF/8PBUbwz67UljT+vaFarUrVgNu93ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ONv+0KDNreWAYJWs2MpSokXFJsmA3GE+3NAAK8P/NSE=; b=HDqimjuQqkQ8HkAzp/0Qm3dcsi2+djcBlQbKELYJuLxPucxxWomox+Q07RUm3SZSFisPHRK3xSSPWiXWtdmkDyLvlVD133bkpTgQ8ybT4QUCYNHjgDXfy7OXK63CHYzFsVPXRizq2jZM6pwKFEfBfAbHupf66BjULsFrFFFIclg+FM6zhpydM4S6jVWiGF8Hi5RVQUtu5cgTz5fgoOwp/tAFm2RQfFVgdjMK4XUl7Ux13hdXuieqqZ1pHf7NLbD5NjFc0LVx8XZSerihCKRNRSxix3nVZqH59Y1SJ858acBhe4F5F0jqLHXx6HJ+VOGSbQlsLs/Hg2CoOmxkftonqQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ONv+0KDNreWAYJWs2MpSokXFJsmA3GE+3NAAK8P/NSE=; b=reJcZVk6vS7fiQT495EK/mxVdI5vga8ee7tqukDds28L2pH3U8ZtgTDXr6SCPyf3sf8ReTgkfBNQXOFUztxb3H+8QMdn0ww45jOCXKvGiT3CdyAN/N3kgTWcSLD9/YvinpSVqb27xp9ZCA3LPprdKTi814x8RQVgAa4kJpBhV0WtBnUUE8hMPKNDD7qwErVMBa6LxQpJvvsvaJybHTw5s+A/moFTsaJ/LNJApZfSwCcrMSrdHbzY+1hEJsSEa0o5lPWrYYqKfHpIZZOqB2ylYoBz8YzRmevqpcUZWe7hCdVus3TWch3rGBGJK4+UYerCkTDeA2d4A5pUiZhObrzVoA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by MN2PR12MB3951.namprd12.prod.outlook.com (2603:10b6:208:16b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.14; Fri, 18 Mar 2022 17:27:45 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c%5]) with mapi id 15.20.5081.018; Fri, 18 Mar 2022 17:27:45 +0000 From: Jason Gunthorpe Cc: Alex Williamson , Lu Baolu , Chaitanya Kulkarni , Cornelia Huck , Daniel Jordan , David Gibson , Eric Auger , iommu@lists.linux-foundation.org, Jason Wang , Jean-Philippe Brucker , Joao Martins , Kevin Tian , kvm@vger.kernel.org, Matthew Rosato , "Michael S. Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 03/12] iommufd: File descriptor, context, kconfig and makefiles Date: Fri, 18 Mar 2022 14:27:28 -0300 Message-Id: <3-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR15CA0031.namprd15.prod.outlook.com (2603:10b6:208:1b4::44) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6eec94b0-70df-49d1-57fa-08da09049aea X-MS-TrafficTypeDiagnostic: MN2PR12MB3951:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fEt78cwZHPOveK7VbanxSK9HS20IJ4U6xPsLLlrIlrC8/8k5dZI+RsjLsuwpgDS87BrDXX3ast2rd1mV1cTPfQdrV0pkeMvHF5JVLjiqhSXicL2vz19RAzUcXBAOdn2EohJbfGcaGwRupch+XXk3qkn/fuMAMOXS5hofmasQZJBEVLP5A2tSEI/6dJqQrRBhpibKQ8k8mK0H0WaqKWQVi9Vo3nLsj3nrZIU13Tg7pqCSOs144DPNM3PRIyURX0YW8VAR5P/XyvF0eTOBcUsCiCSKCFEg23qWrXvOGFmAvmOu1Cuu+NiQN+agbxU3OJbGAPjSxhKeBrwYnALk6HQAoweE8TodbJe0xZ1tYn3+izh9xyMzQcKJKl+VzyAH+k+Gx+RRLMaTAbUvKjqB7+2fJtnvMOIsSK5KP/OHltF5r9EwWCdL7dzyROlRqK6Q0E15WRMwOEzYp2F/Gz5EjLX5NcWu6lI4sRILF54zv4+6PL0QUDIzK0cxKhntoqZR0niSDB+2mnZTLfhDA5zmrzUQQaB+4ao2RlxXj3+nrN1p8nSg/wekKAzbYVVJYD9z8KLmjHqaCwvh1S6WDQWuJ0cfj+CXVx828N/5MYmVrMT15VmAqqfi4MItssuVcvUfk1izJzRh7V6YcRgwVllhm/aT29YrroOqETndCb4mrg1a7r2/qjq25tYTRWftLF9m6FDqSU03L4hCFvFW2qrbkWbF6g== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(30864003)(83380400001)(7416002)(4326008)(2906002)(86362001)(508600001)(8676002)(6512007)(6506007)(6666004)(5660300002)(8936002)(109986005)(66946007)(26005)(66476007)(186003)(316002)(66556008)(2616005)(36756003)(38100700002)(6486002)(54906003)(4216001)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LhbmqTielRnc9g2VgyvRyIZH6g7g7a29nWCM2y5SCkqDe0ol9BIG17A8Dlr8o4HBmEU6rcwIR004CUcdwAkwgxc0a0D0phNG92hQVAndExHlXRdMmqQpq5KR/0d1M63f1iOzq9pn6aDKlFGhvAeNkeXRr+iaLHV5vGnfOG2jDgZ7YXcJ84zKevIKflr5d8g4n1f5wWeyESB56dYzf5Q+60pWoFOt3kJqGuGD+aPULlTvcJqnBPmvsljoVtuwPuFRVaRuw1b+PhvCdnMGex/8OukoblqGrKsE/L8JiA9dPBIVUg3lLB8uBu4Xacr2nzRzO219C7fzmGWEP9DsMZ45ObJaQA3LG3BD4TgLSDxHhG1xbTzAlskOS8ZhKxaO2PKGfgFQgT/0NW7177mZ66jL4TkhKw2Fks5M5h0hcFiwsPakCs+ZKDfu2/a+p5YFtfmcaYdPYAE8KywP4xPcC5LxbTOQaCVTVuSTAJvdL5I2/1j41VdRKJ0WpgKGEL0W6daqV1da574D4iCgPi06UXLeZkPzxIAM4PxhApOXBsWZOh54VmDFdHHyuVPGZ7Yw6hDMR7uv6byRTS1+gveKeqzl8u/+rMf7FU3Xmc2SwYMJHCMwGhfVWvwrXQP67LBlnFFo4+QQgpqBz1jGqoC/s0B/ABhRXqiVqfLYWMTQCD2h+iot/HWyt6IV5BBGSX6dudA1vj+8uFzcD1ndBJZADCZTwshf/vYGLglw/rMkKjl1aSER0lk4CSGSjUcjBZPlbVSwM+nFtB3bAoas5dTCOMXdIvT91kM5EMsYSawUFsNkY5v2616DW/5PFAlZ0y0ixmCFN0QA67QPMCa2aLmVaIJhhJtMX5L2v50Bfj+PaUn1SUUfpkDx0rq60InOK0GXH4v8QArrMIuy3LyzqQsM52q/PluQsFw+bFtpHxWTgdeBw4kAcDJCWHUN9FaaxKFf+zoi3D2g0v3f51SP4EEpXfB/t2PyVHyeAxdz+0Ct9q+KdXuCTXfD08LobM3xduJnfxA2pfLHwcHq+ruvye+Njj6YLu1iTyFNmENW/8oPj1KeXxIsEmhBZn95FfjPUpKtngbq+tBwUwthdKYNrAl4cb1bFWIGObfdkTi37CM2ReVCevndTrJGlJfAZzTA2exqvn01gSovOS/h4iKEnlvG+GGXo7JI1qJaHQqXBGFYjdadHejoeMCQat9MNL70J8QfYzj32xBNPjZzxaZDT9PHZX83JHeqYSrJZeVw6G2N19YC6mgCTD9Mr4GprUQNn+H5GxE6jjkQzSVMFp3ygrzlC6alZKkrqUtPixVkFiep/SBLDf9mjWS7TbmQzSRh9S9ikcg9RfLxC+bYVuNrsYbfuYIkmqZQ7JGs9Y9iIMuMk36lfF6Pv4BSXmsnlRWbvg6gvU/caojH0EX1OoZBJW6NVeo95o3TrqiTSrjZAXhm8NaWXn3OVV/m1sNinUWEsO3epZ1Q X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6eec94b0-70df-49d1-57fa-08da09049aea X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:41.2258 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jQt4b9EFGdJtvKnF9KphbftwQJ9A2wT67DviemQNesaRMxkwfPpjmXr5v8N0y99V X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3951 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This is the basic infrastructure of a new miscdevice to hold the iommufd IOCTL API. It provides: - A miscdevice to create file descriptors to run the IOCTL interface over - A table based ioctl dispatch and centralized extendable pre-validation step - An xarray mapping user ID's to kernel objects. The design has multiple inter-related objects held within in a single IOMMUFD fd - A simple usage count to build a graph of object relations and protect against hostile userspace racing ioctls The only IOCTL provided in this patch is the generic 'destroy any object by handle' operation. Signed-off-by: Yi Liu Signed-off-by: Jason Gunthorpe --- .../userspace-api/ioctl/ioctl-number.rst | 1 + MAINTAINERS | 10 + drivers/iommu/Kconfig | 1 + drivers/iommu/Makefile | 2 +- drivers/iommu/iommufd/Kconfig | 13 + drivers/iommu/iommufd/Makefile | 5 + drivers/iommu/iommufd/iommufd_private.h | 95 ++++++ drivers/iommu/iommufd/main.c | 305 ++++++++++++++++++ include/uapi/linux/iommufd.h | 55 ++++ 9 files changed, 486 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/iommufd/Kconfig create mode 100644 drivers/iommu/iommufd/Makefile create mode 100644 drivers/iommu/iommufd/iommufd_private.h create mode 100644 drivers/iommu/iommufd/main.c create mode 100644 include/uapi/linux/iommufd.h diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst index e6fce2cbd99ed4..4a041dfc61fe95 100644 --- a/Documentation/userspace-api/ioctl/ioctl-number.rst +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -105,6 +105,7 @@ Code Seq# Include File Comments '8' all SNP8023 advanced NIC card ';' 64-7F linux/vfio.h +';' 80-FF linux/iommufd.h '=' 00-3f uapi/linux/ptp_clock.h '@' 00-0F linux/radeonfb.h conflict! '@' 00-0F drivers/video/aty/aty128fb.c conflict! diff --git a/MAINTAINERS b/MAINTAINERS index 1ba1e4af2cbc80..23a9c631051ee8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10038,6 +10038,16 @@ L: linux-mips@vger.kernel.org S: Maintained F: drivers/net/ethernet/sgi/ioc3-eth.c +IOMMU FD +M: Jason Gunthorpe +M: Kevin Tian +L: iommu@lists.linux-foundation.org +S: Maintained +F: Documentation/userspace-api/iommufd.rst +F: drivers/iommu/iommufd/ +F: include/uapi/linux/iommufd.h +F: include/linux/iommufd.h + IOMAP FILESYSTEM LIBRARY M: Christoph Hellwig M: Darrick J. Wong diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 3eb68fa1b8cc02..754d2a9ff64623 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -177,6 +177,7 @@ config MSM_IOMMU source "drivers/iommu/amd/Kconfig" source "drivers/iommu/intel/Kconfig" +source "drivers/iommu/iommufd/Kconfig" config IRQ_REMAP bool "Support for Interrupt Remapping" diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index bc7f730edbb0be..6b38d12692b213 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y += amd/ intel/ arm/ +obj-y += amd/ intel/ arm/ iommufd/ obj-$(CONFIG_IOMMU_API) += iommu.o obj-$(CONFIG_IOMMU_API) += iommu-traces.o obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o diff --git a/drivers/iommu/iommufd/Kconfig b/drivers/iommu/iommufd/Kconfig new file mode 100644 index 00000000000000..fddd453bb0e764 --- /dev/null +++ b/drivers/iommu/iommufd/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +config IOMMUFD + tristate "IOMMU Userspace API" + select INTERVAL_TREE + select IOMMU_API + default n + help + Provides /dev/iommu the user API to control the IOMMU subsystem as + it relates to managing IO page tables that point at user space memory. + + This would commonly be used in combination with VFIO. + + If you don't know what to do here, say N. diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile new file mode 100644 index 00000000000000..a07a8cffe937c6 --- /dev/null +++ b/drivers/iommu/iommufd/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +iommufd-y := \ + main.o + +obj-$(CONFIG_IOMMUFD) += iommufd.o diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h new file mode 100644 index 00000000000000..2d0bba3965be1a --- /dev/null +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES + */ +#ifndef __IOMMUFD_PRIVATE_H +#define __IOMMUFD_PRIVATE_H + +#include +#include +#include +#include + +struct iommufd_ctx { + struct file *filp; + struct xarray objects; +}; + +struct iommufd_ctx *iommufd_fget(int fd); + +struct iommufd_ucmd { + struct iommufd_ctx *ictx; + void __user *ubuffer; + u32 user_size; + void *cmd; +}; + +/* Copy the response in ucmd->cmd back to userspace. */ +static inline int iommufd_ucmd_respond(struct iommufd_ucmd *ucmd, + size_t cmd_len) +{ + if (copy_to_user(ucmd->ubuffer, ucmd->cmd, + min_t(size_t, ucmd->user_size, cmd_len))) + return -EFAULT; + return 0; +} + +/* + * The objects for an acyclic graph through the users refcount. This enum must + * be sorted by type depth first so that destruction completes lower objects and + * releases the users refcount before reaching higher objects in the graph. + */ +enum iommufd_object_type { + IOMMUFD_OBJ_NONE, + IOMMUFD_OBJ_ANY = IOMMUFD_OBJ_NONE, + IOMMUFD_OBJ_MAX, +}; + +/* Base struct for all objects with a userspace ID handle. */ +struct iommufd_object { + struct rw_semaphore destroy_rwsem; + refcount_t users; + enum iommufd_object_type type; + unsigned int id; +}; + +static inline bool iommufd_lock_obj(struct iommufd_object *obj) +{ + if (!down_read_trylock(&obj->destroy_rwsem)) + return false; + if (!refcount_inc_not_zero(&obj->users)) { + up_read(&obj->destroy_rwsem); + return false; + } + return true; +} + +struct iommufd_object *iommufd_get_object(struct iommufd_ctx *ictx, u32 id, + enum iommufd_object_type type); +static inline void iommufd_put_object(struct iommufd_object *obj) +{ + refcount_dec(&obj->users); + up_read(&obj->destroy_rwsem); +} +static inline void iommufd_put_object_keep_user(struct iommufd_object *obj) +{ + up_read(&obj->destroy_rwsem); +} +void iommufd_object_abort(struct iommufd_ctx *ictx, struct iommufd_object *obj); +void iommufd_object_finalize(struct iommufd_ctx *ictx, + struct iommufd_object *obj); +bool iommufd_object_destroy_user(struct iommufd_ctx *ictx, + struct iommufd_object *obj); +struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, + size_t size, + enum iommufd_object_type type); + +#define iommufd_object_alloc(ictx, ptr, type) \ + container_of(_iommufd_object_alloc( \ + ictx, \ + sizeof(*(ptr)) + BUILD_BUG_ON_ZERO( \ + offsetof(typeof(*(ptr)), \ + obj) != 0), \ + type), \ + typeof(*(ptr)), obj) + +#endif diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c new file mode 100644 index 00000000000000..ae8db2f663004f --- /dev/null +++ b/drivers/iommu/iommufd/main.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2021 Intel Corporation + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES + * + * iommfd provides control over the IOMMU HW objects created by IOMMU kernel + * drivers. IOMMU HW objects revolve around IO page tables that map incoming DMA + * addresses (IOVA) to CPU addresses. + * + * The API is divided into a general portion that is intended to work with any + * kernel IOMMU driver, and a device specific portion that is intended to be + * used with a userspace HW driver paired with the specific kernel driver. This + * mechanism allows all the unique functionalities in individual IOMMUs to be + * exposed to userspace control. + */ +#define pr_fmt(fmt) "iommufd: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "iommufd_private.h" + +struct iommufd_object_ops { + void (*destroy)(struct iommufd_object *obj); +}; +static struct iommufd_object_ops iommufd_object_ops[]; + +struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, + size_t size, + enum iommufd_object_type type) +{ + struct iommufd_object *obj; + int rc; + + obj = kzalloc(size, GFP_KERNEL); + if (!obj) + return ERR_PTR(-ENOMEM); + obj->type = type; + init_rwsem(&obj->destroy_rwsem); + refcount_set(&obj->users, 1); + + /* + * Reserve an ID in the xarray but do not publish the pointer yet since + * the caller hasn't initialized it yet. Once the pointer is published + * in the xarray and visible to other threads we can't reliably destroy + * it anymore, so the caller must complete all errorable operations + * before calling iommufd_object_finalize(). + */ + rc = xa_alloc(&ictx->objects, &obj->id, XA_ZERO_ENTRY, + xa_limit_32b, GFP_KERNEL); + if (rc) + goto out_free; + return obj; +out_free: + kfree(obj); + return ERR_PTR(rc); +} + +/* + * Allow concurrent access to the object. This should only be done once the + * system call that created the object is guaranteed to succeed. + */ +void iommufd_object_finalize(struct iommufd_ctx *ictx, + struct iommufd_object *obj) +{ + void *old; + + old = xa_store(&ictx->objects, obj->id, obj, GFP_KERNEL); + /* obj->id was returned from xa_alloc() so the xa_store() cannot fail */ + WARN_ON(old); +} + +/* Undo _iommufd_object_alloc() if iommufd_object_finalize() was not called */ +void iommufd_object_abort(struct iommufd_ctx *ictx, struct iommufd_object *obj) +{ + void *old; + + old = xa_erase(&ictx->objects, obj->id); + WARN_ON(old); + kfree(obj); +} + +struct iommufd_object *iommufd_get_object(struct iommufd_ctx *ictx, u32 id, + enum iommufd_object_type type) +{ + struct iommufd_object *obj; + + xa_lock(&ictx->objects); + obj = xa_load(&ictx->objects, id); + if (!obj || (type != IOMMUFD_OBJ_ANY && obj->type != type) || + !iommufd_lock_obj(obj)) + obj = ERR_PTR(-ENOENT); + xa_unlock(&ictx->objects); + return obj; +} + +/* + * The caller holds a users refcount and wants to destroy the object. Returns + * true if the object was destroyed. In all cases the caller no longer has a + * reference on obj. + */ +bool iommufd_object_destroy_user(struct iommufd_ctx *ictx, + struct iommufd_object *obj) +{ + /* + * The purpose of the destroy_rwsem is to ensure deterministic + * destruction of objects used by external drivers and destroyed by this + * function. Any temporary increment of the refcount must hold the read + * side of this, such as during ioctl execution. + */ + down_write(&obj->destroy_rwsem); + xa_lock(&ictx->objects); + refcount_dec(&obj->users); + if (!refcount_dec_if_one(&obj->users)) { + xa_unlock(&ictx->objects); + up_write(&obj->destroy_rwsem); + return false; + } + __xa_erase(&ictx->objects, obj->id); + xa_unlock(&ictx->objects); + + iommufd_object_ops[obj->type].destroy(obj); + up_write(&obj->destroy_rwsem); + kfree(obj); + return true; +} + +static int iommufd_destroy(struct iommufd_ucmd *ucmd) +{ + struct iommu_destroy *cmd = ucmd->cmd; + struct iommufd_object *obj; + + obj = iommufd_get_object(ucmd->ictx, cmd->id, IOMMUFD_OBJ_ANY); + if (IS_ERR(obj)) + return PTR_ERR(obj); + iommufd_put_object_keep_user(obj); + if (!iommufd_object_destroy_user(ucmd->ictx, obj)) + return -EBUSY; + return 0; +} + +static int iommufd_fops_open(struct inode *inode, struct file *filp) +{ + struct iommufd_ctx *ictx; + + ictx = kzalloc(sizeof(*ictx), GFP_KERNEL); + if (!ictx) + return -ENOMEM; + + xa_init_flags(&ictx->objects, XA_FLAGS_ALLOC1); + ictx->filp = filp; + filp->private_data = ictx; + return 0; +} + +static int iommufd_fops_release(struct inode *inode, struct file *filp) +{ + struct iommufd_ctx *ictx = filp->private_data; + struct iommufd_object *obj; + unsigned long index = 0; + int cur = 0; + + /* Destroy the graph from depth first */ + while (cur < IOMMUFD_OBJ_MAX) { + xa_for_each(&ictx->objects, index, obj) { + if (obj->type != cur) + continue; + xa_erase(&ictx->objects, index); + if (WARN_ON(!refcount_dec_and_test(&obj->users))) + continue; + iommufd_object_ops[obj->type].destroy(obj); + kfree(obj); + } + cur++; + } + WARN_ON(!xa_empty(&ictx->objects)); + kfree(ictx); + return 0; +} + +union ucmd_buffer { + struct iommu_destroy destroy; +}; + +struct iommufd_ioctl_op { + unsigned int size; + unsigned int min_size; + unsigned int ioctl_num; + int (*execute)(struct iommufd_ucmd *ucmd); +}; + +#define IOCTL_OP(_ioctl, _fn, _struct, _last) \ + [_IOC_NR(_ioctl) - IOMMUFD_CMD_BASE] = { \ + .size = sizeof(_struct) + \ + BUILD_BUG_ON_ZERO(sizeof(union ucmd_buffer) < \ + sizeof(_struct)), \ + .min_size = offsetofend(_struct, _last), \ + .ioctl_num = _ioctl, \ + .execute = _fn, \ + } +static struct iommufd_ioctl_op iommufd_ioctl_ops[] = { + IOCTL_OP(IOMMU_DESTROY, iommufd_destroy, struct iommu_destroy, id), +}; + +static long iommufd_fops_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct iommufd_ucmd ucmd = {}; + struct iommufd_ioctl_op *op; + union ucmd_buffer buf; + unsigned int nr; + int ret; + + ucmd.ictx = filp->private_data; + ucmd.ubuffer = (void __user *)arg; + ret = get_user(ucmd.user_size, (u32 __user *)ucmd.ubuffer); + if (ret) + return ret; + + nr = _IOC_NR(cmd); + if (nr < IOMMUFD_CMD_BASE || + (nr - IOMMUFD_CMD_BASE) >= ARRAY_SIZE(iommufd_ioctl_ops)) + return -ENOIOCTLCMD; + op = &iommufd_ioctl_ops[nr - IOMMUFD_CMD_BASE]; + if (op->ioctl_num != cmd) + return -ENOIOCTLCMD; + if (ucmd.user_size < op->min_size) + return -EOPNOTSUPP; + + ucmd.cmd = &buf; + ret = copy_struct_from_user(ucmd.cmd, op->size, ucmd.ubuffer, + ucmd.user_size); + if (ret) + return ret; + ret = op->execute(&ucmd); + return ret; +} + +static const struct file_operations iommufd_fops = { + .owner = THIS_MODULE, + .open = iommufd_fops_open, + .release = iommufd_fops_release, + .unlocked_ioctl = iommufd_fops_ioctl, +}; + +/** + * iommufd_fget - Acquires a reference to the iommufd file. + * @fd: file descriptor + * + * Returns a pointer to the iommufd_ctx, otherwise NULL; + */ +struct iommufd_ctx *iommufd_fget(int fd) +{ + struct file *filp; + + filp = fget(fd); + if (!filp) + return NULL; + + if (filp->f_op != &iommufd_fops) { + fput(filp); + return NULL; + } + return filp->private_data; +} + +static struct iommufd_object_ops iommufd_object_ops[] = { +}; + +static struct miscdevice iommu_misc_dev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "iommu", + .fops = &iommufd_fops, + .nodename = "iommu", + .mode = 0660, +}; + +static int __init iommufd_init(void) +{ + int ret; + + ret = misc_register(&iommu_misc_dev); + if (ret) { + pr_err("Failed to register misc device\n"); + return ret; + } + + return 0; +} + +static void __exit iommufd_exit(void) +{ + misc_deregister(&iommu_misc_dev); +} + +module_init(iommufd_init); +module_exit(iommufd_exit); + +MODULE_DESCRIPTION("I/O Address Space Management for passthrough devices"); +MODULE_LICENSE("GPL v2"); diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h new file mode 100644 index 00000000000000..2f7f76ec6db4cb --- /dev/null +++ b/include/uapi/linux/iommufd.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. + */ +#ifndef _UAPI_IOMMUFD_H +#define _UAPI_IOMMUFD_H + +#include +#include + +#define IOMMUFD_TYPE (';') + +/** + * DOC: General ioctl format + * + * The ioctl mechanims follows a general format to allow for extensibility. Each + * ioctl is passed in a structure pointer as the argument providing the size of + * the structure in the first u32. The kernel checks that any structure space + * beyond what it understands is 0. This allows userspace to use the backward + * compatible portion while consistently using the newer, larger, structures. + * + * ioctls use a standard meaning for common errnos: + * + * - ENOTTY: The IOCTL number itself is not supported at all + * - E2BIG: The IOCTL number is supported, but the provided structure has + * non-zero in a part the kernel does not understand. + * - EOPNOTSUPP: The IOCTL number is supported, and the structure is + * understood, however a known field has a value the kernel does not + * understand or support. + * - EINVAL: Everything about the IOCTL was understood, but a field is not + * correct. + * - ENOENT: An ID or IOVA provided does not exist. + * - ENOMEM: Out of memory. + * - EOVERFLOW: Mathematics oveflowed. + * + * As well as additional errnos. within specific ioctls. + */ +enum { + IOMMUFD_CMD_BASE = 0x80, + IOMMUFD_CMD_DESTROY = IOMMUFD_CMD_BASE, +}; + +/** + * struct iommu_destroy - ioctl(IOMMU_DESTROY) + * @size: sizeof(struct iommu_destroy) + * @id: iommufd object ID to destroy. Can by any destroyable object type. + * + * Destroy any object held within iommufd. + */ +struct iommu_destroy { + __u32 size; + __u32 id; +}; +#define IOMMU_DESTROY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DESTROY) + +#endif From patchwork Fri Mar 18 17:27:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0163C4167E for ; Fri, 18 Mar 2022 17:27:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239634AbiCRR3L (ORCPT ); Fri, 18 Mar 2022 13:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239630AbiCRR3I (ORCPT ); Fri, 18 Mar 2022 13:29:08 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2074.outbound.protection.outlook.com [40.107.93.74]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E0B72A4F85 for ; Fri, 18 Mar 2022 10:27:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bU60KWXPeGf+7oW7jSpkLlpafGPphyfLc+s86XRk2UCJFEFx/dN0LXEIaW6SFkoYNNV50K9cfv6tW+gkh5YbZoe+hLvewOGs0+3R+31XV1H+OxjT9C7L18ZheaJq/H5MfscIxGxTHh9QcW3irSpQ66BhcvnnrCY9LJVQYq1cLhcR1zHxGFBO25uimduKqqlldUEnyXjd4UCJxZsaCIcOEH1lc5phUpmTZDIIYC5K2di5X7ojji6AJpy3xydSW9fRVEUzaAK6t5KYssDpZYVTadBHC7l86LHcUJQNkLUrvTtV8bYncx1qUObZsCaiHYP2TlWqeDKzbkxHJSI7cVAdzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8yLLEBbBOWMliWes7bwgbB3hkYda8vmMWRXQ1hDJkJA=; b=fT3shWh0UhqRbH//U01engVIEjVltMu+IMag6fZCaYtj0Z/QWMpGRuoRYJR+tV+VnjIselN2Et/eSRSS6k3RSqc8jrnrB/sfFdDrGZL8ZvwFkDso0Z+PF6X/mAXN7pk4Oez0oQWgfKNFJeF4uWnhQqPC/t30qyCPnB9oepStwjcECNaOAMOAmiuTyBOW9R1vVwqDZoYSRFDtjWe7MKuOuZda+orGB/LWcm0j9WWNp7J+MBW7r+pEF+zpsH1hlRU+/zgNGG15LdHJ9LS/jRBS+5c4UH8NFDywzvFhZ1nYMwJdZyLVLMNuLJ8t49PPXfQU7i+kGPeEKSfoxSFy/pXY+Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8yLLEBbBOWMliWes7bwgbB3hkYda8vmMWRXQ1hDJkJA=; b=aItWsYNrXyIwWS/fvbzV2DM0GHzuPg6XPzAZlw8FbZpgN18X9jesPdqlFnE1xwScQCawW9bOJOgyiAqCg8Ak9mhuGaBohPVr6+tRQX0WF3vuR1UjX/hDU1KqcQnAQeK9XQKjt9YLB3vHmu0oohe6GYb+UeIGnztrZ9KiE9MyRxxIddvI83xFQILSja12bxXuFSZKsLBo1FWvs3mVsim+nVYEikH8GsncBQLN1oP1vKMp+WVLCTg7WzKMAWmH4vzjHG+uCMD529l/KfiPiyovDTsj4CDJ0oeYqGxQ9NJ6ffCuNZxsoMhbUPBbecSo+IPllXf4ZvMfZGGxTWvjBJStpw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by MN2PR12MB3951.namprd12.prod.outlook.com (2603:10b6:208:16b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.14; Fri, 18 Mar 2022 17:27:43 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c%5]) with mapi id 15.20.5081.018; Fri, 18 Mar 2022 17:27:43 +0000 From: Jason Gunthorpe Cc: Alex Williamson , Lu Baolu , Chaitanya Kulkarni , Cornelia Huck , Daniel Jordan , David Gibson , Eric Auger , iommu@lists.linux-foundation.org, Jason Wang , Jean-Philippe Brucker , Joao Martins , Kevin Tian , kvm@vger.kernel.org, Matthew Rosato , "Michael S. Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 04/12] kernel/user: Allow user::locked_vm to be usable for iommufd Date: Fri, 18 Mar 2022 14:27:29 -0300 Message-Id: <4-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: BL1PR13CA0222.namprd13.prod.outlook.com (2603:10b6:208:2bf::17) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1635b9d3-f7a0-452e-2802-08da09049a73 X-MS-TrafficTypeDiagnostic: MN2PR12MB3951:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SG8U2pQwyEPwsXMnYwnAsjMgUkcGp2DTWTGydEc5HZtM2vi2c6n8Rpe+p9GrqU9aNJMkuCJ+TjO7tJZCtSpbJRh75slxkdcxsZERsRZ2Qe0gzRcaSSlizhFgVJQ7toHvemHfnxNThRILSSAGlYGXGqUgWG1gkY0V6ATtltVCT2wl6DKhNFlkNoszuSY429V8itLcOo3CW7NlN7Qqg59RoWHN3wNC9VQ6npZVKM/KRhcJJt2M7co9Epi0vA8RHOeBlFVN14Xu9vQcBdo4BX32Mcp6F5LBFqcNt0yzikrdaFc60MoeUbYm64UaYG8UGo1/z8PS6UPgU87rMGV9G8T0+xrFzP7xcw8Xk4j8g2ekpiDeTYQXneJH0Ep+6kStXLMcyhHmuOQqsaQddFn19hwMyRQ6+c4NrPx/iG8qe7t8PXcK7TOJ+RYLkxyavW6aEHirbyEOoZwO9LLV0ayI7OLbepJZqB3RUbLP/gflE3cDvVtLladXaQ+Tt0Z9ZVM+w8quAWbqr1ZMajTw2ErwC1DTSpmVyIA2146MvGhJ7/o36WiEdYUoO4nXNPgQ2ykr3q1cipJm2EfPjNvL7AnJrxy47EE6leEQmdlttL5RAvFK52cGGN03c9ZfGM5mIHTxvU2w74NZdiMA9i85qX152fRNyo6KwzY1xGngs8YSavPf4clsGd80vkxjYxo21ybHlNlpLKbNlRn758Z408n628GN6g== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(83380400001)(7416002)(4326008)(2906002)(86362001)(508600001)(8676002)(6512007)(6506007)(6666004)(5660300002)(8936002)(109986005)(66946007)(26005)(66476007)(186003)(316002)(66556008)(2616005)(36756003)(38100700002)(6486002)(54906003)(4216001)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: S2yhHRj0f6P1CUo2fSoLvXo11IFr4DMNN71inpv6buePjayjaoDyymA8uS8KO68MBezijp/OxcIN+h8MI1X8F1VdagiM9qfr5Jr8HOWbTg3NNCpylneABgfSjpNcxsszrIm1PADVPwWRjVaLu5/5bzVQ0zrGgOFVcx9urefSb3OvGZXDVL7sIErWHVVpMzcISSyTfWZOZYW6k3ewTwLaUrDpjbWROI1UX7driGiuUbHbvPRrAsADiIvW2w69+UeoceCyB/3NQBhEY+rbJ0FCRnB+v9KAcJVRQBa5js+iMkzAZlaEvXcf71X7aCzegvg51ciIbRD/Cyt+aQ2pL3dHy+j39lGE25ql7mZzLQO/tyOzVQPtXWkMPysDM0HPCZzgeTOIed2kpTzp9umXbrvd7QZfOarUCe+u2XQz/xAKkARsunKOvp6H+OjPu9xgsjKMDrW35RhVnURtsSG/SjBXRmf3Db0H62Bk/LXN1WxZbkDoKjNGeJ/FEINhJsx617uhmMHP7MhFx6cXbUCtp5YFzsQnmHPYgBFc08AK+pe35pNIZ8X6670sMU6QIWpAuSbKBoIm1GiNVDDb+EUlcXTA79k2USs2FmW66skeIkIiE+Y0IIaMv2AxPaKGbN9zerRlV7VEuWYd73poMuyxyg4ZuhuLDFeaI/JMt8ybxBfQJC2cZNG5A7Fp8O9xqpTQw/T83n3mEosGxjGbCART+PWZxYmt7QCbY2m5arqfQXhs1eJEPR4SVNwi6ZfCkjV7atPFmaVNdzMdOWq5WqWoC/zjFBi54L0dn4sDj+orZjrdiXRdzSI7urNQE/fmHgeAPCchOtnBUGbIAIlmkXeqvCk71sG+VvRvtSe8MgIDO8b6G3lhggwbLGEJb09fWO+igV6xVa5SJ1NMGpVMtbCrG5mIYnnyXb56jpeLicMkaN1MHtKjhn1+8v7APE0/L1ecKxE+UtB2+7f2rVOzFY5FGNN//uFNJK+VHvGqVt5qoSxiGPaJcmNZJF9pZjmblZ1+B9kKMSPtNWUc88Jm6ySiiV0SYN2bWnbUE3gJeCJmwM1pYXAV9x/a+M2FLZndIyQB0m1/TEre4dhbZSzuPOqzB4g8SxdRQrZuhAMlkjPCXPKa88S7FbQ8D1HBP6GiDV+ARDBF5q2aWa0RMiQwJeMBpj8rAaZwS1nIow6psXO6LKOzVsMictcv0NqUu/JH7S0GSgQk4vWtH/CTFeFLihE635uvvPH+Emka6/zDmQMrvzoxkCfftljs6O3G1YC0/KQP6XlNNYNK7+4OxiIiL98lEhSok4HOFAX1hB4p9BJmpBQVErCVlrOBhSzeKaMnh4KqJBF+Kj+7IcOP4wal7w1dtPX/I24bY08WI+V2MKsjguv9xhQ3JKJgBetZ8Thfzfzdfv1gtEnx1oqtpg2dWaAlHfm7Txm46Ns75ld+TmvWrQuEvvA8SZJo9K0F+uZj9gKRskqF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1635b9d3-f7a0-452e-2802-08da09049a73 X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:40.3666 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: C0ElHAne2/uvwNxXc1zyaJLrmZqu/IWeDmq+AkrXvqD/oNqznDHFKABLjK6Y0llu X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3951 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Following the pattern of io_uring, perf, skb, and bpf iommfd will use user->locked_vm for accounting pinned pages. Ensure the value is included in the struct and export free_uid() as iommufd is modular. user->locked_vm is the correct accounting to use for ulimit because it is per-user, and the ulimit is not supposed to be per-process. Other places (vfio, vdpa and infiniband) have used mm->pinned_vm and/or mm->locked_vm for accounting pinned pages, but this is only per-process and inconsistent with the majority of the kernel. Signed-off-by: Jason Gunthorpe --- include/linux/sched/user.h | 2 +- kernel/user.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/sched/user.h b/include/linux/sched/user.h index 00ed419dd46413..c47dae71dad3c8 100644 --- a/include/linux/sched/user.h +++ b/include/linux/sched/user.h @@ -24,7 +24,7 @@ struct user_struct { kuid_t uid; #if defined(CONFIG_PERF_EVENTS) || defined(CONFIG_BPF_SYSCALL) || \ - defined(CONFIG_NET) || defined(CONFIG_IO_URING) + defined(CONFIG_NET) || defined(CONFIG_IO_URING) || IS_ENABLED(CONFIG_IOMMUFD) atomic_long_t locked_vm; #endif #ifdef CONFIG_WATCH_QUEUE diff --git a/kernel/user.c b/kernel/user.c index e2cf8c22b539a7..d667debeafd609 100644 --- a/kernel/user.c +++ b/kernel/user.c @@ -185,6 +185,7 @@ void free_uid(struct user_struct *up) if (refcount_dec_and_lock_irqsave(&up->__count, &uidhash_lock, &flags)) free_user(up, flags); } +EXPORT_SYMBOL_GPL(free_uid); struct user_struct *alloc_uid(kuid_t uid) { From patchwork Fri Mar 18 17:27:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B776C433F5 for ; Fri, 18 Mar 2022 17:27:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239633AbiCRR3J (ORCPT ); Fri, 18 Mar 2022 13:29:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239629AbiCRR3I (ORCPT ); Fri, 18 Mar 2022 13:29:08 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2074.outbound.protection.outlook.com [40.107.93.74]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12E7F1D763C for ; Fri, 18 Mar 2022 10:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AB7h/6bb0mNZE440XOJWhCSuyKzQBdi8PZPmibs1b+3BQ7BCCpFy82gOM+3u+6Nn4DXzfEfa9Q9YrffPCS+oAsXwZXomsiLZi3V1RDnFgF5lhy9VsWAC19BGfc7APclB1qsPk0unNDw0O0XcoaC6z8LMdxGELBtfgLZBe8wpZWcxgSpqU3GwPKEdCepousDtJAR421/31cECPwTN9lbvmLgu7xZKgiYKUfzTJWdDnzP9hKlaHfxgliBintQvOcyicvPytSSZGye39VxjqR7TaXuwnqhV/XE5BuCmIA52YGwjeGOKlqGGrgV3MkAaf05FvpZ+YPffeM2Vd/QPrN9upg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=M6c2qZhXtjYPkbxz5Q3ZORnWiUXQNTRTlwsNAzW1bLM=; b=YmISfO49MvYWpeO44h4xNvj949+rA0LvpzZNAPQFQydAD2pSZxlo6xh0p8On92LLUizTfoBRrc8TSsG+/KXu8HzlcVLbyO+WRIU4zC3S5ZKqhHE7HkpTPPqPXkgU3Ypt70gpl2Bg7xGAEPHAGYx6ExbtLlqQxzl1fWDP2rtFwHrF4qwATt6xDmeSFrspZ80Wo2011ai5EwhshX/4bVNNCJA2dUCXniSwoeQLFu8gqZPOkX8jMPDD72dJ36mKtGcybGWu0IwrojpitmAHusRSa9hJ2u9+H/imKyCouQz4skrksV7uH9b7dZCsVo+zEvONUWijwIWX7c4p0l4AzNotHg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=M6c2qZhXtjYPkbxz5Q3ZORnWiUXQNTRTlwsNAzW1bLM=; b=GbsGyL6DdhQzrbpJDVpDUkdMQX1Mn68uox4QP9f0ug4D4MY0yY5GABGQ5nYD5PWNzK3Rw60oU1A4lpJmHAZM5Gs7koLnp1jbZYpseg/2+fck1bMxeeLA68NNIrcO09GYhRuBPfRCGQCpTd5d5c8QdeHddRgJ0JAp87AfCeu92ZrOUOv1dcsgwhTVuOtS5xeVbBbzh1Qd2lzaRvsPj949i5Cz4GZ8vYZ22SwGgKQanEyJzdA2iJizszYgXKvTlk9KirDCW8/8OhpruSZkNyOIeAwunJF9aT6/e85msss3+JCLWz/uccCfYzvb8UXMbmbhzRuSXMTHOwwgdNBI3TfkQg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by MN2PR12MB3951.namprd12.prod.outlook.com (2603:10b6:208:16b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.14; Fri, 18 Mar 2022 17:27:41 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c%5]) with mapi id 15.20.5081.018; Fri, 18 Mar 2022 17:27:41 +0000 From: Jason Gunthorpe Cc: Alex Williamson , Lu Baolu , Chaitanya Kulkarni , Cornelia Huck , Daniel Jordan , David Gibson , Eric Auger , iommu@lists.linux-foundation.org, Jason Wang , Jean-Philippe Brucker , Joao Martins , Kevin Tian , kvm@vger.kernel.org, Matthew Rosato , "Michael S. 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The IOAS allows map/unmap of memory into ranges of IOVA called iopt_areas. Domains and in-kernel users (like VFIO mdevs) can be attached to the IOAS to access the PFNs that those IOVA areas cover. The IO Address Space (IOAS) datastructure is composed of: - struct io_pagetable holding the IOVA map - struct iopt_areas representing populated portions of IOVA - struct iopt_pages representing the storage of PFNs - struct iommu_domain representing the IO page table in the system IOMMU - struct iopt_pages_user representing in-kernel users of PFNs (ie VFIO mdevs) - struct xarray pinned_pfns holding a list of pages pinned by in-kernel users This patch introduces the lowest part of the datastructure - the movement of PFNs in a tiered storage scheme: 1) iopt_pages::pinned_pfns xarray 2) An iommu_domain 3) The origin of the PFNs, i.e. the userspace pointer PFN have to be copied between all combinations of tiers, depending on the configuration. The interface is an iterator called a 'pfn_reader' which determines which tier each PFN is stored and loads it into a list of PFNs held in a struct pfn_batch. Each step of the iterator will fill up the pfn_batch, then the caller can use the pfn_batch to send the PFNs to the required destination. Repeating this loop will read all the PFNs in an IOVA range. The pfn_reader and pfn_batch also keep track of the pinned page accounting. While PFNs are always stored and accessed as full PAGE_SIZE units the iommu_domain tier can store with a sub-page offset/length to support IOMMUs with a smaller IOPTE size than PAGE_SIZE. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommufd/Makefile | 3 +- drivers/iommu/iommufd/io_pagetable.h | 101 ++++ drivers/iommu/iommufd/iommufd_private.h | 20 + drivers/iommu/iommufd/pages.c | 723 ++++++++++++++++++++++++ 4 files changed, 846 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/iommufd/io_pagetable.h create mode 100644 drivers/iommu/iommufd/pages.c diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index a07a8cffe937c6..05a0e91e30afad 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only iommufd-y := \ - main.o + main.o \ + pages.o obj-$(CONFIG_IOMMUFD) += iommufd.o diff --git a/drivers/iommu/iommufd/io_pagetable.h b/drivers/iommu/iommufd/io_pagetable.h new file mode 100644 index 00000000000000..94ca8712722d31 --- /dev/null +++ b/drivers/iommu/iommufd/io_pagetable.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. + * + */ +#ifndef __IO_PAGETABLE_H +#define __IO_PAGETABLE_H + +#include +#include +#include +#include + +#include "iommufd_private.h" + +struct iommu_domain; + +/* + * Each io_pagetable is composed of intervals of areas which cover regions of + * the iova that are backed by something. iova not covered by areas is not + * populated in the page table. Each area is fully populated with pages. + * + * iovas are in byte units, but must be iopt->iova_alignment aligned. + * + * pages can be NULL, this means some other thread is still working on setting + * up the area. When observed under the write side of the domain_rwsem a NULL + * pages must mean no domains are filled. + * + * storage_domain points at an arbitrary iommu_domain that is holding the PFNs + * for this area. It is locked by the pages->mutex. This simplifies the locking + * as the pages code can rely on the storage_domain without having to get the + * iopt->domains_rwsem. + * + * The io_pagetable::iova_rwsem protects node + * The iopt_pages::mutex protects pages_node + * iopt and immu_prot are immutable + */ +struct iopt_area { + struct interval_tree_node node; + struct interval_tree_node pages_node; + /* How many bytes into the first page the area starts */ + unsigned int page_offset; + struct io_pagetable *iopt; + struct iopt_pages *pages; + struct iommu_domain *storage_domain; + /* IOMMU_READ, IOMMU_WRITE, etc */ + int iommu_prot; + atomic_t num_users; +}; + +static inline unsigned long iopt_area_index(struct iopt_area *area) +{ + return area->pages_node.start; +} + +static inline unsigned long iopt_area_last_index(struct iopt_area *area) +{ + return area->pages_node.last; +} + +static inline unsigned long iopt_area_iova(struct iopt_area *area) +{ + return area->node.start; +} + +static inline unsigned long iopt_area_last_iova(struct iopt_area *area) +{ + return area->node.last; +} + +/* + * This holds a pinned page list for multiple areas of IO address space. The + * pages always originate from a linear chunk of userspace VA. Multiple + * io_pagetable's, through their iopt_area's, can share a single iopt_pages + * which avoids multi-pinning and double accounting of page consumption. + * + * indexes in this structure are measured in PAGE_SIZE units, are 0 based from + * the start of the uptr and extend to npages. pages are pinned dynamically + * according to the intervals in the users_itree and domains_itree, npages + * records the current number of pages pinned. + */ +struct iopt_pages { + struct kref kref; + struct mutex mutex; + size_t npages; + size_t npinned; + size_t last_npinned; + struct task_struct *source_task; + struct mm_struct *source_mm; + struct user_struct *source_user; + void __user *uptr; + bool writable:1; + bool has_cap_ipc_lock:1; + + struct xarray pinned_pfns; + /* Of iopt_pages_user::node */ + struct rb_root_cached users_itree; + /* Of iopt_area::pages_node */ + struct rb_root_cached domains_itree; +}; + +#endif diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 2d0bba3965be1a..2f1301d39bba7c 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -9,6 +9,26 @@ #include #include +/* + * The IOVA to PFN map. The mapper automatically copies the PFNs into multiple + * domains and permits sharing of PFNs between io_pagetable instances. This + * supports both a design where IOAS's are 1:1 with a domain (eg because the + * domain is HW customized), or where the IOAS is 1:N with multiple generic + * domains. The io_pagetable holds an interval tree of iopt_areas which point + * to shared iopt_pages which hold the pfns mapped to the page table. + * + * The locking order is domains_rwsem -> iova_rwsem -> pages::mutex + */ +struct io_pagetable { + struct rw_semaphore domains_rwsem; + struct xarray domains; + unsigned int next_domain_id; + + struct rw_semaphore iova_rwsem; + struct rb_root_cached area_itree; + struct rb_root_cached reserved_iova_itree; +}; + struct iommufd_ctx { struct file *filp; struct xarray objects; diff --git a/drivers/iommu/iommufd/pages.c b/drivers/iommu/iommufd/pages.c new file mode 100644 index 00000000000000..a75e1c73527920 --- /dev/null +++ b/drivers/iommu/iommufd/pages.c @@ -0,0 +1,723 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. + * + * The iopt_pages is the center of the storage and motion of PFNs. Each + * iopt_pages represents a logical linear array of full PFNs. The array is 0 + * based and has npages in it. Accessors use 'index' to refer to the entry in + * this logical array, regardless of its storage location. + * + * PFNs are stored in a tiered scheme: + * 1) iopt_pages::pinned_pfns xarray + * 2) An iommu_domain + * 3) The origin of the PFNs, i.e. the userspace pointer + * + * PFN have to be copied between all combinations of tiers, depending on the + * configuration. + * + * When a PFN is taken out of the userspace pointer it is pinned exactly once. + * The storage locations of the PFN's index are tracked in the two interval + * trees. If no interval includes the index then it is not pinned. + * + * If users_itree includes the PFN's index then an in-kernel user has requested + * the page. The PFN is stored in the xarray so other requestors can continue to + * find it. + * + * If the domains_itree includes the PFN's index then an iommu_domain is storing + * the PFN and it can be read back using iommu_iova_to_phys(). To avoid + * duplicating storage the xarray is not used if only iommu_domains are using + * the PFN's index. + * + * As a general principle this is designed so that destroy never fails. This + * means removing an iommu_domain or releasing a in-kernel user will not fail + * due to insufficient memory. In practice this means some cases have to hold + * PFNs in the xarray even though they are also being stored in an iommu_domain. + * + * While the iopt_pages can use an iommu_domain as storage, it does not have an + * IOVA itself. Instead the iopt_area represents a range of IOVA and uses the + * iopt_pages as the PFN provider. Multiple iopt_areas can share the iopt_pages + * and reference their own slice of the PFN array, with sub page granularity. + * + * In this file the term 'last' indicates an inclusive and closed interval, eg + * [0,0] refers to a single PFN. 'end' means an open range, eg [0,0) refers to + * no PFNs. + */ +#include +#include +#include +#include + +#include "io_pagetable.h" + +#define TEMP_MEMORY_LIMIT 65536 +#define BATCH_BACKUP_SIZE 32 + +/* + * More memory makes pin_user_pages() and the batching more efficient, but as + * this is only a performance optimization don't try too hard to get it. A 64k + * allocation can hold about 26M of 4k pages and 13G of 2M pages in an + * pfn_batch. Various destroy paths cannot fail and provide a small amount of + * stack memory as a backup contingency. If backup_len is given this cannot + * fail. + */ +static void *temp_kmalloc(size_t *size, void *backup, size_t backup_len) +{ + void *res; + + if (*size < backup_len) + return backup; + *size = min_t(size_t, *size, TEMP_MEMORY_LIMIT); + res = kmalloc(*size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); + if (res) + return res; + *size = PAGE_SIZE; + if (backup_len) { + res = kmalloc(*size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); + if (res) + return res; + *size = backup_len; + return backup; + } + return kmalloc(*size, GFP_KERNEL); +} + +static void iopt_pages_add_npinned(struct iopt_pages *pages, size_t npages) +{ + int rc; + + rc = check_add_overflow(pages->npinned, npages, &pages->npinned); + if (IS_ENABLED(CONFIG_IOMMUFD_TEST)) + WARN_ON(rc || pages->npinned > pages->npages); +} + +static void iopt_pages_sub_npinned(struct iopt_pages *pages, size_t npages) +{ + int rc; + + rc = check_sub_overflow(pages->npinned, npages, &pages->npinned); + if (IS_ENABLED(CONFIG_IOMMUFD_TEST)) + WARN_ON(rc || pages->npinned > pages->npages); +} + +/* + * index is the number of PAGE_SIZE units from the start of the area's + * iopt_pages. If the iova is sub page-size then the area has an iova that + * covers a portion of the first and last pages in the range. + */ +static unsigned long iopt_area_index_to_iova(struct iopt_area *area, + unsigned long index) +{ + if (IS_ENABLED(CONFIG_IOMMUFD_TEST)) + WARN_ON(index < iopt_area_index(area) || + index > iopt_area_last_index(area)); + index -= iopt_area_index(area); + if (index == 0) + return iopt_area_iova(area); + return iopt_area_iova(area) - area->page_offset + index * PAGE_SIZE; +} + +static unsigned long iopt_area_index_to_iova_last(struct iopt_area *area, + unsigned long index) +{ + if (IS_ENABLED(CONFIG_IOMMUFD_TEST)) + WARN_ON(index < iopt_area_index(area) || + index > iopt_area_last_index(area)); + if (index == iopt_area_last_index(area)) + return iopt_area_last_iova(area); + return iopt_area_iova(area) - area->page_offset + + (index - iopt_area_index(area) + 1) * PAGE_SIZE - 1; +} + +static void iommu_unmap_nofail(struct iommu_domain *domain, unsigned long iova, + size_t size) +{ + size_t ret; + + ret = iommu_unmap(domain, iova, size); + /* + * It is a logic error in this code or a driver bug if the IOMMU unmaps + * something other than exactly as requested. + */ + WARN_ON(ret != size); +} + +static struct iopt_area *iopt_pages_find_domain_area(struct iopt_pages *pages, + unsigned long index) +{ + struct interval_tree_node *node; + + node = interval_tree_iter_first(&pages->domains_itree, index, index); + if (!node) + return NULL; + return container_of(node, struct iopt_area, pages_node); +} + +/* + * A simple datastructure to hold a vector of PFNs, optimized for contiguous + * PFNs. This is used as a temporary holding memory for shuttling pfns from one + * place to another. Generally everything is made more efficient if operations + * work on the largest possible grouping of pfns. eg fewer lock/unlock cycles, + * better cache locality, etc + */ +struct pfn_batch { + unsigned long *pfns; + u16 *npfns; + unsigned int array_size; + unsigned int end; + unsigned int total_pfns; +}; + +static void batch_clear(struct pfn_batch *batch) +{ + batch->total_pfns = 0; + batch->end = 0; + batch->pfns[0] = 0; + batch->npfns[0] = 0; +} + +static int __batch_init(struct pfn_batch *batch, size_t max_pages, void *backup, + size_t backup_len) +{ + const size_t elmsz = sizeof(*batch->pfns) + sizeof(*batch->npfns); + size_t size = max_pages * elmsz; + + batch->pfns = temp_kmalloc(&size, backup, backup_len); + if (!batch->pfns) + return -ENOMEM; + batch->array_size = size / elmsz; + batch->npfns = (u16 *)(batch->pfns + batch->array_size); + batch_clear(batch); + return 0; +} + +static int batch_init(struct pfn_batch *batch, size_t max_pages) +{ + return __batch_init(batch, max_pages, NULL, 0); +} + +static void batch_init_backup(struct pfn_batch *batch, size_t max_pages, + void *backup, size_t backup_len) +{ + __batch_init(batch, max_pages, backup, backup_len); +} + +static void batch_destroy(struct pfn_batch *batch, void *backup) +{ + if (batch->pfns != backup) + kfree(batch->pfns); +} + +/* true if the pfn could be added, false otherwise */ +static bool batch_add_pfn(struct pfn_batch *batch, unsigned long pfn) +{ + /* FIXME: U16 is too small */ + if (batch->end && + pfn == batch->pfns[batch->end - 1] + batch->npfns[batch->end - 1] && + batch->npfns[batch->end - 1] != U16_MAX) { + batch->npfns[batch->end - 1]++; + batch->total_pfns++; + return true; + } + if (batch->end == batch->array_size) + return false; + batch->total_pfns++; + batch->pfns[batch->end] = pfn; + batch->npfns[batch->end] = 1; + batch->end++; + return true; +} + +/* + * Fill the batch with pfns from the domain. When the batch is full, or it + * reaches last_index, the function will return. The caller should use + * batch->total_pfns to determine the starting point for the next iteration. + */ +static void batch_from_domain(struct pfn_batch *batch, + struct iommu_domain *domain, + struct iopt_area *area, unsigned long index, + unsigned long last_index) +{ + unsigned int page_offset = 0; + unsigned long iova; + phys_addr_t phys; + + batch_clear(batch); + iova = iopt_area_index_to_iova(area, index); + if (index == iopt_area_index(area)) + page_offset = area->page_offset; + while (index <= last_index) { + /* + * This is pretty slow, it would be nice to get the page size + * back from the driver, or have the driver directly fill the + * batch. + */ + phys = iommu_iova_to_phys(domain, iova) - page_offset; + if (!batch_add_pfn(batch, PHYS_PFN(phys))) + return; + iova += PAGE_SIZE - page_offset; + page_offset = 0; + index++; + } +} + +static int batch_to_domain(struct pfn_batch *batch, struct iommu_domain *domain, + struct iopt_area *area, unsigned long start_index) +{ + unsigned long last_iova = iopt_area_last_iova(area); + unsigned int page_offset = 0; + unsigned long start_iova; + unsigned long next_iova; + unsigned int cur = 0; + unsigned long iova; + int rc; + + /* The first index might be a partial page */ + if (start_index == iopt_area_index(area)) + page_offset = area->page_offset; + next_iova = iova = start_iova = + iopt_area_index_to_iova(area, start_index); + while (cur < batch->end) { + next_iova = min(last_iova + 1, + next_iova + batch->npfns[cur] * PAGE_SIZE - + page_offset); + rc = iommu_map(domain, iova, + PFN_PHYS(batch->pfns[cur]) + page_offset, + next_iova - iova, area->iommu_prot); + if (rc) + goto out_unmap; + iova = next_iova; + page_offset = 0; + cur++; + } + return 0; +out_unmap: + if (start_iova != iova) + iommu_unmap_nofail(domain, start_iova, iova - start_iova); + return rc; +} + +static void batch_from_xarray(struct pfn_batch *batch, struct xarray *xa, + unsigned long start_index, + unsigned long last_index) +{ + XA_STATE(xas, xa, start_index); + void *entry; + + rcu_read_lock(); + while (true) { + entry = xas_next(&xas); + if (xas_retry(&xas, entry)) + continue; + WARN_ON(!xa_is_value(entry)); + if (!batch_add_pfn(batch, xa_to_value(entry)) || + start_index == last_index) + break; + start_index++; + } + rcu_read_unlock(); +} + +static void clear_xarray(struct xarray *xa, unsigned long index, + unsigned long last) +{ + XA_STATE(xas, xa, index); + void *entry; + + xas_lock(&xas); + xas_for_each (&xas, entry, last) + xas_store(&xas, NULL); + xas_unlock(&xas); +} + +static int batch_to_xarray(struct pfn_batch *batch, struct xarray *xa, + unsigned long start_index) +{ + XA_STATE(xas, xa, start_index); + unsigned int npage = 0; + unsigned int cur = 0; + + do { + xas_lock(&xas); + while (cur < batch->end) { + void *old; + + old = xas_store(&xas, + xa_mk_value(batch->pfns[cur] + npage)); + if (xas_error(&xas)) + break; + WARN_ON(old); + npage++; + if (npage == batch->npfns[cur]) { + npage = 0; + cur++; + } + xas_next(&xas); + } + xas_unlock(&xas); + } while (xas_nomem(&xas, GFP_KERNEL)); + + if (xas_error(&xas)) { + if (xas.xa_index != start_index) + clear_xarray(xa, start_index, xas.xa_index - 1); + return xas_error(&xas); + } + return 0; +} + +static void batch_to_pages(struct pfn_batch *batch, struct page **pages) +{ + unsigned int npage = 0; + unsigned int cur = 0; + + while (cur < batch->end) { + *pages++ = pfn_to_page(batch->pfns[cur] + npage); + npage++; + if (npage == batch->npfns[cur]) { + npage = 0; + cur++; + } + } +} + +static void batch_from_pages(struct pfn_batch *batch, struct page **pages, + size_t npages) +{ + struct page **end = pages + npages; + + for (; pages != end; pages++) + if (!batch_add_pfn(batch, page_to_pfn(*pages))) + break; +} + +static void batch_unpin(struct pfn_batch *batch, struct iopt_pages *pages, + unsigned int offset, size_t npages) +{ + unsigned int cur = 0; + + while (offset) { + if (batch->npfns[cur] > offset) + break; + offset -= batch->npfns[cur]; + cur++; + } + + while (npages) { + size_t to_unpin = + min_t(size_t, npages, batch->npfns[cur] - offset); + + unpin_user_page_range_dirty_lock( + pfn_to_page(batch->pfns[cur] + offset), to_unpin, + pages->writable); + iopt_pages_sub_npinned(pages, to_unpin); + cur++; + offset = 0; + npages -= to_unpin; + } +} + +/* + * PFNs are stored in three places, in order of preference: + * - The iopt_pages xarray. This is only populated if there is a + * iopt_pages_user + * - The iommu_domain under an area + * - The original PFN source, ie pages->source_mm + * + * This iterator reads the pfns optimizing to load according to the + * above order. + */ +struct pfn_reader { + struct iopt_pages *pages; + struct interval_tree_span_iter span; + struct pfn_batch batch; + unsigned long batch_start_index; + unsigned long batch_end_index; + unsigned long last_index; + + struct page **upages; + size_t upages_len; + unsigned long upages_start; + unsigned long upages_end; + + unsigned int gup_flags; +}; + +static void update_unpinned(struct iopt_pages *pages) +{ + unsigned long npages = pages->last_npinned - pages->npinned; + + lockdep_assert_held(&pages->mutex); + + if (pages->has_cap_ipc_lock) { + pages->last_npinned = pages->npinned; + return; + } + + if (WARN_ON(pages->npinned > pages->last_npinned) || + WARN_ON(atomic_long_read(&pages->source_user->locked_vm) < npages)) + return; + atomic_long_sub(npages, &pages->source_user->locked_vm); + atomic64_sub(npages, &pages->source_mm->pinned_vm); + pages->last_npinned = pages->npinned; +} + +/* + * Changes in the number of pages pinned is done after the pages have been read + * and processed. If the user lacked the limit then the error unwind will unpin + * everything that was just pinned. + */ +static int update_pinned(struct iopt_pages *pages) +{ + unsigned long lock_limit; + unsigned long cur_pages; + unsigned long new_pages; + unsigned long npages; + + lockdep_assert_held(&pages->mutex); + + if (pages->has_cap_ipc_lock) { + pages->last_npinned = pages->npinned; + return 0; + } + + if (pages->npinned == pages->last_npinned) + return 0; + + if (pages->npinned < pages->last_npinned) { + update_unpinned(pages); + return 0; + } + + lock_limit = + task_rlimit(pages->source_task, RLIMIT_MEMLOCK) >> PAGE_SHIFT; + npages = pages->npinned - pages->last_npinned; + do { + cur_pages = atomic_long_read(&pages->source_user->locked_vm); + new_pages = cur_pages + npages; + if (new_pages > lock_limit) + return -ENOMEM; + } while (atomic_long_cmpxchg(&pages->source_user->locked_vm, cur_pages, + new_pages) != cur_pages); + atomic64_add(npages, &pages->source_mm->pinned_vm); + pages->last_npinned = pages->npinned; + return 0; +} + +static int pfn_reader_pin_pages(struct pfn_reader *pfns) +{ + struct iopt_pages *pages = pfns->pages; + unsigned long npages; + long rc; + + if (!pfns->upages) { + /* All undone in iopt_pfn_reader_destroy */ + pfns->upages_len = + (pfns->last_index - pfns->batch_end_index + 1) * + sizeof(*pfns->upages); + pfns->upages = temp_kmalloc(&pfns->upages_len, NULL, 0); + if (!pfns->upages) + return -ENOMEM; + + if (!mmget_not_zero(pages->source_mm)) { + kfree(pfns->upages); + pfns->upages = NULL; + return -EINVAL; + } + mmap_read_lock(pages->source_mm); + } + + npages = min_t(unsigned long, + pfns->span.last_hole - pfns->batch_end_index + 1, + pfns->upages_len / sizeof(*pfns->upages)); + + /* FIXME use pin_user_pages_fast() if current == source_mm */ + rc = pin_user_pages_remote( + pages->source_mm, + (uintptr_t)(pages->uptr + pfns->batch_end_index * PAGE_SIZE), + npages, pfns->gup_flags, pfns->upages, NULL, NULL); + if (rc < 0) + return rc; + if (WARN_ON(!rc)) + return -EFAULT; + iopt_pages_add_npinned(pages, rc); + pfns->upages_start = pfns->batch_end_index; + pfns->upages_end = pfns->batch_end_index + rc; + return 0; +} + +/* + * The batch can contain a mixture of pages that are still in use and pages that + * need to be unpinned. Unpin only pages that are not held anywhere else. + */ +static void iopt_pages_unpin(struct iopt_pages *pages, struct pfn_batch *batch, + unsigned long index, unsigned long last) +{ + struct interval_tree_span_iter user_span; + struct interval_tree_span_iter area_span; + + lockdep_assert_held(&pages->mutex); + + for (interval_tree_span_iter_first(&user_span, &pages->users_itree, 0, + last); + !interval_tree_span_iter_done(&user_span); + interval_tree_span_iter_next(&user_span)) { + if (!user_span.is_hole) + continue; + + for (interval_tree_span_iter_first( + &area_span, &pages->domains_itree, + user_span.start_hole, user_span.last_hole); + !interval_tree_span_iter_done(&area_span); + interval_tree_span_iter_next(&area_span)) { + if (!area_span.is_hole) + continue; + + batch_unpin(batch, pages, area_span.start_hole - index, + area_span.last_hole - area_span.start_hole + + 1); + } + } +} + +/* Process a single span in the users_itree */ +static int pfn_reader_fill_span(struct pfn_reader *pfns) +{ + struct interval_tree_span_iter *span = &pfns->span; + struct iopt_area *area; + int rc; + + if (!span->is_hole) { + batch_from_xarray(&pfns->batch, &pfns->pages->pinned_pfns, + pfns->batch_end_index, span->last_used); + return 0; + } + + /* FIXME: This should consider the entire hole remaining */ + area = iopt_pages_find_domain_area(pfns->pages, pfns->batch_end_index); + if (area) { + unsigned int last_index; + + last_index = min(iopt_area_last_index(area), span->last_hole); + /* The storage_domain cannot change without the pages mutex */ + batch_from_domain(&pfns->batch, area->storage_domain, area, + pfns->batch_end_index, last_index); + return 0; + } + + if (pfns->batch_end_index >= pfns->upages_end) { + rc = pfn_reader_pin_pages(pfns); + if (rc) + return rc; + } + + batch_from_pages(&pfns->batch, + pfns->upages + + (pfns->batch_end_index - pfns->upages_start), + pfns->upages_end - pfns->batch_end_index); + return 0; +} + +static bool pfn_reader_done(struct pfn_reader *pfns) +{ + return pfns->batch_start_index == pfns->last_index + 1; +} + +static int pfn_reader_next(struct pfn_reader *pfns) +{ + int rc; + + batch_clear(&pfns->batch); + pfns->batch_start_index = pfns->batch_end_index; + while (pfns->batch_end_index != pfns->last_index + 1) { + rc = pfn_reader_fill_span(pfns); + if (rc) + return rc; + pfns->batch_end_index = + pfns->batch_start_index + pfns->batch.total_pfns; + if (pfns->batch_end_index != pfns->span.last_used + 1) + return 0; + interval_tree_span_iter_next(&pfns->span); + } + return 0; +} + +/* + * Adjust the pfn_reader to start at an externally determined hole span in the + * users_itree. + */ +static int pfn_reader_seek_hole(struct pfn_reader *pfns, + struct interval_tree_span_iter *span) +{ + pfns->batch_start_index = span->start_hole; + pfns->batch_end_index = span->start_hole; + pfns->last_index = span->last_hole; + pfns->span = *span; + return pfn_reader_next(pfns); +} + +static int pfn_reader_init(struct pfn_reader *pfns, struct iopt_pages *pages, + unsigned long index, unsigned long last) +{ + int rc; + + lockdep_assert_held(&pages->mutex); + + rc = batch_init(&pfns->batch, last - index + 1); + if (rc) + return rc; + pfns->pages = pages; + pfns->batch_start_index = index; + pfns->batch_end_index = index; + pfns->last_index = last; + pfns->upages = NULL; + pfns->upages_start = 0; + pfns->upages_end = 0; + interval_tree_span_iter_first(&pfns->span, &pages->users_itree, index, + last); + + if (pages->writable) { + pfns->gup_flags = FOLL_LONGTERM | FOLL_WRITE; + } else { + /* Still need to break COWs on read */ + pfns->gup_flags = FOLL_LONGTERM | FOLL_FORCE | FOLL_WRITE; + } + return 0; +} + +static void pfn_reader_destroy(struct pfn_reader *pfns) +{ + if (pfns->upages) { + size_t npages = pfns->upages_end - pfns->batch_end_index; + + mmap_read_unlock(pfns->pages->source_mm); + mmput(pfns->pages->source_mm); + + /* Any pages not transferred to the batch are just unpinned */ + unpin_user_pages(pfns->upages + (pfns->batch_end_index - + pfns->upages_start), + npages); + kfree(pfns->upages); + pfns->upages = NULL; + } + + if (pfns->batch_start_index != pfns->batch_end_index) + iopt_pages_unpin(pfns->pages, &pfns->batch, + pfns->batch_start_index, + pfns->batch_end_index - 1); + batch_destroy(&pfns->batch, NULL); + WARN_ON(pfns->pages->last_npinned != pfns->pages->npinned); +} + +static int pfn_reader_first(struct pfn_reader *pfns, struct iopt_pages *pages, + unsigned long index, unsigned long last) +{ + int rc; + + rc = pfn_reader_init(pfns, pages, index, last); + if (rc) + return rc; + rc = pfn_reader_next(pfns); + if (rc) { + pfn_reader_destroy(pfns); + return rc; + } + return 0; +} From patchwork Fri Mar 18 17:27:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5E8CC433EF for ; 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Each area points to a slice of exactly one iopt_pages, and each iopt_pages can have multiple areas and users. The three storage tiers are managed to meet these objectives: - If no iommu_domain or user exists then minimal memory should be consumed by iomufd - If a page has been pinned then an iopt_pages will not pin it again - If an in-kernel user exists then the xarray must provide the backing storage to avoid allocations on domain removals - Otherwise any iommu_domain will be used for storage In a common configuration with only an iommu_domain the iopt_pages does not allocate significant memory itself. The external interface for pages has several logical operations: iopt_area_fill_domain() will load the PFNs from storage into a single domain. This is used when attaching a new domain to an existing IOAS. iopt_area_fill_domains() will load the PFNs from storage into multiple domains. This is used when creating a new IOVA map in an existing IOAS iopt_pages_add_user() creates an iopt_pages_user that tracks an in-kernel user of PFNs. This is some external driver that might be accessing the IOVA using the CPU, or programming PFNs with the DMA API. ie a VFIO mdev. iopt_pages_fill_xarray() will load PFNs into the xarray and return a 'struct page *' array. It is used by iopt_pages_user's to extract PFNs for in-kernel use. iopt_pages_fill_from_xarray() is a fast path when it is known the xarray is already filled. As an iopt_pages can be referred to in slices by many areas and users it uses interval trees to keep track of which storage tiers currently hold the PFNs. On a page-by-page basis any request for a PFN will be satisfied from one of the storage tiers and the PFN copied to target domain/array. Unfill actions are similar, on a page by page basis domains are unmapped, xarray entries freed or struct pages fully put back. Significant complexity is required to fully optimize all of these data motions. The implementation calculates the largest consecutive range of same-storage indexes and operates in blocks. The accumulation of PFNs always generates the largest contiguous PFN range possible to optimize and this gathering can cross storage tier boundaries. For cases like 'fill domains' care is taken to avoid duplicated work and PFNs are read once and pushed into all domains. The map/unmap interaction with the iommu_domain always works in contiguous PFN blocks. The implementation does not require or benefit from any split/merge optimization in the iommu_domain driver. This design suggests several possible improvements in the IOMMU API that would greatly help performance, particularly a way for the driver to map and read the pfns lists instead of working with one driver call perpage to read, and one driver call per contiguous range to store. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommufd/io_pagetable.h | 71 +++- drivers/iommu/iommufd/pages.c | 594 +++++++++++++++++++++++++++ 2 files changed, 664 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/io_pagetable.h b/drivers/iommu/iommufd/io_pagetable.h index 94ca8712722d31..c8b6a60ff24c94 100644 --- a/drivers/iommu/iommufd/io_pagetable.h +++ b/drivers/iommu/iommufd/io_pagetable.h @@ -47,6 +47,14 @@ struct iopt_area { atomic_t num_users; }; +int iopt_area_fill_domains(struct iopt_area *area, struct iopt_pages *pages); +void iopt_area_unfill_domains(struct iopt_area *area, struct iopt_pages *pages); + +int iopt_area_fill_domain(struct iopt_area *area, struct iommu_domain *domain); +void iopt_area_unfill_domain(struct iopt_area *area, struct iopt_pages *pages, + struct iommu_domain *domain); +void iopt_unmap_domain(struct io_pagetable *iopt, struct iommu_domain *domain); + static inline unsigned long iopt_area_index(struct iopt_area *area) { return area->pages_node.start; @@ -67,6 +75,37 @@ static inline unsigned long iopt_area_last_iova(struct iopt_area *area) return area->node.last; } +static inline size_t iopt_area_length(struct iopt_area *area) +{ + return (area->node.last - area->node.start) + 1; +} + +static inline struct iopt_area *iopt_area_iter_first(struct io_pagetable *iopt, + unsigned long start, + unsigned long last) +{ + struct interval_tree_node *node; + + lockdep_assert_held(&iopt->iova_rwsem); + + node = interval_tree_iter_first(&iopt->area_itree, start, last); + if (!node) + return NULL; + return container_of(node, struct iopt_area, node); +} + +static inline struct iopt_area *iopt_area_iter_next(struct iopt_area *area, + unsigned long start, + unsigned long last) +{ + struct interval_tree_node *node; + + node = interval_tree_iter_next(&area->node, start, last); + if (!node) + return NULL; + return container_of(node, struct iopt_area, node); +} + /* * This holds a pinned page list for multiple areas of IO address space. The * pages always originate from a linear chunk of userspace VA. Multiple @@ -75,7 +114,7 @@ static inline unsigned long iopt_area_last_iova(struct iopt_area *area) * * indexes in this structure are measured in PAGE_SIZE units, are 0 based from * the start of the uptr and extend to npages. pages are pinned dynamically - * according to the intervals in the users_itree and domains_itree, npages + * according to the intervals in the users_itree and domains_itree, npinned * records the current number of pages pinned. */ struct iopt_pages { @@ -98,4 +137,34 @@ struct iopt_pages { struct rb_root_cached domains_itree; }; +struct iopt_pages *iopt_alloc_pages(void __user *uptr, unsigned long length, + bool writable); +void iopt_release_pages(struct kref *kref); +static inline void iopt_put_pages(struct iopt_pages *pages) +{ + kref_put(&pages->kref, iopt_release_pages); +} + +void iopt_pages_fill_from_xarray(struct iopt_pages *pages, unsigned long start, + unsigned long last, struct page **out_pages); +int iopt_pages_fill_xarray(struct iopt_pages *pages, unsigned long start, + unsigned long last, struct page **out_pages); +void iopt_pages_unfill_xarray(struct iopt_pages *pages, unsigned long start, + unsigned long last); + +int iopt_pages_add_user(struct iopt_pages *pages, unsigned long start, + unsigned long last, struct page **out_pages, + bool write); +void iopt_pages_remove_user(struct iopt_pages *pages, unsigned long start, + unsigned long last); + +/* + * Each interval represents an active iopt_access_pages(), it acts as an + * interval lock that keeps the PFNs pinned and stored in the xarray. + */ +struct iopt_pages_user { + struct interval_tree_node node; + refcount_t refcount; +}; + #endif diff --git a/drivers/iommu/iommufd/pages.c b/drivers/iommu/iommufd/pages.c index a75e1c73527920..8e6a8cc8b20ad1 100644 --- a/drivers/iommu/iommufd/pages.c +++ b/drivers/iommu/iommufd/pages.c @@ -140,6 +140,18 @@ static void iommu_unmap_nofail(struct iommu_domain *domain, unsigned long iova, WARN_ON(ret != size); } +static void iopt_area_unmap_domain_range(struct iopt_area *area, + struct iommu_domain *domain, + unsigned long start_index, + unsigned long last_index) +{ + unsigned long start_iova = iopt_area_index_to_iova(area, start_index); + + iommu_unmap_nofail(domain, start_iova, + iopt_area_index_to_iova_last(area, last_index) - + start_iova + 1); +} + static struct iopt_area *iopt_pages_find_domain_area(struct iopt_pages *pages, unsigned long index) { @@ -721,3 +733,585 @@ static int pfn_reader_first(struct pfn_reader *pfns, struct iopt_pages *pages, } return 0; } + +struct iopt_pages *iopt_alloc_pages(void __user *uptr, unsigned long length, + bool writable) +{ + struct iopt_pages *pages; + + /* + * The iommu API uses size_t as the length, and protect the DIV_ROUND_UP + * below from overflow + */ + if (length > SIZE_MAX - PAGE_SIZE || length == 0) + return ERR_PTR(-EINVAL); + + pages = kzalloc(sizeof(*pages), GFP_KERNEL); + if (!pages) + return ERR_PTR(-ENOMEM); + + kref_init(&pages->kref); + xa_init(&pages->pinned_pfns); + mutex_init(&pages->mutex); + pages->source_mm = current->mm; + mmgrab(pages->source_mm); + pages->uptr = (void __user *)ALIGN_DOWN((uintptr_t)uptr, PAGE_SIZE); + pages->npages = DIV_ROUND_UP(length + (uptr - pages->uptr), PAGE_SIZE); + pages->users_itree = RB_ROOT_CACHED; + pages->domains_itree = RB_ROOT_CACHED; + pages->writable = writable; + pages->has_cap_ipc_lock = capable(CAP_IPC_LOCK); + pages->source_task = current->group_leader; + get_task_struct(current->group_leader); + pages->source_user = get_uid(current_user()); + return pages; +} + +void iopt_release_pages(struct kref *kref) +{ + struct iopt_pages *pages = container_of(kref, struct iopt_pages, kref); + + WARN_ON(!RB_EMPTY_ROOT(&pages->users_itree.rb_root)); + WARN_ON(!RB_EMPTY_ROOT(&pages->domains_itree.rb_root)); + WARN_ON(pages->npinned); + WARN_ON(!xa_empty(&pages->pinned_pfns)); + mmdrop(pages->source_mm); + mutex_destroy(&pages->mutex); + put_task_struct(pages->source_task); + free_uid(pages->source_user); + kfree(pages); +} + +/* Quickly guess if the interval tree might fully cover the given interval */ +static bool interval_tree_fully_covers(struct rb_root_cached *root, + unsigned long index, unsigned long last) +{ + struct interval_tree_node *node; + + node = interval_tree_iter_first(root, index, last); + if (!node) + return false; + return node->start <= index && node->last >= last; +} + +static bool interval_tree_fully_covers_area(struct rb_root_cached *root, + struct iopt_area *area) +{ + return interval_tree_fully_covers(root, iopt_area_index(area), + iopt_area_last_index(area)); +} + +static void __iopt_area_unfill_domain(struct iopt_area *area, + struct iopt_pages *pages, + struct iommu_domain *domain, + unsigned long last_index) +{ + unsigned long unmapped_index = iopt_area_index(area); + unsigned long cur_index = unmapped_index; + u64 backup[BATCH_BACKUP_SIZE]; + struct pfn_batch batch; + + lockdep_assert_held(&pages->mutex); + + /* Fast path if there is obviously something else using every pfn */ + if (interval_tree_fully_covers_area(&pages->domains_itree, area) || + interval_tree_fully_covers_area(&pages->users_itree, area)) { + iopt_area_unmap_domain_range(area, domain, + iopt_area_index(area), last_index); + return; + } + + /* + * unmaps must always 'cut' at a place where the pfns are not contiguous + * to pair with the maps that always install contiguous pages. This + * algorithm is efficient in the expected case of few pinners. + */ + batch_init_backup(&batch, last_index + 1, backup, sizeof(backup)); + while (cur_index != last_index + 1) { + unsigned long batch_index = cur_index; + + batch_from_domain(&batch, domain, area, cur_index, last_index); + cur_index += batch.total_pfns; + iopt_area_unmap_domain_range(area, domain, unmapped_index, + cur_index - 1); + unmapped_index = cur_index; + iopt_pages_unpin(pages, &batch, batch_index, cur_index - 1); + batch_clear(&batch); + } + batch_destroy(&batch, backup); + update_unpinned(pages); +} + +static void iopt_area_unfill_partial_domain(struct iopt_area *area, + struct iopt_pages *pages, + struct iommu_domain *domain, + unsigned long end_index) +{ + if (end_index != iopt_area_index(area)) + __iopt_area_unfill_domain(area, pages, domain, end_index - 1); +} + +/** + * iopt_unmap_domain() - Unmap without unpinning PFNs in a domain + * @iopt: The iopt the domain is part of + * @domain: The domain to unmap + * + * The caller must know that unpinning is not required, usually because there + * are other domains in the iopt. + */ +void iopt_unmap_domain(struct io_pagetable *iopt, struct iommu_domain *domain) +{ + struct interval_tree_span_iter span; + + for (interval_tree_span_iter_first(&span, &iopt->area_itree, 0, + ULONG_MAX); + !interval_tree_span_iter_done(&span); + interval_tree_span_iter_next(&span)) + if (!span.is_hole) + iommu_unmap_nofail(domain, span.start_used, + span.last_used - span.start_used + + 1); +} + +/** + * iopt_area_unfill_domain() - Unmap and unpin PFNs in a domain + * @area: IOVA area to use + * @pages: page supplier for the area (area->pages is NULL) + * @domain: Domain to unmap from + * + * The domain should be removed from the domains_itree before calling. The + * domain will always be unmapped, but the PFNs may not be unpinned if there are + * still users. + */ +void iopt_area_unfill_domain(struct iopt_area *area, struct iopt_pages *pages, + struct iommu_domain *domain) +{ + __iopt_area_unfill_domain(area, pages, domain, + iopt_area_last_index(area)); +} + +/** + * iopt_area_fill_domain() - Map PFNs from the area into a domain + * @area: IOVA area to use + * @domain: Domain to load PFNs into + * + * Read the pfns from the area's underlying iopt_pages and map them into the + * given domain. Called when attaching a new domain to an io_pagetable. + */ +int iopt_area_fill_domain(struct iopt_area *area, struct iommu_domain *domain) +{ + struct pfn_reader pfns; + int rc; + + lockdep_assert_held(&area->pages->mutex); + + rc = pfn_reader_first(&pfns, area->pages, iopt_area_index(area), + iopt_area_last_index(area)); + if (rc) + return rc; + + while (!pfn_reader_done(&pfns)) { + rc = batch_to_domain(&pfns.batch, domain, area, + pfns.batch_start_index); + if (rc) + goto out_unmap; + + rc = pfn_reader_next(&pfns); + if (rc) + goto out_unmap; + } + + rc = update_pinned(area->pages); + if (rc) + goto out_unmap; + goto out_destroy; + +out_unmap: + iopt_area_unfill_partial_domain(area, area->pages, domain, + pfns.batch_start_index); +out_destroy: + pfn_reader_destroy(&pfns); + return rc; +} + +/** + * iopt_area_fill_domains() - Install PFNs into the area's domains + * @area: The area to act on + * @pages: The pages associated with the area (area->pages is NULL) + * + * Called during area creation. The area is freshly created and not inserted in + * the domains_itree yet. PFNs are read and loaded into every domain held in the + * area's io_pagetable and the area is installed in the domains_itree. + * + * On failure all domains are left unchanged. + */ +int iopt_area_fill_domains(struct iopt_area *area, struct iopt_pages *pages) +{ + struct pfn_reader pfns; + struct iommu_domain *domain; + unsigned long unmap_index; + unsigned long index; + int rc; + + lockdep_assert_held(&area->iopt->domains_rwsem); + + if (xa_empty(&area->iopt->domains)) + return 0; + + mutex_lock(&pages->mutex); + rc = pfn_reader_first(&pfns, pages, iopt_area_index(area), + iopt_area_last_index(area)); + if (rc) + goto out_unlock; + + while (!pfn_reader_done(&pfns)) { + xa_for_each (&area->iopt->domains, index, domain) { + rc = batch_to_domain(&pfns.batch, domain, area, + pfns.batch_start_index); + if (rc) + goto out_unmap; + } + + rc = pfn_reader_next(&pfns); + if (rc) + goto out_unmap; + } + rc = update_pinned(pages); + if (rc) + goto out_unmap; + + area->storage_domain = xa_load(&area->iopt->domains, 0); + interval_tree_insert(&area->pages_node, &pages->domains_itree); + goto out_destroy; + +out_unmap: + xa_for_each (&area->iopt->domains, unmap_index, domain) { + unsigned long end_index = pfns.batch_start_index; + + if (unmap_index <= index) + end_index = pfns.batch_end_index; + + /* + * The area is not yet part of the domains_itree so we have to + * manage the unpinning specially. The last domain does the + * unpin, every other domain is just unmapped. + */ + if (unmap_index != area->iopt->next_domain_id - 1) { + if (end_index != iopt_area_index(area)) + iopt_area_unmap_domain_range( + area, domain, iopt_area_index(area), + end_index - 1); + } else { + iopt_area_unfill_partial_domain(area, pages, domain, + end_index); + } + } +out_destroy: + pfn_reader_destroy(&pfns); +out_unlock: + mutex_unlock(&pages->mutex); + return rc; +} + +/** + * iopt_area_unfill_domains() - unmap PFNs from the area's domains + * @area: The area to act on + * @pages: The pages associated with the area (area->pages is NULL) + * + * Called during area destruction. This unmaps the iova's covered by all the + * area's domains and releases the PFNs. + */ +void iopt_area_unfill_domains(struct iopt_area *area, struct iopt_pages *pages) +{ + struct io_pagetable *iopt = area->iopt; + struct iommu_domain *domain; + unsigned long index; + + lockdep_assert_held(&iopt->domains_rwsem); + + mutex_lock(&pages->mutex); + if (!area->storage_domain) + goto out_unlock; + + xa_for_each (&iopt->domains, index, domain) + if (domain != area->storage_domain) + iopt_area_unmap_domain_range( + area, domain, iopt_area_index(area), + iopt_area_last_index(area)); + + interval_tree_remove(&area->pages_node, &pages->domains_itree); + iopt_area_unfill_domain(area, pages, area->storage_domain); + area->storage_domain = NULL; +out_unlock: + mutex_unlock(&pages->mutex); +} + +/* + * Erase entries in the pinned_pfns xarray that are not covered by any users. + * This does not unpin the pages, the caller is responsible to deal with the pin + * reference. The main purpose of this action is to save memory in the xarray. + */ +static void iopt_pages_clean_xarray(struct iopt_pages *pages, + unsigned long index, unsigned long last) +{ + struct interval_tree_span_iter span; + + lockdep_assert_held(&pages->mutex); + + for (interval_tree_span_iter_first(&span, &pages->users_itree, index, + last); + !interval_tree_span_iter_done(&span); + interval_tree_span_iter_next(&span)) + if (span.is_hole) + clear_xarray(&pages->pinned_pfns, span.start_hole, + span.last_hole); +} + +/** + * iopt_pages_unfill_xarray() - Update the xarry after removing a user + * @pages: The pages to act on + * @start: Starting PFN index + * @last: Last PFN index + * + * Called when an iopt_pages_user is removed, removes pages from the itree. + * The user should already be removed from the users_itree. + */ +void iopt_pages_unfill_xarray(struct iopt_pages *pages, unsigned long start, + unsigned long last) +{ + struct interval_tree_span_iter span; + struct pfn_batch batch; + u64 backup[BATCH_BACKUP_SIZE]; + + lockdep_assert_held(&pages->mutex); + + if (interval_tree_fully_covers(&pages->domains_itree, start, last)) + return iopt_pages_clean_xarray(pages, start, last); + + batch_init_backup(&batch, last + 1, backup, sizeof(backup)); + for (interval_tree_span_iter_first(&span, &pages->users_itree, start, + last); + !interval_tree_span_iter_done(&span); + interval_tree_span_iter_next(&span)) { + unsigned long cur_index; + + if (!span.is_hole) + continue; + cur_index = span.start_hole; + while (cur_index != span.last_hole + 1) { + batch_from_xarray(&batch, &pages->pinned_pfns, + cur_index, span.last_hole); + iopt_pages_unpin(pages, &batch, cur_index, + cur_index + batch.total_pfns - 1); + cur_index += batch.total_pfns; + batch_clear(&batch); + } + clear_xarray(&pages->pinned_pfns, span.start_hole, + span.last_hole); + } + batch_destroy(&batch, backup); + update_unpinned(pages); +} + +/** + * iopt_pages_fill_from_xarray() - Fast path for reading PFNs + * @pages: The pages to act on + * @start: The first page index in the range + * @last: The last page index in the range + * @out_pages: The output array to return the pages + * + * This can be called if the caller is holding a refcount on an iopt_pages_user + * that is known to have already been filled. It quickly reads the pages + * directly from the xarray. + * + * This is part of the SW iommu interface to read pages for in-kernel use. + */ +void iopt_pages_fill_from_xarray(struct iopt_pages *pages, unsigned long start, + unsigned long last, struct page **out_pages) +{ + XA_STATE(xas, &pages->pinned_pfns, start); + void *entry; + + rcu_read_lock(); + while (true) { + entry = xas_next(&xas); + if (xas_retry(&xas, entry)) + continue; + WARN_ON(!xa_is_value(entry)); + *(out_pages++) = pfn_to_page(xa_to_value(entry)); + if (start == last) + break; + start++; + } + rcu_read_unlock(); +} + +/** + * iopt_pages_fill_xarray() - Read PFNs + * @pages: The pages to act on + * @start: The first page index in the range + * @last: The last page index in the range + * @out_pages: The output array to return the pages, may be NULL + * + * This populates the xarray and returns the pages in out_pages. As the slow + * path this is able to copy pages from other storage tiers into the xarray. + * + * On failure the xarray is left unchanged. + * + * This is part of the SW iommu interface to read pages for in-kernel use. + */ +int iopt_pages_fill_xarray(struct iopt_pages *pages, unsigned long start, + unsigned long last, struct page **out_pages) +{ + struct interval_tree_span_iter span; + unsigned long xa_end = start; + struct pfn_reader pfns; + int rc; + + rc = pfn_reader_init(&pfns, pages, start, last); + if (rc) + return rc; + + for (interval_tree_span_iter_first(&span, &pages->users_itree, start, + last); + !interval_tree_span_iter_done(&span); + interval_tree_span_iter_next(&span)) { + if (!span.is_hole) { + if (out_pages) + iopt_pages_fill_from_xarray( + pages + (span.start_used - start), + span.start_used, span.last_used, + out_pages); + continue; + } + + rc = pfn_reader_seek_hole(&pfns, &span); + if (rc) + goto out_clean_xa; + + while (!pfn_reader_done(&pfns)) { + rc = batch_to_xarray(&pfns.batch, &pages->pinned_pfns, + pfns.batch_start_index); + if (rc) + goto out_clean_xa; + batch_to_pages(&pfns.batch, out_pages); + xa_end += pfns.batch.total_pfns; + out_pages += pfns.batch.total_pfns; + rc = pfn_reader_next(&pfns); + if (rc) + goto out_clean_xa; + } + } + + rc = update_pinned(pages); + if (rc) + goto out_clean_xa; + pfn_reader_destroy(&pfns); + return 0; + +out_clean_xa: + if (start != xa_end) + iopt_pages_unfill_xarray(pages, start, xa_end - 1); + pfn_reader_destroy(&pfns); + return rc; +} + +static struct iopt_pages_user * +iopt_pages_get_exact_user(struct iopt_pages *pages, unsigned long index, + unsigned long last) +{ + struct interval_tree_node *node; + + lockdep_assert_held(&pages->mutex); + + /* There can be overlapping ranges in this interval tree */ + for (node = interval_tree_iter_first(&pages->users_itree, index, last); + node; node = interval_tree_iter_next(node, index, last)) + if (node->start == index && node->last == last) + return container_of(node, struct iopt_pages_user, node); + return NULL; +} + +/** + * iopt_pages_add_user() - Record an in-knerel user for PFNs + * @pages: The source of PFNs + * @start: First page index + * @last: Inclusive last page index + * @out_pages: Output list of struct page's representing the PFNs + * @write: True if the user will write to the pages + * + * Record that an in-kernel user will be accessing the pages, ensure they are + * pinned, and return the PFNs as a simple list of 'struct page *'. + * + * This should be undone through a matching call to iopt_pages_remove_user() + */ +int iopt_pages_add_user(struct iopt_pages *pages, unsigned long start, + unsigned long last, struct page **out_pages, bool write) +{ + struct iopt_pages_user *user; + int rc; + + if (pages->writable != write) + return -EPERM; + + mutex_lock(&pages->mutex); + user = iopt_pages_get_exact_user(pages, start, last); + if (user) { + refcount_inc(&user->refcount); + mutex_unlock(&pages->mutex); + iopt_pages_fill_from_xarray(pages, start, last, out_pages); + return 0; + } + + user = kzalloc(sizeof(*user), GFP_KERNEL); + if (!user) { + rc = -ENOMEM; + goto out_unlock; + } + + rc = iopt_pages_fill_xarray(pages, start, last, out_pages); + if (rc) + goto out_free; + + user->node.start = start; + user->node.last = last; + refcount_set(&user->refcount, 1); + interval_tree_insert(&user->node, &pages->users_itree); + mutex_unlock(&pages->mutex); + return 0; + +out_free: + kfree(user); +out_unlock: + mutex_unlock(&pages->mutex); + return rc; +} + +/** + * iopt_pages_remove_user() - Release an in-kernel user for PFNs + * @pages: The source of PFNs + * @start: First page index + * @last: Inclusive last page index + * + * Undo iopt_pages_add_user() and unpin the pages if necessary. The caller must + * stop using the PFNs before calling this. + */ +void iopt_pages_remove_user(struct iopt_pages *pages, unsigned long start, + unsigned long last) +{ + struct iopt_pages_user *user; + + mutex_lock(&pages->mutex); + user = iopt_pages_get_exact_user(pages, start, last); + if (WARN_ON(!user)) + goto out_unlock; + + if (!refcount_dec_and_test(&user->refcount)) + goto out_unlock; + + interval_tree_remove(&user->node, &pages->users_itree); + iopt_pages_unfill_xarray(pages, start, last); + kfree(user); +out_unlock: + mutex_unlock(&pages->mutex); +} From patchwork Fri Mar 18 17:27:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 515AFC433FE for ; Fri, 18 Mar 2022 17:27:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239624AbiCRR3G (ORCPT ); Fri, 18 Mar 2022 13:29:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239613AbiCRR3F (ORCPT ); Fri, 18 Mar 2022 13:29:05 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 585461D7624 for ; Fri, 18 Mar 2022 10:27:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LvdtT5veeKB9K7Xxl46BEnFsAirW8cXyEJUvJH4NpqFX51CBGikKffjjd1jnl144gCQB/bPSl+WFzaUWPOdGt5MRPMRTiFodLo7IXYeR8+BAQBKnIM0Cc/x/UmZmqOlTrql1fDhl/+oz0lp2hRCu4fx+Q6nMkiXu97uBF0OxV+R6ZixubccRctzIBsot+UiqCPeZlLt5k46evRJ5NhY+zsu/v0FF9VmKfaAjxwkXhGsURObkevBeBD8zG0Vh80SOMHEQGd1lX5mqebo+xFdr4Gs8LfxDi0I9TuRRxpmPeqwlERqibb8NEaQSgZwxOnRzUrfzbfTJSjM5e5IGOUDXAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bqlkb2PSxtqKZOydzs2JIEOWy3w4o3YH4y7fwLO/xsA=; b=jjemnXGR0Lnhw8m0dcrhkVmPWH+eX6qIcbiiutqnQr6dCoXEcXgZ7z3EoSpjL4s1gOU3k3mggzsr2JZy2iEb01diKbMhjmbyyUsMGQ2JnoWlVj+fUalEcRQR79AWEV69VpiaHQrBBQubxKDHGo1IDbAl3sS7voZDXwLbtN+EPjEg7tlnk/IFZ4gt4fobcEy6dBmJdfZ0cBjjYRA+kH/3SGqh0jpXdQAQElu6tlYHNPVioiP+ipjAieFq9r8XP0PbqbL/HeaEtIwtVV+YMzBIiCpZVYbINrqIj/Mta7eENNs5IGKUnFiOA6zFey6vD+Ho08HHCk/FDskkARH+t9zNIQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bqlkb2PSxtqKZOydzs2JIEOWy3w4o3YH4y7fwLO/xsA=; b=SrrMbieNOSdBqp/gZLa4bZGyQxgqpo6J4TCbYge9fsqquAxJ6uFp97UM+p0a7ijjcKP7GXtQznPMcpCACRglZSSn4Pm2WzcpuRckQIXZJtbZSrIwlyXh3vqzBB7CslluhA4vKgWWJ74IJZmyl3lZ8xJkEEjGUOB5yJ5QCzDrZ5f8VkjyQG8bBthwvAwm2WT+5VPbtci0KjcGcwESVbwoVgAAdoOJqdyeovuA+WKptpLHaBBzKCVrj/3zinB45t/Z7OCMQkO/0CVJoEaqqGc1VcDhbnuECS4xaDsP9JnKAx0OrJNYsEP6qJDS/qQ+qNECEsY8UsBuP+jvigoVsX3jnQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by MN2PR12MB3951.namprd12.prod.outlook.com (2603:10b6:208:16b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.14; Fri, 18 Mar 2022 17:27:41 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c%5]) with mapi id 15.20.5081.018; Fri, 18 Mar 2022 17:27:41 +0000 From: Jason Gunthorpe Cc: Alex Williamson , Lu Baolu , Chaitanya Kulkarni , Cornelia Huck , Daniel Jordan , David Gibson , Eric Auger , iommu@lists.linux-foundation.org, Jason Wang , Jean-Philippe Brucker , Joao Martins , Kevin Tian , kvm@vger.kernel.org, Matthew Rosato , "Michael S. Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 07/12] iommufd: Data structure to provide IOVA to PFN mapping Date: Fri, 18 Mar 2022 14:27:32 -0300 Message-Id: <7-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR19CA0063.namprd19.prod.outlook.com (2603:10b6:208:19b::40) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a5427f27-41a1-42a2-7fc2-08da090499ce X-MS-TrafficTypeDiagnostic: MN2PR12MB3951:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7KCIx+nth6DtfKalgRoK3mLkDjwH5p48s40pK9cHcyVTfoM5g9OpSqaAwTTEgl3BiPvFuQFd7QAdsJq5ZwhhHR26CJHFaYAs4cUyX+tGlQGFy1H+zwxweHcUy0zvCfgdksl4HnB0PH6SbrogwGTTxzqdzi7+t0ZHTi7Kn9/U8ICKaA6R03F0t8zivhJUyEY75KiUs1mqs83w/3sOZlfj3bQj3bylMAX0GrD9qiI5dS3ecLD22RYZatcoXxSED311pltva39UUJq32Uh6CR2WOgpiwpFn+oBrgBrGzo3MI19hwFwbhWkml5uT6miG1QUEkzO8qnldyg1NewWsyYRuoq6Sge9gWgB9mtjkWCpaAvdrSM55GJePVpktiD+oial5S2tuC02ZbRv14DkRSyKIHdgyQ9+hQnCph4m1iAgZsQDAYFHKIBbH8WiT1P9SxU7XTo6PPXg2AJ1jTUymbpx9mSCZSETRIh6toX1akmf/xCVnd4IFWRMxG8V5bP8NST6Xv5wPF2ewPl6+J6rIxDhd7csmzlXrugXB4cMU4ft2OfLFILtemjStFb6z5lAJM1a7Hix9Z5BKLup94Z9HzOYFVV/85QW+PKtM8rYIh3TufWsSgdCKR34g8oE9vaX74526SPpbxDsXogs9O6tFbINavKw0q7KL1CK2V1QyAoSomi6upLUX1qPWlbWfN+gkgJc3aIm9UXFhtNN4cJzAx8cO0Q== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(30864003)(83380400001)(7416002)(4326008)(2906002)(86362001)(508600001)(8676002)(6512007)(6506007)(6666004)(5660300002)(8936002)(109986005)(66946007)(26005)(66476007)(186003)(316002)(66556008)(2616005)(36756003)(38100700002)(6486002)(54906003)(4216001)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IlmPkWcYugldH3cC/9z0oTLRMXWx+7Stx9uVah1EI3cAD4ymnC0aOOUudmtKtC1WcPHmourq3rFigrUJeN2Dl9eg0ur6O9JhgjGTtswf+Ca5OdeY47F1tAr0M3OoXVp40TYQr1lhX74pv4VSTubYVfUWp6nEKcbYOHpw1d3zxk81ODTtXDQfssspmP91ABKvL+AqGIbYvSoXydANJdzclPP2uCrDzUlqso9yS3jP7/59/YfPlzXepnxExfl/IhfbhGNwjUPwRmMSqV6WZrjdpF4YCmbdqSEwvdLpaxdH5hSegEvQCj/wsV1ZhcMgKr+0plprEBv09cOMb6vfKT1pEuKsbOBVuFa92JyRiDmfWM0XZa5/sTKbC8Wa5/2Rhbszo7zznjic+q9E72tHCO9p6S/LlhOv7ViUCuJLUmmEtAswHgzWIz46psH1z6i+yqRYi1dJ2LJEfjhIS4qK5Qdi4xs2XTEmlaa8ymxSb+IGSeYLOkDKxRq2mCrkWcymtR6oa9doOGIZ9EvkiLSISzlKSK6TXu4bwfCkZekqum/qLm8e2FNtLSU3eiD1j+a3ZZsSs0YZBZe6o3xdLy07MgtWtzT8/HcvqnJRSSwUQne1gP6v4wwmDBwtpogj/xqYKg+yMHzKph+Pp9Pq0kwiAAta2mplVilH0CapQ9KU8Ea+7BsogHY4tb0B9Youu4AEoFNQ6HSiVuUwdcJyFeT/auPgCMon6knlixt1PA8RTjSUV7roIc/DUoucUDedrThNOnsFIcLexSMOK22e7cYS/UGfQUZIqhOnnC9BLudRvb04q/5ypDuee4lQcwRS2GmG1hzEAexhsjRviqJ0C9GrzxfkzxB1eEWm0CG1FcEwS8KsLJpSFFo3FsjCaTVhzn/4RCP6aUbsROHNW34t+KcQKDBC5o1T6obDXvH6Q8BqQ8oPTuKNGlS63k5Pxq42jWT4dn9cBAUqsA6yORnlqUgO+S1cirX5DtruoYTQh6LrCqIdk6/x1p9XQL/VkhdDtl1dSwYwDZHsPmJ1RDVf5xpqKBosVjjc9UMo4CVorEGEx1GNNhRrqB0TlIr3nZ68+c+W+CKRw6yWWlQ2y+ovZ1mVUJcSztUonvH4BZwfZ4bCUHsP5N3/IXfVTp+OscgJS/jNBhM1KQOznmBWRozj3lfRd8YHiffoU/OB14f80Ca/4ABYBZbJmC+dP9t0mVrFBI61uVVrpr3/gWIHJ0ZAa+Hf8rb63vguYUR9dzedgmPWuvdkg8JaKM6UyH+Ytkz0WOXZHhncMlMF4ziJ1mfOYzXHWuARc+wU/8e6IRCXn7qRtXJc+ygGq5U31V3drPv5nwOlXXtuxEM7w3fjpd+fb9AHgi4JOek2Vd9smQ3Sh+W3zMo3P1OUrurpb63NU4wYca3rTAhOCldCv0X3CtGVkDMOwaGDnZXC3ZKDhtS/xot5s7DjFh0wUFKhFOp3M6E5XWSOybWq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: a5427f27-41a1-42a2-7fc2-08da090499ce X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:39.3824 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2sL4d/lGERvHuqiUt6tXxxg33Ua52tCTNNcMKEGt+HX90t0hi+BaW3MDna2DR0zM X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3951 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This is the remainder of the IOAS data structure. Provide an object called an io_pagetable that is composed of iopt_areas pointing at iopt_pages, along with a list of iommu_domains that mirror the IOVA to PFN map. At the top this is a simple interval tree of iopt_areas indicating the map of IOVA to iopt_pages. An xarray keeps track of a list of domains. Based on the attached domains there is a minimum alignment for areas (which may be smaller than PAGE_SIZE) and an interval tree of reserved IOVA that can't be mapped. The concept of a 'user' refers to something like a VFIO mdev that is accessing the IOVA and using a 'struct page *' for CPU based access. Externally an API is provided that matches the requirements of the IOCTL interface for map/unmap and domain attachment. The API provides a 'copy' primitive to establish a new IOVA map in a different IOAS from an existing mapping. This is designed to support a pre-registration flow where userspace would setup an dummy IOAS with no domains, map in memory and then establish a user to pin all PFNs into the xarray. Copy can then be used to create new IOVA mappings in a different IOAS, with iommu_domains attached. Upon copy the PFNs will be read out of the xarray and mapped into the iommu_domains, avoiding any pin_user_pages() overheads. Signed-off-by: Jason Gunthorpe Signed-off-by: Yi Liu --- drivers/iommu/iommufd/Makefile | 1 + drivers/iommu/iommufd/io_pagetable.c | 890 ++++++++++++++++++++++++ drivers/iommu/iommufd/iommufd_private.h | 35 + 3 files changed, 926 insertions(+) create mode 100644 drivers/iommu/iommufd/io_pagetable.c diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index 05a0e91e30afad..b66a8c47ff55ec 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only iommufd-y := \ + io_pagetable.o \ main.o \ pages.o diff --git a/drivers/iommu/iommufd/io_pagetable.c b/drivers/iommu/iommufd/io_pagetable.c new file mode 100644 index 00000000000000..f9f3b06946bfb9 --- /dev/null +++ b/drivers/iommu/iommufd/io_pagetable.c @@ -0,0 +1,890 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. + * + * The io_pagetable is the top of datastructure that maps IOVA's to PFNs. The + * PFNs can be placed into an iommu_domain, or returned to the caller as a page + * list for access by an in-kernel user. + * + * The datastructure uses the iopt_pages to optimize the storage of the PFNs + * between the domains and xarray. + */ +#include +#include +#include +#include +#include +#include + +#include "io_pagetable.h" + +static unsigned long iopt_area_iova_to_index(struct iopt_area *area, + unsigned long iova) +{ + if (IS_ENABLED(CONFIG_IOMMUFD_TEST)) + WARN_ON(iova < iopt_area_iova(area) || + iova > iopt_area_last_iova(area)); + return (iova - (iopt_area_iova(area) & PAGE_MASK)) / PAGE_SIZE; +} + +static struct iopt_area *iopt_find_exact_area(struct io_pagetable *iopt, + unsigned long iova, + unsigned long last_iova) +{ + struct iopt_area *area; + + area = iopt_area_iter_first(iopt, iova, last_iova); + if (!area || !area->pages || iopt_area_iova(area) != iova || + iopt_area_last_iova(area) != last_iova) + return NULL; + return area; +} + +static bool __alloc_iova_check_hole(struct interval_tree_span_iter *span, + unsigned long length, + unsigned long iova_alignment, + unsigned long page_offset) +{ + if (!span->is_hole || span->last_hole - span->start_hole < length - 1) + return false; + + span->start_hole = + ALIGN(span->start_hole, iova_alignment) | page_offset; + if (span->start_hole > span->last_hole || + span->last_hole - span->start_hole < length - 1) + return false; + return true; +} + +/* + * Automatically find a block of IOVA that is not being used and not reserved. + * Does not return a 0 IOVA even if it is valid. + */ +static int iopt_alloc_iova(struct io_pagetable *iopt, unsigned long *iova, + unsigned long uptr, unsigned long length) +{ + struct interval_tree_span_iter reserved_span; + unsigned long page_offset = uptr % PAGE_SIZE; + struct interval_tree_span_iter area_span; + unsigned long iova_alignment; + + lockdep_assert_held(&iopt->iova_rwsem); + + /* Protect roundup_pow-of_two() from overflow */ + if (length == 0 || length >= ULONG_MAX / 2) + return -EOVERFLOW; + + /* + * Keep alignment present in the uptr when building the IOVA, this + * increases the chance we can map a THP. + */ + if (!uptr) + iova_alignment = roundup_pow_of_two(length); + else + iova_alignment = + min_t(unsigned long, roundup_pow_of_two(length), + 1UL << __ffs64(uptr)); + + if (iova_alignment < iopt->iova_alignment) + return -EINVAL; + for (interval_tree_span_iter_first(&area_span, &iopt->area_itree, + PAGE_SIZE, ULONG_MAX - PAGE_SIZE); + !interval_tree_span_iter_done(&area_span); + interval_tree_span_iter_next(&area_span)) { + if (!__alloc_iova_check_hole(&area_span, length, iova_alignment, + page_offset)) + continue; + + for (interval_tree_span_iter_first( + &reserved_span, &iopt->reserved_iova_itree, + area_span.start_hole, area_span.last_hole); + !interval_tree_span_iter_done(&reserved_span); + interval_tree_span_iter_next(&reserved_span)) { + if (!__alloc_iova_check_hole(&reserved_span, length, + iova_alignment, + page_offset)) + continue; + + *iova = reserved_span.start_hole; + return 0; + } + } + return -ENOSPC; +} + +/* + * The area takes a slice of the pages from start_bytes to start_byte + length + */ +static struct iopt_area * +iopt_alloc_area(struct io_pagetable *iopt, struct iopt_pages *pages, + unsigned long iova, unsigned long start_byte, + unsigned long length, int iommu_prot, unsigned int flags) +{ + struct iopt_area *area; + int rc; + + area = kzalloc(sizeof(*area), GFP_KERNEL); + if (!area) + return ERR_PTR(-ENOMEM); + + area->iopt = iopt; + area->iommu_prot = iommu_prot; + area->page_offset = start_byte % PAGE_SIZE; + area->pages_node.start = start_byte / PAGE_SIZE; + if (check_add_overflow(start_byte, length - 1, &area->pages_node.last)) + return ERR_PTR(-EOVERFLOW); + area->pages_node.last = area->pages_node.last / PAGE_SIZE; + if (WARN_ON(area->pages_node.last >= pages->npages)) + return ERR_PTR(-EOVERFLOW); + + down_write(&iopt->iova_rwsem); + if (flags & IOPT_ALLOC_IOVA) { + rc = iopt_alloc_iova(iopt, &iova, + (uintptr_t)pages->uptr + start_byte, + length); + if (rc) + goto out_unlock; + } + + if (check_add_overflow(iova, length - 1, &area->node.last)) { + rc = -EOVERFLOW; + goto out_unlock; + } + + if (!(flags & IOPT_ALLOC_IOVA)) { + if ((iova & (iopt->iova_alignment - 1)) || + (length & (iopt->iova_alignment - 1)) || !length) { + rc = -EINVAL; + goto out_unlock; + } + + /* No reserved IOVA intersects the range */ + if (interval_tree_iter_first(&iopt->reserved_iova_itree, iova, + area->node.last)) { + rc = -ENOENT; + goto out_unlock; + } + + /* Check that there is not already a mapping in the range */ + if (iopt_area_iter_first(iopt, iova, area->node.last)) { + rc = -EADDRINUSE; + goto out_unlock; + } + } + + /* + * The area is inserted with a NULL pages indicating it is not fully + * initialized yet. + */ + area->node.start = iova; + interval_tree_insert(&area->node, &area->iopt->area_itree); + up_write(&iopt->iova_rwsem); + return area; + +out_unlock: + up_write(&iopt->iova_rwsem); + kfree(area); + return ERR_PTR(rc); +} + +static void iopt_abort_area(struct iopt_area *area) +{ + down_write(&area->iopt->iova_rwsem); + interval_tree_remove(&area->node, &area->iopt->area_itree); + up_write(&area->iopt->iova_rwsem); + kfree(area); +} + +static int iopt_finalize_area(struct iopt_area *area, struct iopt_pages *pages) +{ + int rc; + + down_read(&area->iopt->domains_rwsem); + rc = iopt_area_fill_domains(area, pages); + if (!rc) { + /* + * area->pages must be set inside the domains_rwsem to ensure + * any newly added domains will get filled. Moves the reference + * in from the caller + */ + down_write(&area->iopt->iova_rwsem); + area->pages = pages; + up_write(&area->iopt->iova_rwsem); + } + up_read(&area->iopt->domains_rwsem); + return rc; +} + +int iopt_map_pages(struct io_pagetable *iopt, struct iopt_pages *pages, + unsigned long *dst_iova, unsigned long start_bytes, + unsigned long length, int iommu_prot, unsigned int flags) +{ + struct iopt_area *area; + int rc; + + if ((iommu_prot & IOMMU_WRITE) && !pages->writable) + return -EPERM; + + area = iopt_alloc_area(iopt, pages, *dst_iova, start_bytes, length, + iommu_prot, flags); + if (IS_ERR(area)) + return PTR_ERR(area); + *dst_iova = iopt_area_iova(area); + + rc = iopt_finalize_area(area, pages); + if (rc) { + iopt_abort_area(area); + return rc; + } + return 0; +} + +/** + * iopt_map_user_pages() - Map a user VA to an iova in the io page table + * @iopt: io_pagetable to act on + * @iova: If IOPT_ALLOC_IOVA is set this is unused on input and contains + * the chosen iova on output. Otherwise is the iova to map to on input + * @uptr: User VA to map + * @length: Number of bytes to map + * @iommu_prot: Combination of IOMMU_READ/WRITE/etc bits for the mapping + * @flags: IOPT_ALLOC_IOVA or zero + * + * iova, uptr, and length must be aligned to iova_alignment. For domain backed + * page tables this will pin the pages and load them into the domain at iova. + * For non-domain page tables this will only setup a lazy reference and the + * caller must use iopt_access_pages() to touch them. + * + * iopt_unmap_iova() must be called to undo this before the io_pagetable can be + * destroyed. + */ +int iopt_map_user_pages(struct io_pagetable *iopt, unsigned long *iova, + void __user *uptr, unsigned long length, int iommu_prot, + unsigned int flags) +{ + struct iopt_pages *pages; + int rc; + + pages = iopt_alloc_pages(uptr, length, iommu_prot & IOMMU_WRITE); + if (IS_ERR(pages)) + return PTR_ERR(pages); + + rc = iopt_map_pages(iopt, pages, iova, uptr - pages->uptr, length, + iommu_prot, flags); + if (rc) { + iopt_put_pages(pages); + return rc; + } + return 0; +} + +struct iopt_pages *iopt_get_pages(struct io_pagetable *iopt, unsigned long iova, + unsigned long *start_byte, + unsigned long length) +{ + unsigned long iova_end; + struct iopt_pages *pages; + struct iopt_area *area; + + if (check_add_overflow(iova, length - 1, &iova_end)) + return ERR_PTR(-EOVERFLOW); + + down_read(&iopt->iova_rwsem); + area = iopt_find_exact_area(iopt, iova, iova_end); + if (!area) { + up_read(&iopt->iova_rwsem); + return ERR_PTR(-ENOENT); + } + pages = area->pages; + *start_byte = area->page_offset + iopt_area_index(area) * PAGE_SIZE; + kref_get(&pages->kref); + up_read(&iopt->iova_rwsem); + + return pages; +} + +static int __iopt_unmap_iova(struct io_pagetable *iopt, struct iopt_area *area, + struct iopt_pages *pages) +{ + /* Drivers have to unpin on notification. */ + if (WARN_ON(atomic_read(&area->num_users))) + return -EBUSY; + + iopt_area_unfill_domains(area, pages); + WARN_ON(atomic_read(&area->num_users)); + iopt_abort_area(area); + iopt_put_pages(pages); + return 0; +} + +/** + * iopt_unmap_iova() - Remove a range of iova + * @iopt: io_pagetable to act on + * @iova: Starting iova to unmap + * @length: Number of bytes to unmap + * + * The requested range must exactly match an existing range. + * Splitting/truncating IOVA mappings is not allowed. + */ +int iopt_unmap_iova(struct io_pagetable *iopt, unsigned long iova, + unsigned long length) +{ + struct iopt_pages *pages; + struct iopt_area *area; + unsigned long iova_end; + int rc; + + if (!length) + return -EINVAL; + + if (check_add_overflow(iova, length - 1, &iova_end)) + return -EOVERFLOW; + + down_read(&iopt->domains_rwsem); + down_write(&iopt->iova_rwsem); + area = iopt_find_exact_area(iopt, iova, iova_end); + if (!area) { + up_write(&iopt->iova_rwsem); + up_read(&iopt->domains_rwsem); + return -ENOENT; + } + pages = area->pages; + area->pages = NULL; + up_write(&iopt->iova_rwsem); + + rc = __iopt_unmap_iova(iopt, area, pages); + up_read(&iopt->domains_rwsem); + return rc; +} + +int iopt_unmap_all(struct io_pagetable *iopt) +{ + struct iopt_area *area; + int rc; + + down_read(&iopt->domains_rwsem); + down_write(&iopt->iova_rwsem); + while ((area = iopt_area_iter_first(iopt, 0, ULONG_MAX))) { + struct iopt_pages *pages; + + /* Userspace should not race unmap all and map */ + if (!area->pages) { + rc = -EBUSY; + goto out_unlock_iova; + } + pages = area->pages; + area->pages = NULL; + up_write(&iopt->iova_rwsem); + + rc = __iopt_unmap_iova(iopt, area, pages); + if (rc) + goto out_unlock_domains; + + down_write(&iopt->iova_rwsem); + } + rc = 0; + +out_unlock_iova: + up_write(&iopt->iova_rwsem); +out_unlock_domains: + up_read(&iopt->domains_rwsem); + return rc; +} + +/** + * iopt_access_pages() - Return a list of pages under the iova + * @iopt: io_pagetable to act on + * @iova: Starting IOVA + * @length: Number of bytes to access + * @out_pages: Output page list + * @write: True if access is for writing + * + * Reads @npages starting at iova and returns the struct page * pointers. These + * can be kmap'd by the caller for CPU access. + * + * The caller must perform iopt_unaccess_pages() when done to balance this. + * + * iova can be unaligned from PAGE_SIZE. The first returned byte starts at + * page_to_phys(out_pages[0]) + (iova % PAGE_SIZE). The caller promises not to + * touch memory outside the requested iova slice. + * + * FIXME: callers that need a DMA mapping via a sgl should create another + * interface to build the SGL efficiently + */ +int iopt_access_pages(struct io_pagetable *iopt, unsigned long iova, + unsigned long length, struct page **out_pages, bool write) +{ + unsigned long cur_iova = iova; + unsigned long last_iova; + struct iopt_area *area; + int rc; + + if (!length) + return -EINVAL; + if (check_add_overflow(iova, length - 1, &last_iova)) + return -EOVERFLOW; + + down_read(&iopt->iova_rwsem); + for (area = iopt_area_iter_first(iopt, iova, last_iova); area; + area = iopt_area_iter_next(area, iova, last_iova)) { + unsigned long last = min(last_iova, iopt_area_last_iova(area)); + unsigned long last_index; + unsigned long index; + + /* Need contiguous areas in the access */ + if (iopt_area_iova(area) < cur_iova || !area->pages) { + rc = -EINVAL; + goto out_remove; + } + + index = iopt_area_iova_to_index(area, cur_iova); + last_index = iopt_area_iova_to_index(area, last); + rc = iopt_pages_add_user(area->pages, index, last_index, + out_pages, write); + if (rc) + goto out_remove; + if (last == last_iova) + break; + /* + * Can't cross areas that are not aligned to the system page + * size with this API. + */ + if (cur_iova % PAGE_SIZE) { + rc = -EINVAL; + goto out_remove; + } + cur_iova = last + 1; + out_pages += last_index - index; + atomic_inc(&area->num_users); + } + + up_read(&iopt->iova_rwsem); + return 0; + +out_remove: + if (cur_iova != iova) + iopt_unaccess_pages(iopt, iova, cur_iova - iova); + up_read(&iopt->iova_rwsem); + return rc; +} + +/** + * iopt_unaccess_pages() - Undo iopt_access_pages + * @iopt: io_pagetable to act on + * @iova: Starting IOVA + * @length:- Number of bytes to access + * + * Return the struct page's. The caller must stop accessing them before calling + * this. The iova/length must exactly match the one provided to access_pages. + */ +void iopt_unaccess_pages(struct io_pagetable *iopt, unsigned long iova, + size_t length) +{ + unsigned long cur_iova = iova; + unsigned long last_iova; + struct iopt_area *area; + + if (WARN_ON(!length) || + WARN_ON(check_add_overflow(iova, length - 1, &last_iova))) + return; + + down_read(&iopt->iova_rwsem); + for (area = iopt_area_iter_first(iopt, iova, last_iova); area; + area = iopt_area_iter_next(area, iova, last_iova)) { + unsigned long last = min(last_iova, iopt_area_last_iova(area)); + int num_users; + + iopt_pages_remove_user(area->pages, + iopt_area_iova_to_index(area, cur_iova), + iopt_area_iova_to_index(area, last)); + if (last == last_iova) + break; + cur_iova = last + 1; + num_users = atomic_dec_return(&area->num_users); + WARN_ON(num_users < 0); + } + up_read(&iopt->iova_rwsem); +} + +struct iopt_reserved_iova { + struct interval_tree_node node; + void *owner; +}; + +int iopt_reserve_iova(struct io_pagetable *iopt, unsigned long start, + unsigned long last, void *owner) +{ + struct iopt_reserved_iova *reserved; + + lockdep_assert_held_write(&iopt->iova_rwsem); + + if (iopt_area_iter_first(iopt, start, last)) + return -EADDRINUSE; + + reserved = kzalloc(sizeof(*reserved), GFP_KERNEL); + if (!reserved) + return -ENOMEM; + reserved->node.start = start; + reserved->node.last = last; + reserved->owner = owner; + interval_tree_insert(&reserved->node, &iopt->reserved_iova_itree); + return 0; +} + +void iopt_remove_reserved_iova(struct io_pagetable *iopt, void *owner) +{ + + struct interval_tree_node *node; + + for (node = interval_tree_iter_first(&iopt->reserved_iova_itree, 0, + ULONG_MAX); + node;) { + struct iopt_reserved_iova *reserved = + container_of(node, struct iopt_reserved_iova, node); + + node = interval_tree_iter_next(node, 0, ULONG_MAX); + + if (reserved->owner == owner) { + interval_tree_remove(&reserved->node, + &iopt->reserved_iova_itree); + kfree(reserved); + } + } +} + +int iopt_init_table(struct io_pagetable *iopt) +{ + init_rwsem(&iopt->iova_rwsem); + init_rwsem(&iopt->domains_rwsem); + iopt->area_itree = RB_ROOT_CACHED; + iopt->reserved_iova_itree = RB_ROOT_CACHED; + xa_init(&iopt->domains); + + /* + * iopt's start as SW tables that can use the entire size_t IOVA space + * due to the use of size_t in the APIs. They have no alignment + * restriction. + */ + iopt->iova_alignment = 1; + + return 0; +} + +void iopt_destroy_table(struct io_pagetable *iopt) +{ + if (IS_ENABLED(CONFIG_IOMMUFD_TEST)) + iopt_remove_reserved_iova(iopt, NULL); + WARN_ON(!RB_EMPTY_ROOT(&iopt->reserved_iova_itree.rb_root)); + WARN_ON(!xa_empty(&iopt->domains)); + WARN_ON(!RB_EMPTY_ROOT(&iopt->area_itree.rb_root)); +} + +/** + * iopt_unfill_domain() - Unfill a domain with PFNs + * @iopt: io_pagetable to act on + * @domain: domain to unfill + * + * This is used when removing a domain from the iopt. Every area in the iopt + * will be unmapped from the domain. The domain must already be removed from the + * domains xarray. + */ +static void iopt_unfill_domain(struct io_pagetable *iopt, + struct iommu_domain *domain) +{ + struct iopt_area *area; + + lockdep_assert_held(&iopt->iova_rwsem); + lockdep_assert_held_write(&iopt->domains_rwsem); + + /* + * Some other domain is holding all the pfns still, rapidly unmap this + * domain. + */ + if (iopt->next_domain_id != 0) { + /* Pick an arbitrary remaining domain to act as storage */ + struct iommu_domain *storage_domain = + xa_load(&iopt->domains, 0); + + for (area = iopt_area_iter_first(iopt, 0, ULONG_MAX); area; + area = iopt_area_iter_next(area, 0, ULONG_MAX)) { + struct iopt_pages *pages = area->pages; + + if (WARN_ON(!pages)) + continue; + + mutex_lock(&pages->mutex); + if (area->storage_domain != domain) { + mutex_unlock(&pages->mutex); + continue; + } + area->storage_domain = storage_domain; + mutex_unlock(&pages->mutex); + } + + + iopt_unmap_domain(iopt, domain); + return; + } + + for (area = iopt_area_iter_first(iopt, 0, ULONG_MAX); area; + area = iopt_area_iter_next(area, 0, ULONG_MAX)) { + struct iopt_pages *pages = area->pages; + + if (WARN_ON(!pages)) + continue; + + mutex_lock(&pages->mutex); + interval_tree_remove(&area->pages_node, + &area->pages->domains_itree); + WARN_ON(area->storage_domain != domain); + area->storage_domain = NULL; + iopt_area_unfill_domain(area, pages, domain); + mutex_unlock(&pages->mutex); + } +} + +/** + * iopt_fill_domain() - Fill a domain with PFNs + * @iopt: io_pagetable to act on + * @domain: domain to fill + * + * Fill the domain with PFNs from every area in the iopt. On failure the domain + * is left unchanged. + */ +static int iopt_fill_domain(struct io_pagetable *iopt, + struct iommu_domain *domain) +{ + struct iopt_area *end_area; + struct iopt_area *area; + int rc; + + lockdep_assert_held(&iopt->iova_rwsem); + lockdep_assert_held_write(&iopt->domains_rwsem); + + for (area = iopt_area_iter_first(iopt, 0, ULONG_MAX); area; + area = iopt_area_iter_next(area, 0, ULONG_MAX)) { + struct iopt_pages *pages = area->pages; + + if (WARN_ON(!pages)) + continue; + + mutex_lock(&pages->mutex); + rc = iopt_area_fill_domain(area, domain); + if (rc) { + mutex_unlock(&pages->mutex); + goto out_unfill; + } + if (!area->storage_domain) { + WARN_ON(iopt->next_domain_id != 0); + area->storage_domain = domain; + interval_tree_insert(&area->pages_node, + &pages->domains_itree); + } + mutex_unlock(&pages->mutex); + } + return 0; + +out_unfill: + end_area = area; + for (area = iopt_area_iter_first(iopt, 0, ULONG_MAX); area; + area = iopt_area_iter_next(area, 0, ULONG_MAX)) { + struct iopt_pages *pages = area->pages; + + if (area == end_area) + break; + if (WARN_ON(!pages)) + continue; + mutex_lock(&pages->mutex); + if (iopt->next_domain_id == 0) { + interval_tree_remove(&area->pages_node, + &pages->domains_itree); + area->storage_domain = NULL; + } + iopt_area_unfill_domain(area, pages, domain); + mutex_unlock(&pages->mutex); + } + return rc; +} + +/* All existing area's conform to an increased page size */ +static int iopt_check_iova_alignment(struct io_pagetable *iopt, + unsigned long new_iova_alignment) +{ + struct iopt_area *area; + + lockdep_assert_held(&iopt->iova_rwsem); + + for (area = iopt_area_iter_first(iopt, 0, ULONG_MAX); area; + area = iopt_area_iter_next(area, 0, ULONG_MAX)) + if ((iopt_area_iova(area) % new_iova_alignment) || + (iopt_area_length(area) % new_iova_alignment)) + return -EADDRINUSE; + return 0; +} + +int iopt_table_add_domain(struct io_pagetable *iopt, + struct iommu_domain *domain) +{ + const struct iommu_domain_geometry *geometry = &domain->geometry; + struct iommu_domain *iter_domain; + unsigned int new_iova_alignment; + unsigned long index; + int rc; + + down_write(&iopt->domains_rwsem); + down_write(&iopt->iova_rwsem); + + xa_for_each (&iopt->domains, index, iter_domain) { + if (WARN_ON(iter_domain == domain)) { + rc = -EEXIST; + goto out_unlock; + } + } + + /* + * The io page size drives the iova_alignment. Internally the iopt_pages + * works in PAGE_SIZE units and we adjust when mapping sub-PAGE_SIZE + * objects into the iommu_domain. + * + * A iommu_domain must always be able to accept PAGE_SIZE to be + * compatible as we can't guarantee higher contiguity. + */ + new_iova_alignment = + max_t(unsigned long, 1UL << __ffs(domain->pgsize_bitmap), + iopt->iova_alignment); + if (new_iova_alignment > PAGE_SIZE) { + rc = -EINVAL; + goto out_unlock; + } + if (new_iova_alignment != iopt->iova_alignment) { + rc = iopt_check_iova_alignment(iopt, new_iova_alignment); + if (rc) + goto out_unlock; + } + + /* No area exists that is outside the allowed domain aperture */ + if (geometry->aperture_start != 0) { + rc = iopt_reserve_iova(iopt, 0, geometry->aperture_start - 1, + domain); + if (rc) + goto out_reserved; + } + if (geometry->aperture_end != ULONG_MAX) { + rc = iopt_reserve_iova(iopt, geometry->aperture_end + 1, + ULONG_MAX, domain); + if (rc) + goto out_reserved; + } + + rc = xa_reserve(&iopt->domains, iopt->next_domain_id, GFP_KERNEL); + if (rc) + goto out_reserved; + + rc = iopt_fill_domain(iopt, domain); + if (rc) + goto out_release; + + iopt->iova_alignment = new_iova_alignment; + xa_store(&iopt->domains, iopt->next_domain_id, domain, GFP_KERNEL); + iopt->next_domain_id++; + up_write(&iopt->iova_rwsem); + up_write(&iopt->domains_rwsem); + return 0; +out_release: + xa_release(&iopt->domains, iopt->next_domain_id); +out_reserved: + iopt_remove_reserved_iova(iopt, domain); +out_unlock: + up_write(&iopt->iova_rwsem); + up_write(&iopt->domains_rwsem); + return rc; +} + +void iopt_table_remove_domain(struct io_pagetable *iopt, + struct iommu_domain *domain) +{ + struct iommu_domain *iter_domain = NULL; + unsigned long new_iova_alignment; + unsigned long index; + + down_write(&iopt->domains_rwsem); + down_write(&iopt->iova_rwsem); + + xa_for_each (&iopt->domains, index, iter_domain) + if (iter_domain == domain) + break; + if (WARN_ON(iter_domain != domain) || index >= iopt->next_domain_id) + goto out_unlock; + + /* + * Compress the xarray to keep it linear by swapping the entry to erase + * with the tail entry and shrinking the tail. + */ + iopt->next_domain_id--; + iter_domain = xa_erase(&iopt->domains, iopt->next_domain_id); + if (index != iopt->next_domain_id) + xa_store(&iopt->domains, index, iter_domain, GFP_KERNEL); + + iopt_unfill_domain(iopt, domain); + iopt_remove_reserved_iova(iopt, domain); + + /* Recalculate the iova alignment without the domain */ + new_iova_alignment = 1; + xa_for_each (&iopt->domains, index, iter_domain) + new_iova_alignment = max_t(unsigned long, + 1UL << __ffs(domain->pgsize_bitmap), + new_iova_alignment); + if (!WARN_ON(new_iova_alignment > iopt->iova_alignment)) + iopt->iova_alignment = new_iova_alignment; + +out_unlock: + up_write(&iopt->iova_rwsem); + up_write(&iopt->domains_rwsem); +} + +/* Narrow the valid_iova_itree to include reserved ranges from a group. */ +int iopt_table_enforce_group_resv_regions(struct io_pagetable *iopt, + struct iommu_group *group, + phys_addr_t *sw_msi_start) +{ + struct iommu_resv_region *resv; + struct iommu_resv_region *tmp; + LIST_HEAD(group_resv_regions); + int rc; + + down_write(&iopt->iova_rwsem); + rc = iommu_get_group_resv_regions(group, &group_resv_regions); + if (rc) + goto out_unlock; + + list_for_each_entry (resv, &group_resv_regions, list) { + if (resv->type == IOMMU_RESV_DIRECT_RELAXABLE) + continue; + + /* + * The presence of any 'real' MSI regions should take precedence + * over the software-managed one if the IOMMU driver happens to + * advertise both types. + */ + if (sw_msi_start && resv->type == IOMMU_RESV_MSI) { + *sw_msi_start = 0; + sw_msi_start = NULL; + } + if (sw_msi_start && resv->type == IOMMU_RESV_SW_MSI) + *sw_msi_start = resv->start; + + rc = iopt_reserve_iova(iopt, resv->start, + resv->length - 1 + resv->start, group); + if (rc) + goto out_reserved; + } + rc = 0; + goto out_free_resv; + +out_reserved: + iopt_remove_reserved_iova(iopt, group); +out_free_resv: + list_for_each_entry_safe (resv, tmp, &group_resv_regions, list) + kfree(resv); +out_unlock: + up_write(&iopt->iova_rwsem); + return rc; +} diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 2f1301d39bba7c..bcf08e61bc87e9 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -9,6 +9,9 @@ #include #include +struct iommu_domain; +struct iommu_group; + /* * The IOVA to PFN map. The mapper automatically copies the PFNs into multiple * domains and permits sharing of PFNs between io_pagetable instances. This @@ -27,8 +30,40 @@ struct io_pagetable { struct rw_semaphore iova_rwsem; struct rb_root_cached area_itree; struct rb_root_cached reserved_iova_itree; + unsigned long iova_alignment; }; +int iopt_init_table(struct io_pagetable *iopt); +void iopt_destroy_table(struct io_pagetable *iopt); +struct iopt_pages *iopt_get_pages(struct io_pagetable *iopt, unsigned long iova, + unsigned long *start_byte, + unsigned long length); +enum { IOPT_ALLOC_IOVA = 1 << 0 }; +int iopt_map_user_pages(struct io_pagetable *iopt, unsigned long *iova, + void __user *uptr, unsigned long length, int iommu_prot, + unsigned int flags); +int iopt_map_pages(struct io_pagetable *iopt, struct iopt_pages *pages, + unsigned long *dst_iova, unsigned long start_byte, + unsigned long length, int iommu_prot, unsigned int flags); +int iopt_unmap_iova(struct io_pagetable *iopt, unsigned long iova, + unsigned long length); +int iopt_unmap_all(struct io_pagetable *iopt); + +int iopt_access_pages(struct io_pagetable *iopt, unsigned long iova, + unsigned long npages, struct page **out_pages, bool write); +void iopt_unaccess_pages(struct io_pagetable *iopt, unsigned long iova, + size_t npages); +int iopt_table_add_domain(struct io_pagetable *iopt, + struct iommu_domain *domain); +void iopt_table_remove_domain(struct io_pagetable *iopt, + struct iommu_domain *domain); +int iopt_table_enforce_group_resv_regions(struct io_pagetable *iopt, + struct iommu_group *group, + phys_addr_t *sw_msi_start); +int iopt_reserve_iova(struct io_pagetable *iopt, unsigned long start, + unsigned long last, void *owner); +void iopt_remove_reserved_iova(struct io_pagetable *iopt, void *owner); + struct iommufd_ctx { struct file *filp; struct xarray objects; From patchwork Fri Mar 18 17:27:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEE5FC4332F for ; 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This exposes most of the functionality in the io_pagetable to userspace. This is intended to be the core of the generic interface that IOMMUFD will provide. Every IOMMU driver should be able to implement an iommu_domain that is compatible with this generic mechanism. It is also designed to be easy to use for simple non virtual machine monitor users, like DPDK: - Universal simple support for all IOMMUs (no PPC special path) - An IOVA allocator that considerds the aperture and the reserved ranges - io_pagetable allows any number of iommu_domains to be connected to the IOAS Along with room in the design to add non-generic features to cater to specific HW functionality. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommufd/Makefile | 1 + drivers/iommu/iommufd/ioas.c | 248 ++++++++++++++++++++++++ drivers/iommu/iommufd/iommufd_private.h | 27 +++ drivers/iommu/iommufd/main.c | 17 ++ include/uapi/linux/iommufd.h | 132 +++++++++++++ 5 files changed, 425 insertions(+) create mode 100644 drivers/iommu/iommufd/ioas.c diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index b66a8c47ff55ec..2b4f36f1b72f9d 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only iommufd-y := \ io_pagetable.o \ + ioas.o \ main.o \ pages.o diff --git a/drivers/iommu/iommufd/ioas.c b/drivers/iommu/iommufd/ioas.c new file mode 100644 index 00000000000000..c530b2ba74b06b --- /dev/null +++ b/drivers/iommu/iommufd/ioas.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES + */ +#include +#include +#include +#include + +#include "io_pagetable.h" + +void iommufd_ioas_destroy(struct iommufd_object *obj) +{ + struct iommufd_ioas *ioas = container_of(obj, struct iommufd_ioas, obj); + int rc; + + rc = iopt_unmap_all(&ioas->iopt); + WARN_ON(rc); + iopt_destroy_table(&ioas->iopt); +} + +struct iommufd_ioas *iommufd_ioas_alloc(struct iommufd_ctx *ictx) +{ + struct iommufd_ioas *ioas; + int rc; + + ioas = iommufd_object_alloc(ictx, ioas, IOMMUFD_OBJ_IOAS); + if (IS_ERR(ioas)) + return ioas; + + rc = iopt_init_table(&ioas->iopt); + if (rc) + goto out_abort; + return ioas; + +out_abort: + iommufd_object_abort(ictx, &ioas->obj); + return ERR_PTR(rc); +} + +int iommufd_ioas_alloc_ioctl(struct iommufd_ucmd *ucmd) +{ + struct iommu_ioas_alloc *cmd = ucmd->cmd; + struct iommufd_ioas *ioas; + int rc; + + if (cmd->flags) + return -EOPNOTSUPP; + + ioas = iommufd_ioas_alloc(ucmd->ictx); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + + cmd->out_ioas_id = ioas->obj.id; + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + if (rc) + goto out_table; + iommufd_object_finalize(ucmd->ictx, &ioas->obj); + return 0; + +out_table: + iommufd_ioas_destroy(&ioas->obj); + return rc; +} + +int iommufd_ioas_iova_ranges(struct iommufd_ucmd *ucmd) +{ + struct iommu_ioas_iova_ranges __user *uptr = ucmd->ubuffer; + struct iommu_ioas_iova_ranges *cmd = ucmd->cmd; + struct iommufd_ioas *ioas; + struct interval_tree_span_iter span; + u32 max_iovas; + int rc; + + if (cmd->__reserved) + return -EOPNOTSUPP; + + max_iovas = cmd->size - sizeof(*cmd); + if (max_iovas % sizeof(cmd->out_valid_iovas[0])) + return -EINVAL; + max_iovas /= sizeof(cmd->out_valid_iovas[0]); + + ioas = iommufd_get_ioas(ucmd, cmd->ioas_id); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + + down_read(&ioas->iopt.iova_rwsem); + cmd->out_num_iovas = 0; + for (interval_tree_span_iter_first( + &span, &ioas->iopt.reserved_iova_itree, 0, ULONG_MAX); + !interval_tree_span_iter_done(&span); + interval_tree_span_iter_next(&span)) { + if (!span.is_hole) + continue; + if (cmd->out_num_iovas < max_iovas) { + rc = put_user((u64)span.start_hole, + &uptr->out_valid_iovas[cmd->out_num_iovas] + .start); + if (rc) + goto out_put; + rc = put_user( + (u64)span.last_hole, + &uptr->out_valid_iovas[cmd->out_num_iovas].last); + if (rc) + goto out_put; + } + cmd->out_num_iovas++; + } + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + if (rc) + goto out_put; + if (cmd->out_num_iovas > max_iovas) + rc = -EMSGSIZE; +out_put: + up_read(&ioas->iopt.iova_rwsem); + iommufd_put_object(&ioas->obj); + return rc; +} + +static int conv_iommu_prot(u32 map_flags) +{ + int iommu_prot; + + /* + * We provide no manual cache coherency ioctls to userspace and most + * architectures make the CPU ops for cache flushing privileged. + * Therefore we require the underlying IOMMU to support CPU coherent + * operation. + */ + iommu_prot = IOMMU_CACHE; + if (map_flags & IOMMU_IOAS_MAP_WRITEABLE) + iommu_prot |= IOMMU_WRITE; + if (map_flags & IOMMU_IOAS_MAP_READABLE) + iommu_prot |= IOMMU_READ; + return iommu_prot; +} + +int iommufd_ioas_map(struct iommufd_ucmd *ucmd) +{ + struct iommu_ioas_map *cmd = ucmd->cmd; + struct iommufd_ioas *ioas; + unsigned int flags = 0; + unsigned long iova; + int rc; + + if ((cmd->flags & + ~(IOMMU_IOAS_MAP_FIXED_IOVA | IOMMU_IOAS_MAP_WRITEABLE | + IOMMU_IOAS_MAP_READABLE)) || + cmd->__reserved) + return -EOPNOTSUPP; + if (cmd->iova >= ULONG_MAX || cmd->length >= ULONG_MAX) + return -EOVERFLOW; + + ioas = iommufd_get_ioas(ucmd, cmd->ioas_id); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + + if (!(cmd->flags & IOMMU_IOAS_MAP_FIXED_IOVA)) + flags = IOPT_ALLOC_IOVA; + iova = cmd->iova; + rc = iopt_map_user_pages(&ioas->iopt, &iova, + u64_to_user_ptr(cmd->user_va), cmd->length, + conv_iommu_prot(cmd->flags), flags); + if (rc) + goto out_put; + + cmd->iova = iova; + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); +out_put: + iommufd_put_object(&ioas->obj); + return rc; +} + +int iommufd_ioas_copy(struct iommufd_ucmd *ucmd) +{ + struct iommu_ioas_copy *cmd = ucmd->cmd; + struct iommufd_ioas *src_ioas; + struct iommufd_ioas *dst_ioas; + struct iopt_pages *pages; + unsigned int flags = 0; + unsigned long iova; + unsigned long start_byte; + int rc; + + if ((cmd->flags & + ~(IOMMU_IOAS_MAP_FIXED_IOVA | IOMMU_IOAS_MAP_WRITEABLE | + IOMMU_IOAS_MAP_READABLE))) + return -EOPNOTSUPP; + if (cmd->length >= ULONG_MAX) + return -EOVERFLOW; + + src_ioas = iommufd_get_ioas(ucmd, cmd->src_ioas_id); + if (IS_ERR(src_ioas)) + return PTR_ERR(src_ioas); + /* FIXME: copy is not limited to an exact match anymore */ + pages = iopt_get_pages(&src_ioas->iopt, cmd->src_iova, &start_byte, + cmd->length); + iommufd_put_object(&src_ioas->obj); + if (IS_ERR(pages)) + return PTR_ERR(pages); + + dst_ioas = iommufd_get_ioas(ucmd, cmd->dst_ioas_id); + if (IS_ERR(dst_ioas)) { + iopt_put_pages(pages); + return PTR_ERR(dst_ioas); + } + + if (!(cmd->flags & IOMMU_IOAS_MAP_FIXED_IOVA)) + flags = IOPT_ALLOC_IOVA; + iova = cmd->dst_iova; + rc = iopt_map_pages(&dst_ioas->iopt, pages, &iova, start_byte, + cmd->length, conv_iommu_prot(cmd->flags), flags); + if (rc) { + iopt_put_pages(pages); + goto out_put_dst; + } + + cmd->dst_iova = iova; + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); +out_put_dst: + iommufd_put_object(&dst_ioas->obj); + return rc; +} + +int iommufd_ioas_unmap(struct iommufd_ucmd *ucmd) +{ + struct iommu_ioas_unmap *cmd = ucmd->cmd; + struct iommufd_ioas *ioas; + int rc; + + ioas = iommufd_get_ioas(ucmd, cmd->ioas_id); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + + if (cmd->iova == 0 && cmd->length == U64_MAX) { + rc = iopt_unmap_all(&ioas->iopt); + } else { + if (cmd->iova >= ULONG_MAX || cmd->length >= ULONG_MAX) { + rc = -EOVERFLOW; + goto out_put; + } + rc = iopt_unmap_iova(&ioas->iopt, cmd->iova, cmd->length); + } + +out_put: + iommufd_put_object(&ioas->obj); + return rc; +} diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index bcf08e61bc87e9..d24c9dac5a82a9 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -96,6 +96,7 @@ static inline int iommufd_ucmd_respond(struct iommufd_ucmd *ucmd, enum iommufd_object_type { IOMMUFD_OBJ_NONE, IOMMUFD_OBJ_ANY = IOMMUFD_OBJ_NONE, + IOMMUFD_OBJ_IOAS, IOMMUFD_OBJ_MAX, }; @@ -147,4 +148,30 @@ struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, type), \ typeof(*(ptr)), obj) +/* + * The IO Address Space (IOAS) pagetable is a virtual page table backed by the + * io_pagetable object. It is a user controlled mapping of IOVA -> PFNs. The + * mapping is copied into all of the associated domains and made available to + * in-kernel users. + */ +struct iommufd_ioas { + struct iommufd_object obj; + struct io_pagetable iopt; +}; + +static inline struct iommufd_ioas *iommufd_get_ioas(struct iommufd_ucmd *ucmd, + u32 id) +{ + return container_of(iommufd_get_object(ucmd->ictx, id, + IOMMUFD_OBJ_IOAS), + struct iommufd_ioas, obj); +} + +struct iommufd_ioas *iommufd_ioas_alloc(struct iommufd_ctx *ictx); +int iommufd_ioas_alloc_ioctl(struct iommufd_ucmd *ucmd); +void iommufd_ioas_destroy(struct iommufd_object *obj); +int iommufd_ioas_iova_ranges(struct iommufd_ucmd *ucmd); +int iommufd_ioas_map(struct iommufd_ucmd *ucmd); +int iommufd_ioas_copy(struct iommufd_ucmd *ucmd); +int iommufd_ioas_unmap(struct iommufd_ucmd *ucmd); #endif diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index ae8db2f663004f..e506f493b54cfe 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -184,6 +184,10 @@ static int iommufd_fops_release(struct inode *inode, struct file *filp) } union ucmd_buffer { + struct iommu_ioas_alloc alloc; + struct iommu_ioas_iova_ranges iova_ranges; + struct iommu_ioas_map map; + struct iommu_ioas_unmap unmap; struct iommu_destroy destroy; }; @@ -205,6 +209,16 @@ struct iommufd_ioctl_op { } static struct iommufd_ioctl_op iommufd_ioctl_ops[] = { IOCTL_OP(IOMMU_DESTROY, iommufd_destroy, struct iommu_destroy, id), + IOCTL_OP(IOMMU_IOAS_ALLOC, iommufd_ioas_alloc_ioctl, + struct iommu_ioas_alloc, out_ioas_id), + IOCTL_OP(IOMMU_IOAS_COPY, iommufd_ioas_copy, struct iommu_ioas_copy, + src_iova), + IOCTL_OP(IOMMU_IOAS_IOVA_RANGES, iommufd_ioas_iova_ranges, + struct iommu_ioas_iova_ranges, __reserved), + IOCTL_OP(IOMMU_IOAS_MAP, iommufd_ioas_map, struct iommu_ioas_map, + __reserved), + IOCTL_OP(IOMMU_IOAS_UNMAP, iommufd_ioas_unmap, struct iommu_ioas_unmap, + length), }; static long iommufd_fops_ioctl(struct file *filp, unsigned int cmd, @@ -270,6 +284,9 @@ struct iommufd_ctx *iommufd_fget(int fd) } static struct iommufd_object_ops iommufd_object_ops[] = { + [IOMMUFD_OBJ_IOAS] = { + .destroy = iommufd_ioas_destroy, + }, }; static struct miscdevice iommu_misc_dev = { diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 2f7f76ec6db4cb..ba7b17ec3002e3 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -37,6 +37,11 @@ enum { IOMMUFD_CMD_BASE = 0x80, IOMMUFD_CMD_DESTROY = IOMMUFD_CMD_BASE, + IOMMUFD_CMD_IOAS_ALLOC, + IOMMUFD_CMD_IOAS_IOVA_RANGES, + IOMMUFD_CMD_IOAS_MAP, + IOMMUFD_CMD_IOAS_COPY, + IOMMUFD_CMD_IOAS_UNMAP, }; /** @@ -52,4 +57,131 @@ struct iommu_destroy { }; #define IOMMU_DESTROY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DESTROY) +/** + * struct iommu_ioas_alloc - ioctl(IOMMU_IOAS_ALLOC) + * @size: sizeof(struct iommu_ioas_alloc) + * @flags: Must be 0 + * @out_ioas_id: Output IOAS ID for the allocated object + * + * Allocate an IO Address Space (IOAS) which holds an IO Virtual Address (IOVA) + * to memory mapping. + */ +struct iommu_ioas_alloc { + __u32 size; + __u32 flags; + __u32 out_ioas_id; +}; +#define IOMMU_IOAS_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_ALLOC) + +/** + * struct iommu_ioas_iova_ranges - ioctl(IOMMU_IOAS_IOVA_RANGES) + * @size: sizeof(struct iommu_ioas_iova_ranges) + * @ioas_id: IOAS ID to read ranges from + * @out_num_iovas: Output total number of ranges in the IOAS + * @__reserved: Must be 0 + * @out_valid_iovas: Array of valid IOVA ranges. The array length is the smaller + * of out_num_iovas or the length implied by size. + * @out_valid_iovas.start: First IOVA in the allowed range + * @out_valid_iovas.last: Inclusive last IOVA in the allowed range + * + * Query an IOAS for ranges of allowed IOVAs. Operation outside these ranges is + * not allowed. out_num_iovas will be set to the total number of iovas + * and the out_valid_iovas[] will be filled in as space permits. + * size should include the allocated flex array. + */ +struct iommu_ioas_iova_ranges { + __u32 size; + __u32 ioas_id; + __u32 out_num_iovas; + __u32 __reserved; + struct iommu_valid_iovas { + __aligned_u64 start; + __aligned_u64 last; + } out_valid_iovas[]; +}; +#define IOMMU_IOAS_IOVA_RANGES _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_IOVA_RANGES) + +/** + * enum iommufd_ioas_map_flags - Flags for map and copy + * @IOMMU_IOAS_MAP_FIXED_IOVA: If clear the kernel will compute an appropriate + * IOVA to place the mapping at + * @IOMMU_IOAS_MAP_WRITEABLE: DMA is allowed to write to this mapping + * @IOMMU_IOAS_MAP_READABLE: DMA is allowed to read from this mapping + */ +enum iommufd_ioas_map_flags { + IOMMU_IOAS_MAP_FIXED_IOVA = 1 << 0, + IOMMU_IOAS_MAP_WRITEABLE = 1 << 1, + IOMMU_IOAS_MAP_READABLE = 1 << 2, +}; + +/** + * struct iommu_ioas_map - ioctl(IOMMU_IOAS_MAP) + * @size: sizeof(struct iommu_ioas_map) + * @flags: Combination of enum iommufd_ioas_map_flags + * @ioas_id: IOAS ID to change the mapping of + * @__reserved: Must be 0 + * @user_va: Userspace pointer to start mapping from + * @length: Number of bytes to map + * @iova: IOVA the mapping was placed at. If IOMMU_IOAS_MAP_FIXED_IOVA is set + * then this must be provided as input. + * + * Set an IOVA mapping from a user pointer. If FIXED_IOVA is specified then the + * mapping will be established at iova, otherwise a suitable location will be + * automatically selected and returned in iova. + */ +struct iommu_ioas_map { + __u32 size; + __u32 flags; + __u32 ioas_id; + __u32 __reserved; + __aligned_u64 user_va; + __aligned_u64 length; + __aligned_u64 iova; +}; +#define IOMMU_IOAS_MAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_MAP) + +/** + * struct iommu_ioas_copy - ioctl(IOMMU_IOAS_COPY) + * @size: sizeof(struct iommu_ioas_copy) + * @flags: Combination of enum iommufd_ioas_map_flags + * @dst_ioas_id: IOAS ID to change the mapping of + * @src_ioas_id: IOAS ID to copy from + * @length: Number of bytes to copy and map + * @dst_iova: IOVA the mapping was placed at. If IOMMU_IOAS_MAP_FIXED_IOVA is + * set then this must be provided as input. + * @src_iova: IOVA to start the copy + * + * Copy an already existing mapping from src_ioas_id and establish it in + * dst_ioas_id. The src iova/length must exactly match a range used with + * IOMMU_IOAS_MAP. + */ +struct iommu_ioas_copy { + __u32 size; + __u32 flags; + __u32 dst_ioas_id; + __u32 src_ioas_id; + __aligned_u64 length; + __aligned_u64 dst_iova; + __aligned_u64 src_iova; +}; +#define IOMMU_IOAS_COPY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_COPY) + +/** + * struct iommu_ioas_unmap - ioctl(IOMMU_IOAS_UNMAP) + * @size: sizeof(struct iommu_ioas_copy) + * @ioas_id: IOAS ID to change the mapping of + * @iova: IOVA to start the unmapping at + * @length: Number of bytes to unmap + * + * Unmap an IOVA range. The iova/length must exactly match a range + * used with IOMMU_IOAS_PAGETABLE_MAP, or be the values 0 & U64_MAX. + * In the latter case all IOVAs will be unmaped. + */ +struct iommu_ioas_unmap { + __u32 size; + __u32 ioas_id; + __aligned_u64 iova; + __aligned_u64 length; +}; +#define IOMMU_IOAS_UNMAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_UNMAP) #endif From patchwork Fri Mar 18 17:27:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D955C4332F for ; Fri, 18 Mar 2022 17:27:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239638AbiCRR3L (ORCPT ); Fri, 18 Mar 2022 13:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239636AbiCRR3K (ORCPT ); Fri, 18 Mar 2022 13:29:10 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2074.outbound.protection.outlook.com [40.107.93.74]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E877320C19E for ; Fri, 18 Mar 2022 10:27:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=K1peycVRxBYRPofDFeialPeZYvdEf6XU46lBI2NAqmNXh2pMSbczW7GCP077mM/AIlzUns7BGFYvlwnNLzT7X4HdOo6HBAi7h/2uSeIIoDESEKNt5mp4CRRdR9MjgxF24POfrLVrkQWKe6AIc6D7DG1QFC+j/dRvmaL5xnvRMEcxoVfYYSqAP6ar6+WxZDZlEVH82hS8bceFW6DVnQUNMJ1NZlkgwPyPKlQOjxPdt5AASYhEmI/f3Gx4PyvBzHZ6Zlio8pDi5euGEF/W5BSkqrmkL3vfZ9Xai58R5tjIebwphZ/pPmA/IRJd/KQMzbtkwRT882SsNVcpKYy0Gf4/Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=eBhljm885tuF+r13knAd8C5boMj48iH8g6P3EMq7lWA=; b=Qq3InIocfcn35TaxpOcD4FT13zPAi9WanOqO764WJZhjMR3TQDidT5kd5Tbq/5ZF3Ur2awlquoJQeVQFdLMpumMrus5eoeGPhPsQQahlOKezr6kveE4xNvX0MxGk3xsyBcvDQq8uMEO+wAZ/iPdueSvWUYZVil10FPZXOVcfrdHi9FuGyaT/8MB9FVDTfKuDIeYFxMlsqOG2ElinSHILMSBfIJxHEQNhQzjjIoCOgRnsNzkxqueN/zYa3wyPGCymgRQtDm4Roe4wWWjKgm1D265kYOu5QQGJJ1Z3/GbuFVnzepUEadE/0l+dmPnNOSuaYlNwtsBwj6FmmN9FOYfcaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eBhljm885tuF+r13knAd8C5boMj48iH8g6P3EMq7lWA=; b=sL3pP8bsTqND/kNqgbXJg4F7S02YpnVoXGfvbGu7Ak1jS8cS54jB7wpRRaTZMcV0Xc0Hax/erwy4YIOqQeO+ZMZCuTF7gwAK3wL0NX5q/3uhZHR2Rr20fsOf+DVUJFsZHpJrQ3Sa5eiIyIuTP/n8VU3eOabV+Q+tZXBLXswTbCqGROj2W0MIk+pUBsY+Ab3CeiBI4PWnswoX/0P77+OzTMjrT3QKel/2u4smz5A53et9uMZERo/NNu9QEYBOnLvNQ7CdFMaNd2RmvGPBguqZ0cu8xj9mDa3zQIhowuM9WiBRfWFVhv9HJwmztvZaH+XYIkbAQynNn6h6eFPyJ9kZjQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by MN2PR12MB3951.namprd12.prod.outlook.com (2603:10b6:208:16b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.14; Fri, 18 Mar 2022 17:27:44 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c%5]) with mapi id 15.20.5081.018; Fri, 18 Mar 2022 17:27:44 +0000 From: Jason Gunthorpe Cc: Alex Williamson , Lu Baolu , Chaitanya Kulkarni , Cornelia Huck , Daniel Jordan , David Gibson , Eric Auger , iommu@lists.linux-foundation.org, Jason Wang , Jean-Philippe Brucker , Joao Martins , Kevin Tian , kvm@vger.kernel.org, Matthew Rosato , "Michael S. Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 09/12] iommufd: Add a HW pagetable object Date: Fri, 18 Mar 2022 14:27:34 -0300 Message-Id: <9-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR19CA0059.namprd19.prod.outlook.com (2603:10b6:208:19b::36) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0bd1f63b-dd01-4b3f-4eac-08da09049a7a X-MS-TrafficTypeDiagnostic: MN2PR12MB3951:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2sDi9ZMNho4StKQRCmLuA1HOKi3tiFSi5hDCFvZpgVGm+5EdsK4sF2uom1SxXk4wiVBQOSpf95JSMEMOH+QqnRN9hv+9moRigkQsczRMA77wuhzKCha61t5i4TMM23+GGfGSJUAczra2p3MiVuIKn8qsHOKa+VSJcHvgAT/qcczjkiNxw3jwOUx/PXpkf+3bOMjtu6wydU8lVSsyy/311z8y8RSpC8ZBeVn8RbR0i29NzUe4XbeC0b5FuWlCGHNO/k0QVVkO7oNJ7YgiACDHm6u3jQuoMFrDE8HpGzZa5o0UAddsK0eIq3iUu+qwZlVo04lzK6QSvhzlgRVp1ELRcCpRj4/6wOoJ5R5qxSe75461YAZs8n6VqHtihsQR6b6OxF/iJj8afuUbXTBGpVWOoooSguAFX7l59TRd+sNM0gCbCKD43aol5EBVsYYgLpmTSo4Kt4rnM61Zk0ACe7YReiGz5p3KMAb/wTVGwPUGP7moB1dzFvf9mAf4ad02yL6jQ/9fBKkSIo6z89pT/vaK5piUGdD2WtDKRSNNISalMjrqWRom0zrMl95RWfjYo1pGyhBcgTG6IUv431S1j40BFEYpUKarRL2b4x7vxQQeeZLHiKbXb7pybw33CGu91yqQ4nAoxfM0dLLgPtpTyioJlY+b5hv9TwH4whHustYDQ7ijuEYvVehDuJnb0Y14IJBx+HXFLJsGk2+VMd9M/xepMg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(83380400001)(7416002)(4326008)(2906002)(86362001)(508600001)(8676002)(6512007)(6506007)(6666004)(5660300002)(8936002)(109986005)(66946007)(26005)(66476007)(186003)(316002)(66556008)(2616005)(36756003)(38100700002)(6486002)(54906003)(4216001)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CUC4JDdRSDt7uqbCy6FFhwP8H+HcL9Ndf9w/CtsDdurxntbc95xOMEHciA2HgD0dKXsbLvK9wOPv1otWLlg3CNGn2kzB2zpDFeryybL2Xl4pjN31B+ptVe4VcnElErCj5Ttju41W48XaxQ1+FgUHs6xrshfykL4UfWuSfwSPQShmpSrQ7bpL9MZdp1z36Mp8fFzOEUGQ1VxmT8hP6ryQgRFow5mqmHnzP8LLHWYm328QMIzg8q5HTVUFx4IiblYSP09SKra/1cicupCIEMfH1kz66B0JN7NKnx9lRUStFjlen1vd/gStcMPnhCCHc2E2kaNK2lMlGuVsw7n5RTXCuzVTuQRouy46WhpZMZ0Y+mfX2nUKi8gVLCwdXiabdCQc8uhekTzgwdlIIP2i9qD84RMaQWBjC8w6gF6H8sk4dkPcyG/UGRl8k/OPfCZBuEtDWLMtR3DmicpN1PADR0xOfNFVHoQfB7p5ht8tF8XUZz8fsNkzWQUwpPhdzRfyn1sZqR2kgcygMMS0hyYKsdruf3GUEJXJcf/RDu6Oo4nJDnvlD0VFjdF5/C/gCi4+Lio/OCXsKdmQtlXkkj39l41i3atRjS/GT2v0e2faWAtCG3ahiNlbOBkci84fRW6Dry/RxtkJ2lZBrhRyyeRrzN5X+9xSe8sBeJxab8c/rm+SOlKQRfAe6L40zhdz8Z35GPVmVu0GlOdj8aoT4LxrZ/7yIz9T7fLFBoLEaAYWmtXLRcBxd8nNJxajkDMfBnbnDx5fzZMLtxFf6pY4gGT6rEuHA9WnOohzyvCvasHlwL7vFoR7gXnGgjjrNdr+YJrTXJdm9QjOXAukF5A0rW+l+HDhlX0jkOfaGs1rFkMmlqPiBA5jmCuE1DYGJ07Q8lihu5DJOHo89u/Di/a+lWxKYH9e3qjhsA9hmxleEi0uDKYTmHATZgeT1DYkcaLQrtJB027eg2GBJDzX5YjTO0V3kSjdb5tyGw1+hv1LxLt1lcO6R7zTGOkZygTKcgZJYR/lFbBAGIJ4t+Tx0t5WI1+P7v6Sz1db4EtRHH0DLebmrRTIrgWqg424tyYTYIWYWNMv5XgLqIKcq9Vh3bxQcgCL9NUcpJfnCFiAggqIC/+3po8xp3YluztPC9mHZLZzVL087u9cek5/g0kG1lcI5fpAWhLojeCopq0OJfq8IpO/U6HeHQwU0bsHDjbEBBogWMYvdfo4+8d9fQbkfav3lfU+CuF9Og80PCbrisCFhYN1Vy980od9LaGVcHBFt9oDshG2Q4IYWai6jCEka69I04z89Gzis1/LeeZF8Ebj5zf9jfrEXNg+VaOc82BW+CCSUgM3tb4WOwckseiMv+V1W/GjM3T+ZsuNMAkPBPseCm3Ng74j9RstCNsYDsVMyHguixQFYRkryr0milIlZP+grJoeTeoP3bZ2DtWL/1GYEU+kBD3B1IIQQB6bwNIDpFde2Ghxp0HG X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0bd1f63b-dd01-4b3f-4eac-08da09049a7a X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:40.4603 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5Rv+JnpVvkSAsVMIgF9iebYrYkVV/Vja4fm4x5iiNnUzVvHDHVSO0Xse6lwV9jHO X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3951 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The hw_pagetable object exposes the internal struct iommu_domain's to userspace. An iommu_domain is required when any DMA device attaches to an IOAS to control the io page table through the iommu driver. For compatibility with VFIO the hw_pagetable is automatically created when a DMA device is attached to the IOAS. If a compatible iommu_domain already exists then the hw_pagetable associated with it is used for the attachment. In the initial series there is no iommufd uAPI for the hw_pagetable object. The next patch provides driver facing APIs for IO page table attachment that allows drivers to accept either an IOAS or a hw_pagetable ID and for the driver to return the hw_pagetable ID that was auto-selected from an IOAS. The expectation is the driver will provide uAPI through its own FD for attaching its device to iommufd. This allows userspace to learn the mapping of devices to iommu_domains and to override the automatic attachment. The future HW specific interface will allow userspace to create hw_pagetable objects using iommu_domains with IOMMU driver specific parameters. This infrastructure will allow linking those domains to IOAS's and devices. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommufd/Makefile | 1 + drivers/iommu/iommufd/hw_pagetable.c | 142 ++++++++++++++++++++++++ drivers/iommu/iommufd/ioas.c | 4 + drivers/iommu/iommufd/iommufd_private.h | 35 ++++++ drivers/iommu/iommufd/main.c | 3 + 5 files changed, 185 insertions(+) create mode 100644 drivers/iommu/iommufd/hw_pagetable.c diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index 2b4f36f1b72f9d..e13e971aa28c60 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only iommufd-y := \ + hw_pagetable.o \ io_pagetable.o \ ioas.o \ main.o \ diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c new file mode 100644 index 00000000000000..bafd7d07918bfd --- /dev/null +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES + */ +#include + +#include "iommufd_private.h" + +void iommufd_hw_pagetable_destroy(struct iommufd_object *obj) +{ + struct iommufd_hw_pagetable *hwpt = + container_of(obj, struct iommufd_hw_pagetable, obj); + struct iommufd_ioas *ioas = hwpt->ioas; + + WARN_ON(!list_empty(&hwpt->devices)); + mutex_lock(&ioas->mutex); + list_del(&hwpt->auto_domains_item); + mutex_unlock(&ioas->mutex); + + iommu_domain_free(hwpt->domain); + refcount_dec(&hwpt->ioas->obj.users); + mutex_destroy(&hwpt->devices_lock); +} + +/* + * When automatically managing the domains we search for a compatible domain in + * the iopt and if one is found use it, otherwise create a new domain. + * Automatic domain selection will never pick a manually created domain. + */ +static struct iommufd_hw_pagetable * +iommufd_hw_pagetable_auto_get(struct iommufd_ctx *ictx, + struct iommufd_ioas *ioas, struct device *dev) +{ + struct iommufd_hw_pagetable *hwpt; + int rc; + + /* + * There is no differentiation when domains are allocated, so any domain + * from the right ops is interchangeable with any other. + */ + mutex_lock(&ioas->mutex); + list_for_each_entry (hwpt, &ioas->auto_domains, auto_domains_item) { + /* + * FIXME: We really need an op from the driver to test if a + * device is compatible with a domain. This thing from VFIO + * works sometimes. + */ + if (hwpt->domain->ops == dev_iommu_ops(dev)->default_domain_ops) { + if (refcount_inc_not_zero(&hwpt->obj.users)) { + mutex_unlock(&ioas->mutex); + return hwpt; + } + } + } + + hwpt = iommufd_object_alloc(ictx, hwpt, IOMMUFD_OBJ_HW_PAGETABLE); + if (IS_ERR(hwpt)) { + rc = PTR_ERR(hwpt); + goto out_unlock; + } + + hwpt->domain = iommu_domain_alloc(dev->bus); + if (!hwpt->domain) { + rc = -ENOMEM; + goto out_abort; + } + + INIT_LIST_HEAD(&hwpt->devices); + mutex_init(&hwpt->devices_lock); + hwpt->ioas = ioas; + /* The calling driver is a user until iommufd_hw_pagetable_put() */ + refcount_inc(&ioas->obj.users); + + list_add_tail(&hwpt->auto_domains_item, &ioas->auto_domains); + /* + * iommufd_object_finalize() consumes the refcount, get one for the + * caller. This pairs with the first put in + * iommufd_object_destroy_user() + */ + refcount_inc(&hwpt->obj.users); + iommufd_object_finalize(ictx, &hwpt->obj); + + mutex_unlock(&ioas->mutex); + return hwpt; + +out_abort: + iommufd_object_abort(ictx, &hwpt->obj); +out_unlock: + mutex_unlock(&ioas->mutex); + return ERR_PTR(rc); +} + +/** + * iommufd_hw_pagetable_from_id() - Get an iommu_domain for a device + * @ictx: iommufd context + * @pt_id: ID of the IOAS or hw_pagetable object + * @dev: Device to get an iommu_domain for + * + * Turn a general page table ID into an iommu_domain contained in a + * iommufd_hw_pagetable object. If a hw_pagetable ID is specified then that + * iommu_domain is used, otherwise a suitable iommu_domain in the IOAS is found + * for the device, creating one automatically if necessary. + */ +struct iommufd_hw_pagetable * +iommufd_hw_pagetable_from_id(struct iommufd_ctx *ictx, u32 pt_id, + struct device *dev) +{ + struct iommufd_object *obj; + + obj = iommufd_get_object(ictx, pt_id, IOMMUFD_OBJ_ANY); + if (IS_ERR(obj)) + return ERR_CAST(obj); + + switch (obj->type) { + case IOMMUFD_OBJ_HW_PAGETABLE: + iommufd_put_object_keep_user(obj); + return container_of(obj, struct iommufd_hw_pagetable, obj); + case IOMMUFD_OBJ_IOAS: { + struct iommufd_ioas *ioas = + container_of(obj, struct iommufd_ioas, obj); + struct iommufd_hw_pagetable *hwpt; + + hwpt = iommufd_hw_pagetable_auto_get(ictx, ioas, dev); + iommufd_put_object(obj); + return hwpt; + } + default: + iommufd_put_object(obj); + return ERR_PTR(-EINVAL); + } +} + +void iommufd_hw_pagetable_put(struct iommufd_ctx *ictx, + struct iommufd_hw_pagetable *hwpt) +{ + if (list_empty(&hwpt->auto_domains_item)) { + /* Manually created hw_pagetables just keep going */ + refcount_dec(&hwpt->obj.users); + return; + } + iommufd_object_destroy_user(ictx, &hwpt->obj); +} diff --git a/drivers/iommu/iommufd/ioas.c b/drivers/iommu/iommufd/ioas.c index c530b2ba74b06b..48149988c84bbc 100644 --- a/drivers/iommu/iommufd/ioas.c +++ b/drivers/iommu/iommufd/ioas.c @@ -17,6 +17,7 @@ void iommufd_ioas_destroy(struct iommufd_object *obj) rc = iopt_unmap_all(&ioas->iopt); WARN_ON(rc); iopt_destroy_table(&ioas->iopt); + mutex_destroy(&ioas->mutex); } struct iommufd_ioas *iommufd_ioas_alloc(struct iommufd_ctx *ictx) @@ -31,6 +32,9 @@ struct iommufd_ioas *iommufd_ioas_alloc(struct iommufd_ctx *ictx) rc = iopt_init_table(&ioas->iopt); if (rc) goto out_abort; + + INIT_LIST_HEAD(&ioas->auto_domains); + mutex_init(&ioas->mutex); return ioas; out_abort: diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index d24c9dac5a82a9..c5c9650cc86818 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -96,6 +96,7 @@ static inline int iommufd_ucmd_respond(struct iommufd_ucmd *ucmd, enum iommufd_object_type { IOMMUFD_OBJ_NONE, IOMMUFD_OBJ_ANY = IOMMUFD_OBJ_NONE, + IOMMUFD_OBJ_HW_PAGETABLE, IOMMUFD_OBJ_IOAS, IOMMUFD_OBJ_MAX, }; @@ -153,10 +154,20 @@ struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, * io_pagetable object. It is a user controlled mapping of IOVA -> PFNs. The * mapping is copied into all of the associated domains and made available to * in-kernel users. + * + * Every iommu_domain that is created is wrapped in a iommufd_hw_pagetable + * object. When we go to attach a device to an IOAS we need to get an + * iommu_domain and wrapping iommufd_hw_pagetable for it. + * + * An iommu_domain & iommfd_hw_pagetable will be automatically selected + * for a device based on the auto_domains list. If no suitable iommu_domain + * is found a new iommu_domain will be created. */ struct iommufd_ioas { struct iommufd_object obj; struct io_pagetable iopt; + struct mutex mutex; + struct list_head auto_domains; }; static inline struct iommufd_ioas *iommufd_get_ioas(struct iommufd_ucmd *ucmd, @@ -174,4 +185,28 @@ int iommufd_ioas_iova_ranges(struct iommufd_ucmd *ucmd); int iommufd_ioas_map(struct iommufd_ucmd *ucmd); int iommufd_ioas_copy(struct iommufd_ucmd *ucmd); int iommufd_ioas_unmap(struct iommufd_ucmd *ucmd); + +/* + * A HW pagetable is called an iommu_domain inside the kernel. This user object + * allows directly creating and inspecting the domains. Domains that have kernel + * owned page tables will be associated with an iommufd_ioas that provides the + * IOVA to PFN map. + */ +struct iommufd_hw_pagetable { + struct iommufd_object obj; + struct iommufd_ioas *ioas; + struct iommu_domain *domain; + /* Head at iommufd_ioas::auto_domains */ + struct list_head auto_domains_item; + struct mutex devices_lock; + struct list_head devices; +}; + +struct iommufd_hw_pagetable * +iommufd_hw_pagetable_from_id(struct iommufd_ctx *ictx, u32 pt_id, + struct device *dev); +void iommufd_hw_pagetable_put(struct iommufd_ctx *ictx, + struct iommufd_hw_pagetable *hwpt); +void iommufd_hw_pagetable_destroy(struct iommufd_object *obj); + #endif diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index e506f493b54cfe..954cde173c86fc 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -287,6 +287,9 @@ static struct iommufd_object_ops iommufd_object_ops[] = { [IOMMUFD_OBJ_IOAS] = { .destroy = iommufd_ioas_destroy, }, + [IOMMUFD_OBJ_HW_PAGETABLE] = { + .destroy = iommufd_hw_pagetable_destroy, + }, }; static struct miscdevice iommu_misc_dev = { From patchwork Fri Mar 18 17:27:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74779C3525B for ; Fri, 18 Mar 2022 17:27:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239635AbiCRR3O (ORCPT ); Fri, 18 Mar 2022 13:29:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239639AbiCRR3M (ORCPT ); Fri, 18 Mar 2022 13:29:12 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2074.outbound.protection.outlook.com [40.107.93.74]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B912DED for ; Fri, 18 Mar 2022 10:27:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Nd5FzH9omBHcaR09YqXoh+hK9TCTBOqP7c6H0xOSUbFK+GhSixkQSHQ5qiHUyJ4WjwOITib8wiFRRMMP3xA/Yz+QSdXnDwQ3zgt8js87ruWfp/fDwQ/KfY6MuZFMhL93HQHprFCBnvObFsNi1DE9E55Y7i3BipzRuaZVgtZa0xkksAtffbsnnTvolmAXV/Ekzp+KVGJQtW3vFhvKxX8vTxH4P1hU4Y3qJO7vzk4GGS14tLEo6Qsu0AYtqwDP4saYZCrgHaTXOf2v5QUbeoRtduPLCnQt43AkouRsXnpxa6pDx7qwOM3uZl07jhatu4UK+v+azyTFKSjiKbcD8qhScA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tfJq4DR+Yo1ZHM8NIH4c/wojdHPsryGCdV3gE+Wmn5Q=; b=M5RPk4rQTszZmBahO1yKmwfUquokcGXf7T6vcsKTyW/SejzS5WsRoXshSJ1y2X1laBGG3RPTzL5OxEH8kL88Th9sgn8zByRqr8cWA6vMLttGDCCj6LtwDPZgcc88Eplo0rcnAeKmH1jifJpIOGIPnmaAPRQt2alLPhaEPGjM1O4Jut3Lu0CH8HiY4/1i8ZXCzsfgqYRbYRCerCaUo1zV/HJhGRBZ/k3MT7nwIBjjYmdwcU20TBfzTAiq1UtDFlT7Lj58mCNcJKHVDPUfQ0JOV+H16Vli4xYWGuPsMSoFFXHnuk+35uDK9WhNIYB+puxfmugRL9v7iphAqrrqrRQzwA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tfJq4DR+Yo1ZHM8NIH4c/wojdHPsryGCdV3gE+Wmn5Q=; b=YEHrGGsGbSvpcpulQ/m8j+WG8mZaS1KkfpYB/Eys9+hnEppzLaXanVcnp80qsyyGDK4ko17Xwj09EOkydFxdXPk8LNGkRE41ebWyJ+v4UQMreiZ63bHwxlwzQfPCXegssxBXZs4U9hrm8u/NfpiTFH7BYreT4VtTvX6E8IW/PNSxoDoLr2NKADAT5xs9Nru4a35a9MblSjzSibJRUglGTa5MAfjdTWJxp+JeyEZRy8nBsT6BJHbsTTmS0HFjxYhNbzDvtRSinBmwUO9T4sDaE/KpRuBJpZvUpSw44z1/4eY/cCWFDC0DyVcwM6eo/X4RRKQkfXcnz6vLeOserISU1A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by MN2PR12MB3951.namprd12.prod.outlook.com (2603:10b6:208:16b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.14; Fri, 18 Mar 2022 17:27:45 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c%5]) with mapi id 15.20.5081.018; Fri, 18 Mar 2022 17:27:45 +0000 From: Jason Gunthorpe Cc: Alex Williamson , Lu Baolu , Chaitanya Kulkarni , Cornelia Huck , Daniel Jordan , David Gibson , Eric Auger , iommu@lists.linux-foundation.org, Jason Wang , Jean-Philippe Brucker , Joao Martins , Kevin Tian , kvm@vger.kernel.org, Matthew Rosato , "Michael S. Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 10/12] iommufd: Add kAPI toward external drivers Date: Fri, 18 Mar 2022 14:27:35 -0300 Message-Id: <10-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR19CA0038.namprd19.prod.outlook.com (2603:10b6:208:19b::15) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7c2cb800-5e35-41d2-609e-08da09049a8d X-MS-TrafficTypeDiagnostic: MN2PR12MB3951:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DlB/U9aQAvU1HRHgvKzz0JLQkE+UXncJIFMws8Xyb7ktHIjXByJmDHWbFRhaIv/WoQbcZOzBLcC4oSeQkuhW/oMJsQbjBxdP2LqzGCfsgCmm/uFaM6zlLOIj1Hw7cJaDyKUbixsbtlMgdWSgshwLBq8Oh9UmHyrNuUV4tFQv7zxQzZ4hXhB9uVsHoSC+sVdXVuNYkjwyBGN3fvmcJZG1RZhkz9jZSAacTjB+osPEt+s1XGI+J/XTwVaYm5CBEIYamUiUtmS/tGsAf4PVvhY6LbleilBf9QrlGe35r/ayCeQw2PktYiwAeDX3jA7m7ASqS1X3tqUmtMzsgmxteux+hD7BeU1xyDi9GMUdCzPSngFFVE8wCZ57qigbBEE+4Js325KC+P/DPH251cTXR2kYKPP0bK32AmnBfDfeXmCZwQkenF/pIpeAQd+XTPR3zkCnPI6ztKTdqZAb9D3CRKc1KqrbgNo4rAhN69zkDxmz2VQ2zu2pgAYVbLXanrSEkrykecrLiNhfuZbfKGZ/x/hqe3X/fCy4vwHfdAM3PB7C8D9TnoYR+B6ldzyWSe/kG+SbAWDIHK4mFKyJb25CGojRhj2DeWM1wtUjt/j6hgmtyM33olc9dm25HYrxaAFCTWJ0bdVKrlKR8ru9+vg8s0o8OrN2dXB3M6Ll7EeYzGb+sANhcGQ+uUfTPAu9mIS60zZq X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(30864003)(83380400001)(7416002)(4326008)(2906002)(86362001)(508600001)(8676002)(6512007)(6506007)(6666004)(5660300002)(8936002)(109986005)(66946007)(26005)(66476007)(186003)(316002)(66556008)(2616005)(36756003)(38100700002)(6486002)(54906003)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vRkkSUAG/ax2WvTWGr84bcI1YRNQRQtuptMHEdpZUDFKIGnj80TmwavyiRdIeJTxAyF6Va6nrqca9BfPm+p6/OgF+e9i2bfm7pW5GM+c5SEcKAoseJQDdSo1MajeiBJSawB+MDUP2XFnnDYqnhZpyyILT77b+CctcZawt4TkNHcBem6oh4KOPPW+1q7oVnxiDiXcdXJodYT05KY10k2FhlT3N+x5i63dSlXWEODn10km03JIeJZZhUUdu5YGNEMJ8b+fHI/m3y84WDk99ecWzR3ftnsiovaPIlOfesvVXkCRGD9l0rpkw4+d0Ztg2AdqEtmqu575d+ZDUlkWMZ3y6owfwlLz2sa7kGLslHSafduWV/hsygbd2YfZCR2Rk0eaVoJCQBrPyF1Cz5+liZGhccREgJirocgPoQrOxHjXtrUNGwOVs4y7X8w7w29I/8qZKaJLb2i1jM3QGoNCqOBxKjLFF0+iO23VDyL8ejtYs9wjteNDXVdWU/ivxtxlJiVQGHF0yLm/2JAQZPCQV24ioN1cHYtg+K1z4OyfjlafNoRmIjUTAVxdQVQb7TTPkMwTSudPwXVA8wzmdba95m75fAMvH6jaEgfCgK4fufb+SVS1ZvPw9s/z6FFEsRbUHnAgjjp/TVrU70yqxW7aFfVYsobT8qFYX/Kw4uaqBbt7zTEzujNY8aqEHRyHoe1TGDcdsC/QDKj+9tuE2EZabemDu3YFyj6qPSAudEYxDFdUktf3shvb07bcn+xnj+mNLPK3AMW61jQ+MxhdfqbDDRI+86E6IYmbo8j5tOL3xhwmPqTRgGD+q5Sas4WgQdB9uPn1PYQ+CxNZ1n7Ko7IGX1UHk2gnxHt0M1qDHQ7kqWFCznLlMxvR2WGQJfGOP/fLe26FLa4zQ/v3H4/xW8cG0mcr5y0Jsb2MVuh7Y2h3CjDZxyonGK1fqKSerV6tPyaaxaoaz/3pnI7exx/uA20ueTegIxgDd1SgAYq9TPvCJjEaYGSdtQH6WFr+EMXvJGiV3Bs0b65+3eua6d/W31+hBCFEKBEubNWVtb1+PtcJ67btYIzF5WtAAU5EU61jbvjM3f5BMzudb78IEqziYaTxhGNgTSwjZUgf+8EHkWXnFqJIaRW6ZbJ5+j4zwaQmzahqn4QuVkutduFI9UrdcLHN3HoAGUq8TWM36S+lqOVmWEgt4zc6X9kQX9Jf80nkL0PpkJ8amZ9tQ4N1fQ8JEHC7uHshjknlDoEYf3qJt79nQBF28AJn1C50hnZkvDNgOSz6wjOv40c4MCgzK7R5bZVULydBNldLlQrscmoQvir2mWetbgBD4yPam1q5Ke1D8AwD66E7blubYCSRbAMV3wjwV3sWvs/Ub4UI/Ho+dW8Vs6mQjSBladsLglVnM+NOeHUoAnAewt6pSCJnSYp+szcANDbzFc62w/poG0R+efMrm4htZyotx/7QbWfze+s05TdCKIh8 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7c2cb800-5e35-41d2-609e-08da09049a8d X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:40.5696 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lAciH9CzOIoTKTj/jC2aG5SVLayhkYVfRryFZ1NITOJ5p/PEB6brygryWViVCyB9 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3951 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add the four functions external drivers need to connect physical DMA to the IOMMUFD: iommufd_bind_pci_device() / iommufd_unbind_device() Register the device with iommufd and establish security isolation. iommufd_device_attach() / iommufd_device_detach() Connect a bound device to a page table binding a device creates a device object ID in the uAPI, however the generic API provides no IOCTLs to manipulate them. An API to support the VFIO mdevs is a WIP at this point, but likely involves requesting a struct iommufd_device without providing any struct device, and then using the pin/unpin/rw operations on that iommufd_device. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommufd/Makefile | 1 + drivers/iommu/iommufd/device.c | 274 ++++++++++++++++++++++++ drivers/iommu/iommufd/iommufd_private.h | 4 + drivers/iommu/iommufd/main.c | 3 + include/linux/iommufd.h | 50 +++++ 5 files changed, 332 insertions(+) create mode 100644 drivers/iommu/iommufd/device.c create mode 100644 include/linux/iommufd.h diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index e13e971aa28c60..ca28a135b9675f 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only iommufd-y := \ + device.o \ hw_pagetable.o \ io_pagetable.o \ ioas.o \ diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c new file mode 100644 index 00000000000000..c20bc9eab07e13 --- /dev/null +++ b/drivers/iommu/iommufd/device.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES + */ +#include +#include +#include +#include +#include +#include +#include + +#include "iommufd_private.h" + +/* + * A iommufd_device object represents the binding relationship between a + * consuming driver and the iommufd. These objects are created/destroyed by + * external drivers, not by userspace. + */ +struct iommufd_device { + struct iommufd_object obj; + struct iommufd_ctx *ictx; + struct iommufd_hw_pagetable *hwpt; + /* Head at iommufd_hw_pagetable::devices */ + struct list_head devices_item; + /* always the physical device */ + struct device *dev; + struct iommu_group *group; +}; + +void iommufd_device_destroy(struct iommufd_object *obj) +{ + struct iommufd_device *idev = + container_of(obj, struct iommufd_device, obj); + + iommu_group_release_dma_owner(idev->group); + iommu_group_put(idev->group); + fput(idev->ictx->filp); +} + +/** + * iommufd_bind_pci_device - Bind a physical device to an iommu fd + * @fd: iommufd file descriptor. + * @pdev: Pointer to a physical PCI device struct + * @id: Output ID number to return to userspace for this device + * + * A successful bind establishes an ownership over the device and returns + * struct iommufd_device pointer, otherwise returns error pointer. + * + * A driver using this API must set driver_managed_dma and must not touch + * the device until this routine succeeds and establishes ownership. + * + * Binding a PCI device places the entire RID under iommufd control. + * + * The caller must undo this with iommufd_unbind_device() + */ +struct iommufd_device *iommufd_bind_pci_device(int fd, struct pci_dev *pdev, + u32 *id) +{ + struct iommufd_device *idev; + struct iommufd_ctx *ictx; + struct iommu_group *group; + int rc; + + ictx = iommufd_fget(fd); + if (!ictx) + return ERR_PTR(-EINVAL); + + group = iommu_group_get(&pdev->dev); + if (!group) { + rc = -ENODEV; + goto out_file_put; + } + + /* + * FIXME: Use a device-centric iommu api and this won't work with + * multi-device groups + */ + rc = iommu_group_claim_dma_owner(group, ictx->filp); + if (rc) + goto out_group_put; + + idev = iommufd_object_alloc(ictx, idev, IOMMUFD_OBJ_DEVICE); + if (IS_ERR(idev)) { + rc = PTR_ERR(idev); + goto out_release_owner; + } + idev->ictx = ictx; + idev->dev = &pdev->dev; + /* The calling driver is a user until iommufd_unbind_device() */ + refcount_inc(&idev->obj.users); + /* group refcount moves into iommufd_device */ + idev->group = group; + + /* + * If the caller fails after this success it must call + * iommufd_unbind_device() which is safe since we hold this refcount. + * This also means the device is a leaf in the graph and no other object + * can take a reference on it. + */ + iommufd_object_finalize(ictx, &idev->obj); + *id = idev->obj.id; + return idev; + +out_release_owner: + iommu_group_release_dma_owner(group); +out_group_put: + iommu_group_put(group); +out_file_put: + fput(ictx->filp); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_GPL(iommufd_bind_pci_device); + +void iommufd_unbind_device(struct iommufd_device *idev) +{ + bool was_destroyed; + + was_destroyed = iommufd_object_destroy_user(idev->ictx, &idev->obj); + WARN_ON(!was_destroyed); +} +EXPORT_SYMBOL_GPL(iommufd_unbind_device); + +static bool iommufd_hw_pagetable_has_group(struct iommufd_hw_pagetable *hwpt, + struct iommu_group *group) +{ + struct iommufd_device *cur_dev; + + list_for_each_entry (cur_dev, &hwpt->devices, devices_item) + if (cur_dev->group == group) + return true; + return false; +} + +static int iommufd_device_setup_msi(struct iommufd_device *idev, + struct iommufd_hw_pagetable *hwpt, + phys_addr_t sw_msi_start, + unsigned int flags) +{ + int rc; + + /* + * IOMMU_CAP_INTR_REMAP means that the platform is isolating MSI, + * nothing further to do. + */ + if (iommu_capable(idev->dev->bus, IOMMU_CAP_INTR_REMAP)) + return 0; + + /* + * On ARM systems that set the global IRQ_DOMAIN_FLAG_MSI_REMAP every + * allocated iommu_domain will block interrupts by default and this + * special flow is needed to turn them back on. + */ + if (irq_domain_check_msi_remap()) { + if (WARN_ON(!sw_msi_start)) + return -EPERM; + /* + * iommu_get_msi_cookie() can only be called once per domain, + * it returns -EBUSY on later calls. + */ + if (hwpt->msi_cookie) + return 0; + rc = iommu_get_msi_cookie(hwpt->domain, sw_msi_start); + if (rc && rc != -ENODEV) + return rc; + hwpt->msi_cookie = true; + return 0; + } + + /* + * Otherwise the platform has a MSI window that is not isolated. For + * historical compat with VFIO allow a module parameter to ignore the + * insecurity. + */ + if (!(flags & IOMMUFD_ATTACH_FLAGS_ALLOW_UNSAFE_INTERRUPT)) + return -EPERM; + return 0; +} + +/** + * iommufd_device_attach - Connect a device to an iommu_domain + * @idev: device to attach + * @pt_id: Input a IOMMUFD_OBJ_IOAS, or IOMMUFD_OBJ_HW_PAGETABLE + * Output the IOMMUFD_OBJ_HW_PAGETABLE ID + * @flags: Optional flags + * + * This connects the device to an iommu_domain, either automatically or manually + * selected. Once this completes the device could do DMA. + * + * The caller should return the resulting pt_id back to userspace. + * This function is undone by calling iommufd_device_detach(). + */ +int iommufd_device_attach(struct iommufd_device *idev, u32 *pt_id, + unsigned int flags) +{ + struct iommufd_hw_pagetable *hwpt; + int rc; + + refcount_inc(&idev->obj.users); + + hwpt = iommufd_hw_pagetable_from_id(idev->ictx, *pt_id, idev->dev); + if (IS_ERR(hwpt)) { + rc = PTR_ERR(hwpt); + goto out_users; + } + + mutex_lock(&hwpt->devices_lock); + /* FIXME: Use a device-centric iommu api. For now check if the + * hw_pagetable already has a device of the same group joined to tell if + * we are the first and need to attach the group. */ + if (!iommufd_hw_pagetable_has_group(hwpt, idev->group)) { + phys_addr_t sw_msi_start = 0; + + rc = iommu_attach_group(hwpt->domain, idev->group); + if (rc) + goto out_unlock; + + /* + * hwpt is now the exclusive owner of the group so this is the + * first time enforce is called for this group. + */ + rc = iopt_table_enforce_group_resv_regions( + &hwpt->ioas->iopt, idev->group, &sw_msi_start); + if (rc) + goto out_detach; + rc = iommufd_device_setup_msi(idev, hwpt, sw_msi_start, flags); + if (rc) + goto out_iova; + } + + idev->hwpt = hwpt; + if (list_empty(&hwpt->devices)) { + rc = iopt_table_add_domain(&hwpt->ioas->iopt, hwpt->domain); + if (rc) + goto out_iova; + } + list_add(&idev->devices_item, &hwpt->devices); + mutex_unlock(&hwpt->devices_lock); + + *pt_id = idev->hwpt->obj.id; + return 0; + +out_iova: + iopt_remove_reserved_iova(&hwpt->ioas->iopt, idev->group); +out_detach: + iommu_detach_group(hwpt->domain, idev->group); +out_unlock: + mutex_unlock(&hwpt->devices_lock); + iommufd_hw_pagetable_put(idev->ictx, hwpt); +out_users: + refcount_dec(&idev->obj.users); + return rc; +} +EXPORT_SYMBOL_GPL(iommufd_device_attach); + +void iommufd_device_detach(struct iommufd_device *idev) +{ + struct iommufd_hw_pagetable *hwpt = idev->hwpt; + + mutex_lock(&hwpt->devices_lock); + list_del(&idev->devices_item); + if (!iommufd_hw_pagetable_has_group(hwpt, idev->group)) { + iopt_remove_reserved_iova(&hwpt->ioas->iopt, idev->group); + iommu_detach_group(hwpt->domain, idev->group); + } + if (list_empty(&hwpt->devices)) + iopt_table_remove_domain(&hwpt->ioas->iopt, hwpt->domain); + mutex_unlock(&hwpt->devices_lock); + + iommufd_hw_pagetable_put(idev->ictx, hwpt); + idev->hwpt = NULL; + + refcount_dec(&idev->obj.users); +} +EXPORT_SYMBOL_GPL(iommufd_device_detach); diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index c5c9650cc86818..e5c717231f851e 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -96,6 +96,7 @@ static inline int iommufd_ucmd_respond(struct iommufd_ucmd *ucmd, enum iommufd_object_type { IOMMUFD_OBJ_NONE, IOMMUFD_OBJ_ANY = IOMMUFD_OBJ_NONE, + IOMMUFD_OBJ_DEVICE, IOMMUFD_OBJ_HW_PAGETABLE, IOMMUFD_OBJ_IOAS, IOMMUFD_OBJ_MAX, @@ -196,6 +197,7 @@ struct iommufd_hw_pagetable { struct iommufd_object obj; struct iommufd_ioas *ioas; struct iommu_domain *domain; + bool msi_cookie; /* Head at iommufd_ioas::auto_domains */ struct list_head auto_domains_item; struct mutex devices_lock; @@ -209,4 +211,6 @@ void iommufd_hw_pagetable_put(struct iommufd_ctx *ictx, struct iommufd_hw_pagetable *hwpt); void iommufd_hw_pagetable_destroy(struct iommufd_object *obj); +void iommufd_device_destroy(struct iommufd_object *obj); + #endif diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 954cde173c86fc..6a895489fb5b82 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -284,6 +284,9 @@ struct iommufd_ctx *iommufd_fget(int fd) } static struct iommufd_object_ops iommufd_object_ops[] = { + [IOMMUFD_OBJ_DEVICE] = { + .destroy = iommufd_device_destroy, + }, [IOMMUFD_OBJ_IOAS] = { .destroy = iommufd_ioas_destroy, }, diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h new file mode 100644 index 00000000000000..6caac05475e39f --- /dev/null +++ b/include/linux/iommufd.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Intel Corporation + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES + */ +#ifndef __LINUX_IOMMUFD_H +#define __LINUX_IOMMUFD_H + +#include +#include +#include +#include + +struct pci_dev; +struct iommufd_device; + +#if IS_ENABLED(CONFIG_IOMMUFD) +struct iommufd_device *iommufd_bind_pci_device(int fd, struct pci_dev *pdev, + u32 *id); +void iommufd_unbind_device(struct iommufd_device *idev); + +enum { + IOMMUFD_ATTACH_FLAGS_ALLOW_UNSAFE_INTERRUPT = 1 << 0, +}; +int iommufd_device_attach(struct iommufd_device *idev, u32 *pt_id, + unsigned int flags); +void iommufd_device_detach(struct iommufd_device *idev); + +#else /* !CONFIG_IOMMUFD */ +static inline struct iommufd_device * +iommufd_bind_pci_device(int fd, struct pci_dev *pdev, u32 *id) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void iommufd_unbind_device(struct iommufd_device *idev) +{ +} + +static inline int iommufd_device_attach(struct iommufd_device *idev, + u32 ioas_id) +{ + return -EOPNOTSUPP; +} + +static inline void iommufd_device_detach(struct iommufd_device *idev) +{ +} +#endif /* CONFIG_IOMMUFD */ +#endif From patchwork Fri Mar 18 17:27:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5DF8C433EF for ; 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Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH RFC 11/12] iommufd: vfio container FD ioctl compatibility Date: Fri, 18 Mar 2022 14:27:36 -0300 Message-Id: <11-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> In-Reply-To: <0-v1-e79cd8d168e8+6-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR19CA0062.namprd19.prod.outlook.com (2603:10b6:208:19b::39) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4056a38a-62a5-43e3-d3f4-08da090499f4 X-MS-TrafficTypeDiagnostic: MN2PR12MB3951:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NHZnOfm5z3E1+iNmlycTfm3tEutetq460oyTZrQ/GUxEUn1YXmewnkvjvGfNUm5O/s1HVMc+wxkzn/tUx055NSLBaY3h7aLBOI0yj2rXQxXUDN4BiN2pFe9+R17TH02RM+WWUzPZQSjUkcXo12yWC3MpZMg6lvM8gTLqDN8i5jcgc8EZS8DQDmULdSBHgWu4ZQhr35TFGBXFoUiFhqYg11ufVnRtt9VF6llOylMD/vPO2jJJ63uezTcGtNH/BH77RVrIzDt5pP6WcSni+4RpiHlbl5r98tVgOfMDgmpLpVvhGqmuKKgG1+arenbVNHyY48oulxKwvgsvsrA8bp90/X8vD1Ztha2MB9WPsx4w5cpyeEKSliW0L9Nl0YKHJdTi/WArbgblUNk0PkVXZwo5a8T2xO+8hQrgEVBjtBul7prqXya412biMJHYdrKNPYqVeesF5uZ3rwUYj4oqctjnEOxm1Xk6u7nzdhUspULSHPkMIRqLgTphkOzHg/yf+f4TxWeWuj0Uut7R0NST8TUF9GWKFxEyNX1NQRmL8kLtGtx9/Lo6uCTXlpsc50okoHrN6XHEykSGLRXE/8Maevm3XwDETRnpC1ThFtN2sfO6Y7qCXYGi1N7FWxDCsCK5s3g7sfrpNLhTZxUSGEYBWWjqsOwk6i3nVaQ/eiUxng59JFT2zUpi6no28N3y8/LgfvQL6GLwB5KcGTXrfBpVgukf773y18p09sfCStH3y2mjPjfLbswLa9RhMweZhUA+3KUv8IfvfXQlXY65mD1Y1ez17g== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB4192.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(30864003)(83380400001)(7416002)(4326008)(2906002)(86362001)(508600001)(8676002)(6512007)(6506007)(6666004)(5660300002)(8936002)(109986005)(66946007)(26005)(66476007)(186003)(316002)(66556008)(2616005)(36756003)(966005)(38100700002)(6486002)(54906003)(266003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sqqleW67+biqhGyfWs3J9OVW7yg0UgviYdj16vq9BZUqNSsjrwIZ9pSAndwPJ/cxkZJ4AS0GBifM9H5PZuy7RG3I0NSFtDC/RJ71dnumwQxR6V4+jz3OQiWMoaCayHPerJJwfPDoFscJ8poyx/Q9uv0aRy24KZFt9NJwshUbQcm7SXvV+zfURZfr4Vg0sSb3kbrAbaAQ1sOUy5r/VWxSB8DnJXB6z3pzq94CkR1MimSlGGyd7dZz/SnZ3OmsE/BbG2+YV/mG/CPpqWT9+8Rp1LE4zzy7h9X73sirMylaYwKn2V7K23EdvVD6P6A0Pndt58vkChU3D7QKeFbMrTF17nYzPEOav1TVxM2QdONJ3KiIo7ag3rVVPgwll73HXDLTR7+VYdF5SRusV7nkGyCnP+3khjyMceZcgS3SQ6LFdN7G7YLsurLubpqCT1Ul23+MiXYYzzIUvODdgkJsZ2m9d6qsqsgO/76M1V/TvvGTadjAg1M+Vkr1qFMmMHKSbSadNeYer53QjZ1yXZyOFJLSL2N2FmT/hv/BRWRp6wHOPiQRTEiz9b59SYTCKwvyzy04V95vJ8WNoR5SaAEqmpZZ00kHs1057shYaiEzlLuwVA5GXQsY1Ukc6lcF4hGpE8MshCY1F2QULUaoPKm9ccbuMDVwv/3JlEPo7WTAFp4C66CVtR6oZfOG21ibVg/0DdctdgMPP6jdJXzcUSZEmLkCNRmWIsOF45RfLPCH1VUreFJFnLUx8jAUwJbImmR1qps0Py0jYez+wRaHYQM0Fr/WRlt+QoMkkDaq4neBlCco0xsy35MkKA7teQfBPWXOSA5W6MSilZhHAyD+SymRtFTemqRf38aYl8xTTjjcMNWdDvaG9RKHvPEdUNLQ3nfBYTIIF5d3Y7pYgs+AezAVdiHeEbUpwnH09kmXosWgsWCRQ7Evss75MMyz++PORUPl5/0EJ0gou4ZwjSa/6PvkdNlHmfNldLdEDzxqoPUYbJgM0uxAgu9wcO1hGP6NEonJbAFgKS/MmhIYAsRNgLHD/aK8A8tMsgqMUIVdJTmpMoAp7pnyRQtxzJZPH1jUlLk4bxeiLkIG2EMLE1eP4xmqUFbS22+Zv6g7LRJPVo3BUZfRsg8Q5KFY4ldE6+wZuYyTU9JnLGaiWBpPGf/QrpaIpPz7WXH/yR80Be6aUc7Fa/isGQncpxSmLJaMVd3iz80chdMLdOoBg9Hi1x14S8xhXa+e+RtoKJ4GeM6/JlIwzMkjfS1hFK3ZHs0zCr4KDl9C/uDp6/3iEzBiwZQBfpjWTHdA8l7O+kgvov3hZCkJPYO+TBiUlrvPFciecA5bOxlWqFtSRKdR+c9LQFUICuYYEVIdoz1MXrezdQr/inFxm9jDs3XMX20C6xmmlXGMW4PWBUkmZfjf7F0YaSGp65CK1yBQDOtpxZgK8PeQc06AorukeUeznnJpQqJCymi6i///FCsL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4056a38a-62a5-43e3-d3f4-08da090499f4 X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2022 17:27:39.5698 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PEeh8rzGn9bHzYNjDL4quNrs9i81JSAJuxIPBV0lsXywqM/eWOIyOmQv3H7j/vWa X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3951 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org iommufd can directly implement the /dev/vfio/vfio container IOCTLs by mapping them into io_pagetable operations. Doing so allows the use of iommufd by symliking /dev/vfio/vfio to /dev/iommufd. Allowing VFIO to SET_CONTAINER using a iommufd instead of a container fd is a followup series. Internally the compatibility API uses a normal IOAS object that, like vfio, is automatically allocated when the first device is attached. Userspace can also query or set this IOAS object directly using the IOMMU_VFIO_IOAS ioctl. This allows mixing and matching new iommufd only features while still using the VFIO style map/unmap ioctls. While this is enough to operate qemu, it is still a bit of a WIP with a few gaps to be resolved: - Only the TYPE1v2 mode is supported where unmap cannot punch holes or split areas. The old mode can be implemented with a new operation to split an iopt_area into two without disturbing the iopt_pages or the domains, then unmapping a whole area as normal. - Resource limits rely on memory cgroups to bound what userspace can do instead of the module parameter dma_entry_limit. - VFIO P2P is not implemented. Avoiding the follow_pfn() mis-design will require some additional work to properly expose PFN lifecycle between VFIO and iommfd - Various components of the mdev API are not completed yet - Indefinite suspend of SW access (VFIO_DMA_MAP_FLAG_VADDR) is not implemented. - The 'dirty tracking' is not implemented - A full audit for pedantic compatibility details (eg errnos, etc) has not yet been done - powerpc SPAPR is left out, as it is not connected to the iommu_domain framework. My hope is that SPAPR will be moved into the iommu_domain framework as a special HW specific type and would expect power to support the generic interface through a normal iommu_domain. Signed-off-by: Nicolin Chen Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommufd/Makefile | 3 +- drivers/iommu/iommufd/iommufd_private.h | 6 + drivers/iommu/iommufd/main.c | 16 +- drivers/iommu/iommufd/vfio_compat.c | 401 ++++++++++++++++++++++++ include/uapi/linux/iommufd.h | 36 +++ 5 files changed, 456 insertions(+), 6 deletions(-) create mode 100644 drivers/iommu/iommufd/vfio_compat.c diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index ca28a135b9675f..2fdff04000b326 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -5,6 +5,7 @@ iommufd-y := \ io_pagetable.o \ ioas.o \ main.o \ - pages.o + pages.o \ + vfio_compat.o obj-$(CONFIG_IOMMUFD) += iommufd.o diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index e5c717231f851e..31628591591c17 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -67,6 +67,8 @@ void iopt_remove_reserved_iova(struct io_pagetable *iopt, void *owner); struct iommufd_ctx { struct file *filp; struct xarray objects; + + struct iommufd_ioas *vfio_ioas; }; struct iommufd_ctx *iommufd_fget(int fd); @@ -78,6 +80,9 @@ struct iommufd_ucmd { void *cmd; }; +int iommufd_vfio_ioctl(struct iommufd_ctx *ictx, unsigned int cmd, + unsigned long arg); + /* Copy the response in ucmd->cmd back to userspace. */ static inline int iommufd_ucmd_respond(struct iommufd_ucmd *ucmd, size_t cmd_len) @@ -186,6 +191,7 @@ int iommufd_ioas_iova_ranges(struct iommufd_ucmd *ucmd); int iommufd_ioas_map(struct iommufd_ucmd *ucmd); int iommufd_ioas_copy(struct iommufd_ucmd *ucmd); int iommufd_ioas_unmap(struct iommufd_ucmd *ucmd); +int iommufd_vfio_ioas(struct iommufd_ucmd *ucmd); /* * A HW pagetable is called an iommu_domain inside the kernel. This user object diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 6a895489fb5b82..f746fcff8145cb 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -122,6 +122,8 @@ bool iommufd_object_destroy_user(struct iommufd_ctx *ictx, return false; } __xa_erase(&ictx->objects, obj->id); + if (ictx->vfio_ioas && &ictx->vfio_ioas->obj == obj) + ictx->vfio_ioas = NULL; xa_unlock(&ictx->objects); iommufd_object_ops[obj->type].destroy(obj); @@ -219,27 +221,31 @@ static struct iommufd_ioctl_op iommufd_ioctl_ops[] = { __reserved), IOCTL_OP(IOMMU_IOAS_UNMAP, iommufd_ioas_unmap, struct iommu_ioas_unmap, length), + IOCTL_OP(IOMMU_VFIO_IOAS, iommufd_vfio_ioas, struct iommu_vfio_ioas, + __reserved), }; static long iommufd_fops_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { + struct iommufd_ctx *ictx = filp->private_data; struct iommufd_ucmd ucmd = {}; struct iommufd_ioctl_op *op; union ucmd_buffer buf; unsigned int nr; int ret; - ucmd.ictx = filp->private_data; + nr = _IOC_NR(cmd); + if (nr < IOMMUFD_CMD_BASE || + (nr - IOMMUFD_CMD_BASE) >= ARRAY_SIZE(iommufd_ioctl_ops)) + return iommufd_vfio_ioctl(ictx, cmd, arg); + + ucmd.ictx = ictx; ucmd.ubuffer = (void __user *)arg; ret = get_user(ucmd.user_size, (u32 __user *)ucmd.ubuffer); if (ret) return ret; - nr = _IOC_NR(cmd); - if (nr < IOMMUFD_CMD_BASE || - (nr - IOMMUFD_CMD_BASE) >= ARRAY_SIZE(iommufd_ioctl_ops)) - return -ENOIOCTLCMD; op = &iommufd_ioctl_ops[nr - IOMMUFD_CMD_BASE]; if (op->ioctl_num != cmd) return -ENOIOCTLCMD; diff --git a/drivers/iommu/iommufd/vfio_compat.c b/drivers/iommu/iommufd/vfio_compat.c new file mode 100644 index 00000000000000..5c996bc9b44d48 --- /dev/null +++ b/drivers/iommu/iommufd/vfio_compat.c @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "iommufd_private.h" + +static struct iommufd_ioas *get_compat_ioas(struct iommufd_ctx *ictx) +{ + struct iommufd_ioas *ioas = ERR_PTR(-ENODEV); + + xa_lock(&ictx->objects); + if (!ictx->vfio_ioas || !iommufd_lock_obj(&ictx->vfio_ioas->obj)) + goto out_unlock; + ioas = ictx->vfio_ioas; +out_unlock: + xa_unlock(&ictx->objects); + return ioas; +} + +/* + * Only attaching a group should cause a default creation of the internal ioas, + * this returns the existing ioas if it has already been assigned somehow + * FIXME: maybe_unused + */ +static __maybe_unused struct iommufd_ioas * +create_compat_ioas(struct iommufd_ctx *ictx) +{ + struct iommufd_ioas *ioas = NULL; + struct iommufd_ioas *out_ioas; + + ioas = iommufd_ioas_alloc(ictx); + if (IS_ERR(ioas)) + return ioas; + + xa_lock(&ictx->objects); + if (ictx->vfio_ioas && iommufd_lock_obj(&ictx->vfio_ioas->obj)) + out_ioas = ictx->vfio_ioas; + else + out_ioas = ioas; + xa_unlock(&ictx->objects); + + if (out_ioas != ioas) { + iommufd_object_abort(ictx, &ioas->obj); + return out_ioas; + } + if (!iommufd_lock_obj(&ioas->obj)) + WARN_ON(true); + iommufd_object_finalize(ictx, &ioas->obj); + return ioas; +} + +int iommufd_vfio_ioas(struct iommufd_ucmd *ucmd) +{ + struct iommu_vfio_ioas *cmd = ucmd->cmd; + struct iommufd_ioas *ioas; + + if (cmd->__reserved) + return -EOPNOTSUPP; + switch (cmd->op) { + case IOMMU_VFIO_IOAS_GET: + ioas = get_compat_ioas(ucmd->ictx); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + cmd->ioas_id = ioas->obj.id; + iommufd_put_object(&ioas->obj); + return iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + + case IOMMU_VFIO_IOAS_SET: + ioas = iommufd_get_ioas(ucmd, cmd->ioas_id); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + xa_lock(&ucmd->ictx->objects); + ucmd->ictx->vfio_ioas = ioas; + xa_unlock(&ucmd->ictx->objects); + iommufd_put_object(&ioas->obj); + return 0; + + case IOMMU_VFIO_IOAS_CLEAR: + xa_lock(&ucmd->ictx->objects); + ucmd->ictx->vfio_ioas = NULL; + xa_unlock(&ucmd->ictx->objects); + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int iommufd_vfio_map_dma(struct iommufd_ctx *ictx, unsigned int cmd, + void __user *arg) +{ + u32 supported_flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE; + size_t minsz = offsetofend(struct vfio_iommu_type1_dma_map, size); + struct vfio_iommu_type1_dma_map map; + int iommu_prot = IOMMU_CACHE; + struct iommufd_ioas *ioas; + unsigned long iova; + int rc; + + if (copy_from_user(&map, arg, minsz)) + return -EFAULT; + + if (map.argsz < minsz || map.flags & ~supported_flags) + return -EINVAL; + + if (map.flags & VFIO_DMA_MAP_FLAG_READ) + iommu_prot |= IOMMU_READ; + if (map.flags & VFIO_DMA_MAP_FLAG_WRITE) + iommu_prot |= IOMMU_WRITE; + + ioas = get_compat_ioas(ictx); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + + iova = map.iova; + rc = iopt_map_user_pages(&ioas->iopt, &iova, + u64_to_user_ptr(map.vaddr), map.size, + iommu_prot, 0); + iommufd_put_object(&ioas->obj); + return rc; +} + +static int iommufd_vfio_unmap_dma(struct iommufd_ctx *ictx, unsigned int cmd, + void __user *arg) +{ + size_t minsz = offsetofend(struct vfio_iommu_type1_dma_unmap, size); + u32 supported_flags = VFIO_DMA_UNMAP_FLAG_ALL; + struct vfio_iommu_type1_dma_unmap unmap; + struct iommufd_ioas *ioas; + int rc; + + if (copy_from_user(&unmap, arg, minsz)) + return -EFAULT; + + if (unmap.argsz < minsz || unmap.flags & ~supported_flags) + return -EINVAL; + + ioas = get_compat_ioas(ictx); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + + if (unmap.flags & VFIO_DMA_UNMAP_FLAG_ALL) + rc = iopt_unmap_all(&ioas->iopt); + else + rc = iopt_unmap_iova(&ioas->iopt, unmap.iova, unmap.size); + iommufd_put_object(&ioas->obj); + return rc; +} + +static int iommufd_vfio_check_extension(unsigned long type) +{ + switch (type) { + case VFIO_TYPE1v2_IOMMU: + case VFIO_UNMAP_ALL: + return 1; + /* + * FIXME: The type1 iommu allows splitting of maps, which can fail. This is doable but + * is a bunch of extra code that is only for supporting this case. + */ + case VFIO_TYPE1_IOMMU: + /* + * FIXME: No idea what VFIO_TYPE1_NESTING_IOMMU does as far as the uAPI + * is concerned. Seems like it was never completed, it only does + * something on ARM, but I can't figure out what or how to use it. Can't + * find any user implementation either. + */ + case VFIO_TYPE1_NESTING_IOMMU: + /* + * FIXME: Easy to support, but needs rework in the Intel iommu driver + * to expose the no snoop squashing to iommufd + */ + case VFIO_DMA_CC_IOMMU: + /* + * FIXME: VFIO_DMA_MAP_FLAG_VADDR + * https://lore.kernel.org/kvm/1611939252-7240-1-git-send-email-steven.sistare@oracle.com/ + * Wow, what a wild feature. This should have been implemented by + * allowing a iopt_pages to be associated with a memfd. It can then + * source mapping requests directly from a memfd without going through a + * mm_struct and thus doesn't care that the original qemu exec'd itself. + * The idea that userspace can flip a flag and cause kernel users to + * block indefinately is unacceptable. + * + * For VFIO compat we should implement this in a slightly different way, + * Creating a access_user that spans the whole area will immediately + * stop new faults as they will be handled from the xarray. We can then + * reparent the iopt_pages to the new mm_struct and undo the + * access_user. No blockage of kernel users required, does require + * filling the xarray with pages though. + */ + case VFIO_UPDATE_VADDR: + default: + return 0; + } + + /* FIXME: VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP I think everything with dirty + * tracking should be in its own ioctl, not muddled in unmap. If we want to + * atomically unmap and get the dirty bitmap it should be a flag in the dirty + * tracking ioctl, not here in unmap. Overall dirty tracking needs a careful + * review along side HW drivers implementing it. + */ +} + +static int iommufd_vfio_set_iommu(struct iommufd_ctx *ictx, unsigned long type) +{ + struct iommufd_ioas *ioas = NULL; + + if (type != VFIO_TYPE1v2_IOMMU) + return -EINVAL; + + /* VFIO fails the set_iommu if there is no group */ + ioas = get_compat_ioas(ictx); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + iommufd_put_object(&ioas->obj); + return 0; +} + +static u64 iommufd_get_pagesizes(struct iommufd_ioas *ioas) +{ + /* FIXME: See vfio_update_pgsize_bitmap(), for compat this should return + * the high bits too, and we need to decide if we should report that + * iommufd supports less than PAGE_SIZE alignment or stick to strict + * compatibility. qemu only cares about the first set bit. + */ + return ioas->iopt.iova_alignment; +} + +static int iommufd_fill_cap_iova(struct iommufd_ioas *ioas, + struct vfio_info_cap_header __user *cur, + size_t avail) +{ + struct vfio_iommu_type1_info_cap_iova_range __user *ucap_iovas = + container_of(cur, struct vfio_iommu_type1_info_cap_iova_range, + header); + struct vfio_iommu_type1_info_cap_iova_range cap_iovas = { + .header = { + .id = VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE, + .version = 1, + }, + }; + struct interval_tree_span_iter span; + + for (interval_tree_span_iter_first( + &span, &ioas->iopt.reserved_iova_itree, 0, ULONG_MAX); + !interval_tree_span_iter_done(&span); + interval_tree_span_iter_next(&span)) { + struct vfio_iova_range range; + + if (!span.is_hole) + continue; + range.start = span.start_hole; + range.end = span.last_hole; + if (avail >= struct_size(&cap_iovas, iova_ranges, + cap_iovas.nr_iovas + 1) && + copy_to_user(&ucap_iovas->iova_ranges[cap_iovas.nr_iovas], + &range, sizeof(range))) + return -EFAULT; + cap_iovas.nr_iovas++; + } + if (avail >= struct_size(&cap_iovas, iova_ranges, cap_iovas.nr_iovas) && + copy_to_user(ucap_iovas, &cap_iovas, sizeof(cap_iovas))) + return -EFAULT; + return struct_size(&cap_iovas, iova_ranges, cap_iovas.nr_iovas); +} + +static int iommufd_fill_cap_dma_avail(struct iommufd_ioas *ioas, + struct vfio_info_cap_header __user *cur, + size_t avail) +{ + struct vfio_iommu_type1_info_dma_avail cap_dma = { + .header = { + .id = VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL, + .version = 1, + }, + /* iommufd has no limit, return the same value as VFIO. */ + .avail = U16_MAX, + }; + + if (avail >= sizeof(cap_dma) && + copy_to_user(cur, &cap_dma, sizeof(cap_dma))) + return -EFAULT; + return sizeof(cap_dma); +} + +static int iommufd_vfio_iommu_get_info(struct iommufd_ctx *ictx, + void __user *arg) +{ + typedef int (*fill_cap_fn)(struct iommufd_ioas *ioas, + struct vfio_info_cap_header __user *cur, + size_t avail); + static const fill_cap_fn fill_fns[] = { + iommufd_fill_cap_iova, + iommufd_fill_cap_dma_avail, + }; + size_t minsz = offsetofend(struct vfio_iommu_type1_info, iova_pgsizes); + struct vfio_info_cap_header __user *last_cap = NULL; + struct vfio_iommu_type1_info info; + struct iommufd_ioas *ioas; + size_t total_cap_size; + int rc; + int i; + + if (copy_from_user(&info, arg, minsz)) + return -EFAULT; + + if (info.argsz < minsz) + return -EINVAL; + minsz = min_t(size_t, info.argsz, sizeof(info)); + + ioas = get_compat_ioas(ictx); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + + down_read(&ioas->iopt.iova_rwsem); + info.flags = VFIO_IOMMU_INFO_PGSIZES; + info.iova_pgsizes = iommufd_get_pagesizes(ioas); + info.cap_offset = 0; + + total_cap_size = sizeof(info); + for (i = 0; i != ARRAY_SIZE(fill_fns); i++) { + int cap_size; + + if (info.argsz > total_cap_size) + cap_size = fill_fns[i](ioas, arg + total_cap_size, + info.argsz - total_cap_size); + else + cap_size = fill_fns[i](ioas, NULL, 0); + if (cap_size < 0) { + rc = cap_size; + goto out_put; + } + if (last_cap && info.argsz >= total_cap_size && + put_user(total_cap_size, &last_cap->next)) { + rc = -EFAULT; + goto out_put; + } + last_cap = arg + total_cap_size; + total_cap_size += cap_size; + } + + /* + * If the user did not provide enough space then only some caps are + * returned and the argsz will be updated to the correct amount to get + * all caps. + */ + if (info.argsz >= total_cap_size) + info.cap_offset = sizeof(info); + info.argsz = total_cap_size; + info.flags |= VFIO_IOMMU_INFO_CAPS; + if (copy_to_user(arg, &info, minsz)) + rc = -EFAULT; + rc = 0; + +out_put: + up_read(&ioas->iopt.iova_rwsem); + iommufd_put_object(&ioas->obj); + return rc; +} + +/* FIXME TODO: +PowerPC SPAPR only: +#define VFIO_IOMMU_ENABLE _IO(VFIO_TYPE, VFIO_BASE + 15) +#define VFIO_IOMMU_DISABLE _IO(VFIO_TYPE, VFIO_BASE + 16) +#define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) +#define VFIO_IOMMU_SPAPR_REGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 17) +#define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18) +#define VFIO_IOMMU_SPAPR_TCE_CREATE _IO(VFIO_TYPE, VFIO_BASE + 19) +#define VFIO_IOMMU_SPAPR_TCE_REMOVE _IO(VFIO_TYPE, VFIO_BASE + 20) +*/ + +int iommufd_vfio_ioctl(struct iommufd_ctx *ictx, unsigned int cmd, + unsigned long arg) +{ + void __user *uarg = (void __user *)arg; + + switch (cmd) { + case VFIO_GET_API_VERSION: + return VFIO_API_VERSION; + case VFIO_SET_IOMMU: + return iommufd_vfio_set_iommu(ictx, arg); + case VFIO_CHECK_EXTENSION: + return iommufd_vfio_check_extension(arg); + case VFIO_IOMMU_GET_INFO: + return iommufd_vfio_iommu_get_info(ictx, uarg); + case VFIO_IOMMU_MAP_DMA: + return iommufd_vfio_map_dma(ictx, cmd, uarg); + case VFIO_IOMMU_UNMAP_DMA: + return iommufd_vfio_unmap_dma(ictx, cmd, uarg); + case VFIO_IOMMU_DIRTY_PAGES: + default: + return -ENOIOCTLCMD; + } + return -ENOIOCTLCMD; +} diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index ba7b17ec3002e3..2c0f5ced417335 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -42,6 +42,7 @@ enum { IOMMUFD_CMD_IOAS_MAP, IOMMUFD_CMD_IOAS_COPY, IOMMUFD_CMD_IOAS_UNMAP, + IOMMUFD_CMD_VFIO_IOAS, }; /** @@ -184,4 +185,39 @@ struct iommu_ioas_unmap { __aligned_u64 length; }; #define IOMMU_IOAS_UNMAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_UNMAP) + +/** + * enum iommufd_vfio_ioas_op + * @IOMMU_VFIO_IOAS_GET: Get the current compatibility IOAS + * @IOMMU_VFIO_IOAS_SET: Change the current compatibility IOAS + * @IOMMU_VFIO_IOAS_CLEAR: Disable VFIO compatibility + */ +enum iommufd_vfio_ioas_op { + IOMMU_VFIO_IOAS_GET = 0, + IOMMU_VFIO_IOAS_SET = 1, + IOMMU_VFIO_IOAS_CLEAR = 2, +}; + +/** + * struct iommu_vfio_ioas - ioctl(IOMMU_VFIO_IOAS) + * @size: sizeof(struct iommu_ioas_copy) + * @ioas_id: For IOMMU_VFIO_IOAS_SET the input IOAS ID to set + * For IOMMU_VFIO_IOAS_GET will output the IOAS ID + * @op: One of enum iommufd_vfio_ioas_op + * @__reserved: Must be 0 + * + * The VFIO compatibility support uses a single ioas because VFIO APIs do not + * support the ID field. Set or Get the IOAS that VFIO compatibility will use. + * When VFIO_GROUP_SET_CONTAINER is used on an iommufd it will get the + * compatibility ioas, either by taking what is already set, or auto creating + * one. From then on VFIO will continue to use that ioas and is not effected by + * this ioctl. SET or CLEAR does not destroy any auto-created IOAS. + */ +struct iommu_vfio_ioas { + __u32 size; + __u32 ioas_id; + __u16 op; + __u16 __reserved; +}; +#define IOMMU_VFIO_IOAS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VFIO_IOAS) #endif From patchwork Fri Mar 18 17:27:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 12785707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00A6DC43217 for ; Fri, 18 Mar 2022 17:27:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239642AbiCRR3N (ORCPT ); Fri, 18 Mar 2022 13:29:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239635AbiCRR3L (ORCPT ); Fri, 18 Mar 2022 13:29:11 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 290F72A4F90 for ; Fri, 18 Mar 2022 10:27:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jo925Xbhhk6UeMNyw+XxsdZq+KTp8PwtxCzyZ+T5yqHbg1dJfp62+A9vb3fGUAQqiYjOfp6FYVEMCHQS2zK5jNybA+cx2cEwLIp1Z4SqvuM0xVlRVJIx06Ux5LsRnxMNoB590yN2s5qD0NBr34XParWv1aJd7F8ZSqnPcuaDfl3c3cBxjaF5JNqujWV3dRlj4nC2/R3IL0Tt3hDKzsaAMiOHoZvU1EHMX6IWpj0EetWychvStdyUaP2mmtZGefexRjQezgMiUGfAQTHAQas7oag+32p3wD227J18+zKRummlshvu36CmCi7NzIKGMNN92QA6i7JH+0X5QGEPL63Pig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tHJpxBxS1tDt2/b4xwa2I38aOIUUrnxck433Ya4GsB8=; b=VtbeSVrAtZVkS+2cJXuDs8I8SmdYVDnNXtMzFfK66HniyHY6UywLxaNhpZ5DgBrEqgHWon0zK8NG7/UcIcejEC1W0KPh5dBKK32PxVwOI7qalYO4scsjoVMGEUql8MwUhv2EmCu7lVtcsd/wZcN1E31kXrcqQv1UIztP4DtzM4X2fAZT+XHApGbQLf5VD0Tx8+eeft5E5GM0mnOAxARGbeHQ2UX/7cmQGnjJ95MysUNJSH6QnMhGXETk9vpa5z1w9KLryFcgfW/91mPILJRMkgU4UrMXrcEfq8BkkOEln+6rNpyDbqetlugjZJyGy1rQFClFe7x3y6HGicPPYA0/Eg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tHJpxBxS1tDt2/b4xwa2I38aOIUUrnxck433Ya4GsB8=; b=sqh24Ata/qjWpp4JS0evYhVgLG+YQwmBQmSX0fIubHzvU4o6U1U3F7VzCX+V6JbAhHa24BUIhU9VpSqHpNopiwyo3p0XnVhy8rL8ekyJRiAOgZLWos9hE8BLhqmkhf3BCiGZc00nYvNJJyNj+3m31ACT4161B96ze08mbuHrINRPVZ4MCuXidoEQGenqXuX6g96uv0cyh9BDJIQ3Cs+sJpZjiThG6bHANjvLK8evM/RbEa0YMzaZ9thbCLQJc3D/0bnVhd1wF4lEmWvxFiqRmf0rX+M8Rmei5+ivz4Mcm5mhQ4tfP2WKKQCTZ2Bu4XwFIW7ecBi0vWKXuj6bg6i4Mw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by MN2PR12MB3951.namprd12.prod.outlook.com (2603:10b6:208:16b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5081.14; Fri, 18 Mar 2022 17:27:42 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::11a0:970a:4c24:c70c%5]) with mapi id 15.20.5081.018; Fri, 18 Mar 2022 17:27:42 +0000 From: Jason Gunthorpe Cc: Alex Williamson , Lu Baolu , Chaitanya Kulkarni , Cornelia Huck , Daniel Jordan , David Gibson , Eric Auger , iommu@lists.linux-foundation.org, Jason Wang , Jean-Philippe Brucker , Joao Martins , Kevin Tian , kvm@vger.kernel.org, Matthew Rosato , "Michael S. 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This aims to achieve reasonable functional coverage using the in-kernel self test framework. It provides a mock for the iommu_domain that allows it to run without any HW and the mocking provides a way to directly validate that the PFNs loaded into the iommu_domain are correct. The mock also simulates the rare case of PAGE_SIZE > iommu page size as the mock will typically operate at a 2K iommu page size. This allows exercising all of the calculations to support this mismatch. This allows achieving high coverage of the corner cases in the iopt_pages. However, it is an unusually invasive config option to enable all of this. The config option should never be enabled in a production kernel. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/Kconfig | 9 + drivers/iommu/iommufd/Makefile | 2 + drivers/iommu/iommufd/iommufd_private.h | 9 + drivers/iommu/iommufd/iommufd_test.h | 65 ++ drivers/iommu/iommufd/main.c | 12 + drivers/iommu/iommufd/pages.c | 4 + drivers/iommu/iommufd/selftest.c | 495 +++++++++ tools/testing/selftests/Makefile | 1 + tools/testing/selftests/iommu/.gitignore | 2 + tools/testing/selftests/iommu/Makefile | 11 + tools/testing/selftests/iommu/config | 2 + tools/testing/selftests/iommu/iommufd.c | 1225 ++++++++++++++++++++++ 12 files changed, 1837 insertions(+) create mode 100644 drivers/iommu/iommufd/iommufd_test.h create mode 100644 drivers/iommu/iommufd/selftest.c create mode 100644 tools/testing/selftests/iommu/.gitignore create mode 100644 tools/testing/selftests/iommu/Makefile create mode 100644 tools/testing/selftests/iommu/config create mode 100644 tools/testing/selftests/iommu/iommufd.c diff --git a/drivers/iommu/iommufd/Kconfig b/drivers/iommu/iommufd/Kconfig index fddd453bb0e764..9b41fde7c839c5 100644 --- a/drivers/iommu/iommufd/Kconfig +++ b/drivers/iommu/iommufd/Kconfig @@ -11,3 +11,12 @@ config IOMMUFD This would commonly be used in combination with VFIO. If you don't know what to do here, say N. + +config IOMMUFD_TEST + bool "IOMMU Userspace API Test support" + depends on IOMMUFD + depends on RUNTIME_TESTING_MENU + default n + help + This is dangerous, do not enable unless running + tools/testing/selftests/iommu diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index 2fdff04000b326..8aeba81800c512 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -8,4 +8,6 @@ iommufd-y := \ pages.o \ vfio_compat.o +iommufd-$(CONFIG_IOMMUFD_TEST) += selftest.o + obj-$(CONFIG_IOMMUFD) += iommufd.o diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 31628591591c17..6f11470c8ea677 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -102,6 +102,9 @@ enum iommufd_object_type { IOMMUFD_OBJ_NONE, IOMMUFD_OBJ_ANY = IOMMUFD_OBJ_NONE, IOMMUFD_OBJ_DEVICE, +#ifdef CONFIG_IOMMUFD_TEST + IOMMUFD_OBJ_SELFTEST, +#endif IOMMUFD_OBJ_HW_PAGETABLE, IOMMUFD_OBJ_IOAS, IOMMUFD_OBJ_MAX, @@ -219,4 +222,10 @@ void iommufd_hw_pagetable_destroy(struct iommufd_object *obj); void iommufd_device_destroy(struct iommufd_object *obj); +#ifdef CONFIG_IOMMUFD_TEST +int iommufd_test(struct iommufd_ucmd *ucmd); +void iommufd_selftest_destroy(struct iommufd_object *obj); +extern size_t iommufd_test_memory_limit; +#endif + #endif diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/iommufd_test.h new file mode 100644 index 00000000000000..d22ef484af1a90 --- /dev/null +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. + */ +#ifndef _UAPI_IOMMUFD_TEST_H +#define _UAPI_IOMMUFD_TEST_H + +#include +#include + +enum { + IOMMU_TEST_OP_ADD_RESERVED, + IOMMU_TEST_OP_MOCK_DOMAIN, + IOMMU_TEST_OP_MD_CHECK_MAP, + IOMMU_TEST_OP_MD_CHECK_REFS, + IOMMU_TEST_OP_ACCESS_PAGES, + IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT, +}; + +enum { + MOCK_APERTURE_START = 1UL << 24, + MOCK_APERTURE_LAST = (1UL << 31) - 1, +}; + +enum { + MOCK_FLAGS_ACCESS_WRITE = 1 << 0, +}; + +struct iommu_test_cmd { + __u32 size; + __u32 op; + __u32 id; + union { + struct { + __u32 device_id; + } mock_domain; + struct { + __aligned_u64 start; + __aligned_u64 length; + } add_reserved; + struct { + __aligned_u64 iova; + __aligned_u64 length; + __aligned_u64 uptr; + } check_map; + struct { + __aligned_u64 length; + __aligned_u64 uptr; + __u32 refs; + } check_refs; + struct { + __u32 flags; + __u32 out_access_id; + __aligned_u64 iova; + __aligned_u64 length; + __aligned_u64 uptr; + } access_pages; + struct { + __u32 limit; + } memory_limit; + }; + __u32 last; +}; +#define IOMMU_TEST_CMD _IO(IOMMUFD_TYPE, IOMMUFD_CMD_BASE + 32) + +#endif diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index f746fcff8145cb..8c820bb90caa72 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -24,6 +24,7 @@ #include #include "iommufd_private.h" +#include "iommufd_test.h" struct iommufd_object_ops { void (*destroy)(struct iommufd_object *obj); @@ -191,6 +192,9 @@ union ucmd_buffer { struct iommu_ioas_map map; struct iommu_ioas_unmap unmap; struct iommu_destroy destroy; +#ifdef CONFIG_IOMMUFD_TEST + struct iommu_test_cmd test; +#endif }; struct iommufd_ioctl_op { @@ -223,6 +227,9 @@ static struct iommufd_ioctl_op iommufd_ioctl_ops[] = { length), IOCTL_OP(IOMMU_VFIO_IOAS, iommufd_vfio_ioas, struct iommu_vfio_ioas, __reserved), +#ifdef CONFIG_IOMMUFD_TEST + IOCTL_OP(IOMMU_TEST_CMD, iommufd_test, struct iommu_test_cmd, last), +#endif }; static long iommufd_fops_ioctl(struct file *filp, unsigned int cmd, @@ -299,6 +306,11 @@ static struct iommufd_object_ops iommufd_object_ops[] = { [IOMMUFD_OBJ_HW_PAGETABLE] = { .destroy = iommufd_hw_pagetable_destroy, }, +#ifdef CONFIG_IOMMUFD_TEST + [IOMMUFD_OBJ_SELFTEST] = { + .destroy = iommufd_selftest_destroy, + }, +#endif }; static struct miscdevice iommu_misc_dev = { diff --git a/drivers/iommu/iommufd/pages.c b/drivers/iommu/iommufd/pages.c index 8e6a8cc8b20ad1..3fd39e0201f542 100644 --- a/drivers/iommu/iommufd/pages.c +++ b/drivers/iommu/iommufd/pages.c @@ -48,7 +48,11 @@ #include "io_pagetable.h" +#ifndef CONFIG_IOMMUFD_TEST #define TEMP_MEMORY_LIMIT 65536 +#else +#define TEMP_MEMORY_LIMIT iommufd_test_memory_limit +#endif #define BATCH_BACKUP_SIZE 32 /* diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c new file mode 100644 index 00000000000000..a665719b493ec5 --- /dev/null +++ b/drivers/iommu/iommufd/selftest.c @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. + * + * Kernel side components to support tools/testing/selftests/iommu + */ +#include +#include +#include + +#include "iommufd_private.h" +#include "iommufd_test.h" + +size_t iommufd_test_memory_limit = 65536; + +enum { + MOCK_IO_PAGE_SIZE = PAGE_SIZE / 2, + + /* + * Like a real page table alignment requires the low bits of the address + * to be zero. xarray also requires the high bit to be zero, so we store + * the pfns shifted. The upper bits are used for metadata. + */ + MOCK_PFN_MASK = ULONG_MAX / MOCK_IO_PAGE_SIZE, + + _MOCK_PFN_START = MOCK_PFN_MASK + 1, + MOCK_PFN_START_IOVA = _MOCK_PFN_START, + MOCK_PFN_LAST_IOVA = _MOCK_PFN_START, +}; + +struct mock_iommu_domain { + struct iommu_domain domain; + struct xarray pfns; +}; + +enum selftest_obj_type { + TYPE_ACCESS, + TYPE_IDEV, +}; + +struct selftest_obj { + struct iommufd_object obj; + enum selftest_obj_type type; + + union { + struct { + struct iommufd_ioas *ioas; + unsigned long iova; + size_t length; + } access; + struct { + struct iommufd_hw_pagetable *hwpt; + struct iommufd_ctx *ictx; + } idev; + }; +}; + +static struct iommu_domain *mock_domain_alloc(unsigned int iommu_domain_type) +{ + struct mock_iommu_domain *mock; + + if (WARN_ON(iommu_domain_type != IOMMU_DOMAIN_UNMANAGED)) + return NULL; + + mock = kzalloc(sizeof(*mock), GFP_KERNEL); + if (!mock) + return NULL; + mock->domain.geometry.aperture_start = MOCK_APERTURE_START; + mock->domain.geometry.aperture_end = MOCK_APERTURE_LAST; + mock->domain.pgsize_bitmap = MOCK_IO_PAGE_SIZE; + xa_init(&mock->pfns); + return &mock->domain; +} + +static void mock_domain_free(struct iommu_domain *domain) +{ + struct mock_iommu_domain *mock = + container_of(domain, struct mock_iommu_domain, domain); + + WARN_ON(!xa_empty(&mock->pfns)); + kfree(mock); +} + +static int mock_domain_map_pages(struct iommu_domain *domain, + unsigned long iova, phys_addr_t paddr, + size_t pgsize, size_t pgcount, int prot, + gfp_t gfp, size_t *mapped) +{ + struct mock_iommu_domain *mock = + container_of(domain, struct mock_iommu_domain, domain); + unsigned long flags = MOCK_PFN_START_IOVA; + + WARN_ON(iova % MOCK_IO_PAGE_SIZE); + WARN_ON(pgsize % MOCK_IO_PAGE_SIZE); + for (; pgcount; pgcount--) { + size_t cur; + + for (cur = 0; cur != pgsize; cur += MOCK_IO_PAGE_SIZE) { + void *old; + + if (pgcount == 1 && cur + MOCK_IO_PAGE_SIZE == pgsize) + flags = MOCK_PFN_LAST_IOVA; + old = xa_store(&mock->pfns, iova / MOCK_IO_PAGE_SIZE, + xa_mk_value((paddr / MOCK_IO_PAGE_SIZE) | flags), + GFP_KERNEL); + if (xa_is_err(old)) + return xa_err(old); + WARN_ON(old); + iova += MOCK_IO_PAGE_SIZE; + paddr += MOCK_IO_PAGE_SIZE; + *mapped += MOCK_IO_PAGE_SIZE; + flags = 0; + } + } + return 0; +} + +static size_t mock_domain_unmap_pages(struct iommu_domain *domain, + unsigned long iova, size_t pgsize, + size_t pgcount, + struct iommu_iotlb_gather *iotlb_gather) +{ + struct mock_iommu_domain *mock = + container_of(domain, struct mock_iommu_domain, domain); + bool first = true; + size_t ret = 0; + void *ent; + + WARN_ON(iova % MOCK_IO_PAGE_SIZE); + WARN_ON(pgsize % MOCK_IO_PAGE_SIZE); + + for (; pgcount; pgcount--) { + size_t cur; + + for (cur = 0; cur != pgsize; cur += MOCK_IO_PAGE_SIZE) { + ent = xa_erase(&mock->pfns, iova / MOCK_IO_PAGE_SIZE); + WARN_ON(!ent); + /* + * iommufd generates unmaps that must be a strict + * superset of the map's performend So every starting + * IOVA should have been an iova passed to map, and the + * + * First IOVA must be present and have been a first IOVA + * passed to map_pages + */ + if (first) { + WARN_ON(!(xa_to_value(ent) & + MOCK_PFN_START_IOVA)); + first = false; + } + if (pgcount == 1 && cur + MOCK_IO_PAGE_SIZE == pgsize) + WARN_ON(!(xa_to_value(ent) & + MOCK_PFN_LAST_IOVA)); + + iova += MOCK_IO_PAGE_SIZE; + ret += MOCK_IO_PAGE_SIZE; + } + } + return ret; +} + +static phys_addr_t mock_domain_iova_to_phys(struct iommu_domain *domain, + dma_addr_t iova) +{ + struct mock_iommu_domain *mock = + container_of(domain, struct mock_iommu_domain, domain); + void *ent; + + WARN_ON(iova % MOCK_IO_PAGE_SIZE); + ent = xa_load(&mock->pfns, iova / MOCK_IO_PAGE_SIZE); + WARN_ON(!ent); + return (xa_to_value(ent) & MOCK_PFN_MASK) * MOCK_IO_PAGE_SIZE; +} + +static const struct iommu_ops mock_ops = { + .owner = THIS_MODULE, + .pgsize_bitmap = MOCK_IO_PAGE_SIZE, + .domain_alloc = mock_domain_alloc, + .default_domain_ops = + &(struct iommu_domain_ops){ + .free = mock_domain_free, + .map_pages = mock_domain_map_pages, + .unmap_pages = mock_domain_unmap_pages, + .iova_to_phys = mock_domain_iova_to_phys, + }, +}; + +static inline struct iommufd_hw_pagetable * +get_md_pagetable(struct iommufd_ucmd *ucmd, u32 mockpt_id, + struct mock_iommu_domain **mock) +{ + struct iommufd_hw_pagetable *hwpt; + struct iommufd_object *obj; + + obj = iommufd_get_object(ucmd->ictx, mockpt_id, + IOMMUFD_OBJ_HW_PAGETABLE); + if (IS_ERR(obj)) + return ERR_CAST(obj); + hwpt = container_of(obj, struct iommufd_hw_pagetable, obj); + if (hwpt->domain->ops != mock_ops.default_domain_ops) { + return ERR_PTR(-EINVAL); + iommufd_put_object(&hwpt->obj); + } + *mock = container_of(hwpt->domain, struct mock_iommu_domain, domain); + return hwpt; +} + +/* Create an hw_pagetable with the mock domain so we can test the domain ops */ +static int iommufd_test_mock_domain(struct iommufd_ucmd *ucmd, + struct iommu_test_cmd *cmd) +{ + struct bus_type mock_bus = { .iommu_ops = &mock_ops }; + struct device mock_dev = { .bus = &mock_bus }; + struct iommufd_hw_pagetable *hwpt; + struct selftest_obj *sobj; + int rc; + + sobj = iommufd_object_alloc(ucmd->ictx, sobj, IOMMUFD_OBJ_SELFTEST); + if (IS_ERR(sobj)) + return PTR_ERR(sobj); + sobj->idev.ictx = ucmd->ictx; + sobj->type = TYPE_IDEV; + + hwpt = iommufd_hw_pagetable_from_id(ucmd->ictx, cmd->id, &mock_dev); + if (IS_ERR(hwpt)) { + rc = PTR_ERR(hwpt); + goto out_sobj; + } + if (WARN_ON(refcount_read(&hwpt->obj.users) != 2)) { + rc = -EINVAL; + goto out_hwpt; + } + sobj->idev.hwpt = hwpt; + + /* Creating a real iommufd_device is too hard, fake one */ + rc = iopt_table_add_domain(&hwpt->ioas->iopt, hwpt->domain); + if (rc) + goto out_hwpt; + + /* Convert auto domain to user created */ + list_del_init(&hwpt->auto_domains_item); + cmd->id = hwpt->obj.id; + cmd->mock_domain.device_id = sobj->obj.id; + iommufd_object_finalize(ucmd->ictx, &sobj->obj); + return iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + +out_hwpt: + iommufd_hw_pagetable_put(ucmd->ictx, hwpt); +out_sobj: + iommufd_object_abort(ucmd->ictx, &sobj->obj); + return rc; +} + +/* Add an additional reserved IOVA to the IOAS */ +static int iommufd_test_add_reserved(struct iommufd_ucmd *ucmd, + unsigned int mockpt_id, + unsigned long start, size_t length) +{ + struct iommufd_ioas *ioas; + int rc; + + ioas = iommufd_get_ioas(ucmd, mockpt_id); + if (IS_ERR(ioas)) + return PTR_ERR(ioas); + down_write(&ioas->iopt.iova_rwsem); + rc = iopt_reserve_iova(&ioas->iopt, start, start + length - 1, NULL); + up_write(&ioas->iopt.iova_rwsem); + iommufd_put_object(&ioas->obj); + return rc; +} + +/* Check that every pfn under each iova matches the pfn under a user VA */ +static int iommufd_test_md_check_pa(struct iommufd_ucmd *ucmd, + unsigned int mockpt_id, unsigned long iova, + size_t length, void __user *uptr) +{ + struct iommufd_hw_pagetable *hwpt; + struct mock_iommu_domain *mock; + int rc; + + if (iova % MOCK_IO_PAGE_SIZE || length % MOCK_IO_PAGE_SIZE || + (uintptr_t)uptr % MOCK_IO_PAGE_SIZE) + return -EINVAL; + + hwpt = get_md_pagetable(ucmd, mockpt_id, &mock); + if (IS_ERR(hwpt)) + return PTR_ERR(hwpt); + + for (; length; length -= MOCK_IO_PAGE_SIZE) { + struct page *pages[1]; + unsigned long pfn; + long npages; + void *ent; + + npages = get_user_pages_fast((uintptr_t)uptr & PAGE_MASK, 1, 0, + pages); + if (npages < 0) { + rc = npages; + goto out_put; + } + if (WARN_ON(npages != 1)) { + rc = -EFAULT; + goto out_put; + } + pfn = page_to_pfn(pages[0]); + put_page(pages[0]); + + ent = xa_load(&mock->pfns, iova / MOCK_IO_PAGE_SIZE); + if (!ent || + (xa_to_value(ent) & MOCK_PFN_MASK) * MOCK_IO_PAGE_SIZE != + pfn * PAGE_SIZE + ((uintptr_t)uptr % PAGE_SIZE)) { + rc = -EINVAL; + goto out_put; + } + iova += MOCK_IO_PAGE_SIZE; + uptr += MOCK_IO_PAGE_SIZE; + } + rc = 0; + +out_put: + iommufd_put_object(&hwpt->obj); + return rc; +} + +/* Check that the page ref count matches, to look for missing pin/unpins */ +static int iommufd_test_md_check_refs(struct iommufd_ucmd *ucmd, + void __user *uptr, size_t length, + unsigned int refs) +{ + if (length % PAGE_SIZE || (uintptr_t)uptr % PAGE_SIZE) + return -EINVAL; + + for (; length; length -= PAGE_SIZE) { + struct page *pages[1]; + long npages; + + npages = get_user_pages_fast((uintptr_t)uptr, 1, 0, pages); + if (npages < 0) + return npages; + if (WARN_ON(npages != 1)) + return -EFAULT; + if (!PageCompound(pages[0])) { + unsigned int count; + + count = page_ref_count(pages[0]); + if (count / GUP_PIN_COUNTING_BIAS != refs) { + put_page(pages[0]); + return -EIO; + } + } + put_page(pages[0]); + uptr += PAGE_SIZE; + } + return 0; +} + +/* Check that the pages in a page array match the pages in the user VA */ +static int iommufd_test_check_pages(void __user *uptr, struct page **pages, + size_t npages) +{ + for (; npages; npages--) { + struct page *tmp_pages[1]; + long rc; + + rc = get_user_pages_fast((uintptr_t)uptr, 1, 0, tmp_pages); + if (rc < 0) + return rc; + if (WARN_ON(rc != 1)) + return -EFAULT; + put_page(tmp_pages[0]); + if (tmp_pages[0] != *pages) + return -EBADE; + pages++; + uptr += PAGE_SIZE; + } + return 0; +} + +/* Test iopt_access_pages() by checking it returns the correct pages */ +static int iommufd_test_access_pages(struct iommufd_ucmd *ucmd, + unsigned int ioas_id, unsigned long iova, + size_t length, void __user *uptr, + u32 flags) +{ + struct iommu_test_cmd *cmd = ucmd->cmd; + struct selftest_obj *sobj; + struct page **pages; + size_t npages; + int rc; + + if (flags & ~MOCK_FLAGS_ACCESS_WRITE) + return -EOPNOTSUPP; + + sobj = iommufd_object_alloc(ucmd->ictx, sobj, IOMMUFD_OBJ_SELFTEST); + if (IS_ERR(sobj)) + return PTR_ERR(sobj); + sobj->type = TYPE_ACCESS; + + npages = (ALIGN(iova + length, PAGE_SIZE) - + ALIGN_DOWN(iova, PAGE_SIZE)) / + PAGE_SIZE; + pages = kvcalloc(npages, sizeof(*pages), GFP_KERNEL); + if (!pages) { + rc = -ENOMEM; + goto out_abort; + } + + sobj->access.ioas = iommufd_get_ioas(ucmd, ioas_id); + if (IS_ERR(sobj->access.ioas)) { + rc = PTR_ERR(sobj->access.ioas); + goto out_free; + } + + sobj->access.iova = iova; + sobj->access.length = length; + rc = iopt_access_pages(&sobj->access.ioas->iopt, iova, length, pages, + flags & MOCK_FLAGS_ACCESS_WRITE); + if (rc) + goto out_put; + + rc = iommufd_test_check_pages( + uptr - (iova - ALIGN_DOWN(iova, PAGE_SIZE)), pages, npages); + if (rc) + goto out_unaccess; + + cmd->access_pages.out_access_id = sobj->obj.id; + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + if (rc) + goto out_unaccess; + + iommufd_object_finalize(ucmd->ictx, &sobj->obj); + iommufd_put_object_keep_user(&sobj->access.ioas->obj); + kvfree(pages); + return 0; +out_unaccess: + iopt_unaccess_pages(&sobj->access.ioas->iopt, iova, length); +out_put: + iommufd_put_object(&sobj->access.ioas->obj); +out_free: + kvfree(pages); +out_abort: + iommufd_object_abort(ucmd->ictx, &sobj->obj); + return rc; +} + +void iommufd_selftest_destroy(struct iommufd_object *obj) +{ + struct selftest_obj *sobj = container_of(obj, struct selftest_obj, obj); + + switch (sobj->type) { + case TYPE_IDEV: + iopt_table_remove_domain(&sobj->idev.hwpt->ioas->iopt, + sobj->idev.hwpt->domain); + iommufd_hw_pagetable_put(sobj->idev.ictx, sobj->idev.hwpt); + break; + case TYPE_ACCESS: + iopt_unaccess_pages(&sobj->access.ioas->iopt, + sobj->access.iova, sobj->access.length); + refcount_dec(&sobj->access.ioas->obj.users); + break; + } +} + +int iommufd_test(struct iommufd_ucmd *ucmd) +{ + struct iommu_test_cmd *cmd = ucmd->cmd; + + switch (cmd->op) { + case IOMMU_TEST_OP_ADD_RESERVED: + return iommufd_test_add_reserved(ucmd, cmd->id, + cmd->add_reserved.start, + cmd->add_reserved.length); + case IOMMU_TEST_OP_MOCK_DOMAIN: + return iommufd_test_mock_domain(ucmd, cmd); + case IOMMU_TEST_OP_MD_CHECK_MAP: + return iommufd_test_md_check_pa( + ucmd, cmd->id, cmd->check_map.iova, + cmd->check_map.length, + u64_to_user_ptr(cmd->check_map.uptr)); + case IOMMU_TEST_OP_MD_CHECK_REFS: + return iommufd_test_md_check_refs( + ucmd, u64_to_user_ptr(cmd->check_refs.uptr), + cmd->check_refs.length, cmd->check_refs.refs); + case IOMMU_TEST_OP_ACCESS_PAGES: + return iommufd_test_access_pages( + ucmd, cmd->id, cmd->access_pages.iova, + cmd->access_pages.length, + u64_to_user_ptr(cmd->access_pages.uptr), + cmd->access_pages.flags); + case IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT: + iommufd_test_memory_limit = cmd->memory_limit.limit; + return 0; + default: + return -EOPNOTSUPP; + } +} diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile index d08fe4cfe81152..5533a3b2e8af51 100644 --- a/tools/testing/selftests/Makefile +++ b/tools/testing/selftests/Makefile @@ -21,6 +21,7 @@ TARGETS += ftrace TARGETS += futex TARGETS += gpio TARGETS += intel_pstate +TARGETS += iommu TARGETS += ipc TARGETS += ir TARGETS += kcmp diff --git a/tools/testing/selftests/iommu/.gitignore b/tools/testing/selftests/iommu/.gitignore new file mode 100644 index 00000000000000..c6bd07e7ff59b3 --- /dev/null +++ b/tools/testing/selftests/iommu/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +/iommufd diff --git a/tools/testing/selftests/iommu/Makefile b/tools/testing/selftests/iommu/Makefile new file mode 100644 index 00000000000000..7bc38b3beaeb20 --- /dev/null +++ b/tools/testing/selftests/iommu/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +CFLAGS += -Wall -O2 -Wno-unused-function +CFLAGS += -I../../../../include/uapi/ +CFLAGS += -I../../../../include/ + +CFLAGS += -D_GNU_SOURCE + +TEST_GEN_PROGS := +TEST_GEN_PROGS += iommufd + +include ../lib.mk diff --git a/tools/testing/selftests/iommu/config b/tools/testing/selftests/iommu/config new file mode 100644 index 00000000000000..6c4f901d6fed3c --- /dev/null +++ b/tools/testing/selftests/iommu/config @@ -0,0 +1,2 @@ +CONFIG_IOMMUFD +CONFIG_IOMMUFD_TEST diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c new file mode 100644 index 00000000000000..5c47d706ed9449 --- /dev/null +++ b/tools/testing/selftests/iommu/iommufd.c @@ -0,0 +1,1225 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES */ +#include +#include +#include +#include +#include +#include +#include + +#include "../kselftest_harness.h" + +#define __EXPORTED_HEADERS__ +#include +#include +#include "../../../../drivers/iommu/iommufd/iommufd_test.h" + +static void *buffer; + +static unsigned long PAGE_SIZE; +static unsigned long HUGEPAGE_SIZE; +static unsigned long BUFFER_SIZE; + +#define MOCK_PAGE_SIZE (PAGE_SIZE / 2) + +static unsigned long get_huge_page_size(void) +{ + char buf[80]; + int ret; + int fd; + + fd = open("/sys/kernel/mm/transparent_hugepage/hpage_pmd_size", + O_RDONLY); + if (fd < 0) + return 2 * 1024 * 1024; + + ret = read(fd, buf, sizeof(buf)); + close(fd); + if (ret <= 0 || ret == sizeof(buf)) + return 2 * 1024 * 1024; + buf[ret] = 0; + return strtoul(buf, NULL, 10); +} + +static __attribute__((constructor)) void setup_sizes(void) +{ + int rc; + + PAGE_SIZE = sysconf(_SC_PAGE_SIZE); + HUGEPAGE_SIZE = get_huge_page_size(); + + BUFFER_SIZE = PAGE_SIZE * 16; + rc = posix_memalign(&buffer, HUGEPAGE_SIZE, BUFFER_SIZE); + assert(rc || buffer || (uintptr_t)buffer % HUGEPAGE_SIZE == 0); +} + +/* + * Have the kernel check the refcount on pages. I don't know why a freshly + * mmap'd anon non-compound page starts out with a ref of 3 + */ +#define check_refs(_ptr, _length, _refs) \ + ({ \ + struct iommu_test_cmd test_cmd = { \ + .size = sizeof(test_cmd), \ + .op = IOMMU_TEST_OP_MD_CHECK_REFS, \ + .check_refs = { .length = _length, \ + .uptr = (uintptr_t)(_ptr), \ + .refs = _refs }, \ + }; \ + ASSERT_EQ(0, \ + ioctl(self->fd, \ + _IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_REFS), \ + &test_cmd)); \ + }) + +/* Hack to make assertions more readable */ +#define _IOMMU_TEST_CMD(x) IOMMU_TEST_CMD + +#define EXPECT_ERRNO(expected_errno, cmd) \ + ({ \ + ASSERT_EQ(-1, cmd); \ + EXPECT_EQ(expected_errno, errno); \ + }) + +FIXTURE(iommufd) { + int fd; +}; + +FIXTURE_SETUP(iommufd) { + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); +} + +FIXTURE_TEARDOWN(iommufd) { + ASSERT_EQ(0, close(self->fd)); +} + +TEST_F(iommufd, simple_close) +{ +} + +TEST_F(iommufd, cmd_fail) +{ + struct iommu_destroy cmd = { .size = sizeof(cmd), .id = 0 }; + + /* object id is invalid */ + EXPECT_ERRNO(ENOENT, ioctl(self->fd, IOMMU_DESTROY, &cmd)); + /* Bad pointer */ + EXPECT_ERRNO(EFAULT, ioctl(self->fd, IOMMU_DESTROY, NULL)); + /* Unknown ioctl */ + EXPECT_ERRNO(ENOTTY, + ioctl(self->fd, _IO(IOMMUFD_TYPE, IOMMUFD_CMD_BASE - 1), + &cmd)); +} + +TEST_F(iommufd, cmd_ex_fail) +{ + struct { + struct iommu_destroy cmd; + __u64 future; + } cmd = { .cmd = { .size = sizeof(cmd), .id = 0 } }; + + /* object id is invalid and command is longer */ + EXPECT_ERRNO(ENOENT, ioctl(self->fd, IOMMU_DESTROY, &cmd)); + /* future area is non-zero */ + cmd.future = 1; + EXPECT_ERRNO(E2BIG, ioctl(self->fd, IOMMU_DESTROY, &cmd)); + /* Original command "works" */ + cmd.cmd.size = sizeof(cmd.cmd); + EXPECT_ERRNO(ENOENT, ioctl(self->fd, IOMMU_DESTROY, &cmd)); + /* Short command fails */ + cmd.cmd.size = sizeof(cmd.cmd) - 1; + EXPECT_ERRNO(EOPNOTSUPP, ioctl(self->fd, IOMMU_DESTROY, &cmd)); +} + +FIXTURE(iommufd_ioas) { + int fd; + uint32_t ioas_id; + uint32_t domain_id; + uint64_t base_iova; +}; + +FIXTURE_VARIANT(iommufd_ioas) { + unsigned int mock_domains; + unsigned int memory_limit; +}; + +FIXTURE_SETUP(iommufd_ioas) { + struct iommu_test_cmd memlimit_cmd = { + .size = sizeof(memlimit_cmd), + .op = IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT, + .memory_limit = {.limit = variant->memory_limit}, + }; + struct iommu_ioas_alloc alloc_cmd = { + .size = sizeof(alloc_cmd), + }; + unsigned int i; + + if (!variant->memory_limit) + memlimit_cmd.memory_limit.limit = 65536; + + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_ALLOC, &alloc_cmd)); + ASSERT_NE(0, alloc_cmd.out_ioas_id); + self->ioas_id = alloc_cmd.out_ioas_id; + + ASSERT_EQ(0, ioctl(self->fd, + _IOMMU_TEST_CMD(IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT), + &memlimit_cmd)); + + for (i = 0; i != variant->mock_domains; i++) { + struct iommu_test_cmd test_cmd = { + .size = sizeof(test_cmd), + .op = IOMMU_TEST_OP_MOCK_DOMAIN, + .id = self->ioas_id, + }; + + ASSERT_EQ(0, ioctl(self->fd, + _IOMMU_TEST_CMD(IOMMU_TEST_OP_MOCK_DOMAIN), + &test_cmd)); + EXPECT_NE(0, test_cmd.id); + self->domain_id = test_cmd.id; + self->base_iova = MOCK_APERTURE_START; + } +} + +FIXTURE_TEARDOWN(iommufd_ioas) { + struct iommu_test_cmd memlimit_cmd = { + .size = sizeof(memlimit_cmd), + .op = IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT, + .memory_limit = {.limit = 65536}, + }; + + ASSERT_EQ(0, ioctl(self->fd, + _IOMMU_TEST_CMD(IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT), + &memlimit_cmd)); + ASSERT_EQ(0, close(self->fd)); + + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + check_refs(buffer, BUFFER_SIZE, 0); + ASSERT_EQ(0, close(self->fd)); +} + +FIXTURE_VARIANT_ADD(iommufd_ioas, no_domain) { +}; + +FIXTURE_VARIANT_ADD(iommufd_ioas, mock_domain) { + .mock_domains = 1, +}; + +FIXTURE_VARIANT_ADD(iommufd_ioas, two_mock_domain) { + .mock_domains = 2, +}; + +FIXTURE_VARIANT_ADD(iommufd_ioas, mock_domain_limit) { + .mock_domains = 1, + .memory_limit = 16, +}; + +TEST_F(iommufd_ioas, ioas_auto_destroy) +{ +} + +TEST_F(iommufd_ioas, ioas_destroy) +{ + struct iommu_destroy destroy_cmd = { + .size = sizeof(destroy_cmd), + .id = self->ioas_id, + }; + + if (self->domain_id) { + /* IOAS cannot be freed while a domain is on it */ + EXPECT_ERRNO(EBUSY, + ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + } else { + /* Can allocate and manually free an IOAS table */ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + } +} + +TEST_F(iommufd_ioas, ioas_area_destroy) +{ + struct iommu_destroy destroy_cmd = { + .size = sizeof(destroy_cmd), + .id = self->ioas_id, + }; + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .ioas_id = self->ioas_id, + .user_va = (uintptr_t)buffer, + .length = PAGE_SIZE, + .iova = self->base_iova, + }; + + /* Adding an area does not change ability to destroy */ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + if (self->domain_id) + EXPECT_ERRNO(EBUSY, + ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + else + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); +} + +TEST_F(iommufd_ioas, ioas_area_auto_destroy) +{ + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .ioas_id = self->ioas_id, + .user_va = (uintptr_t)buffer, + .length = PAGE_SIZE, + }; + int i; + + /* Can allocate and automatically free an IOAS table with many areas */ + for (i = 0; i != 10; i++) { + map_cmd.iova = self->base_iova + i * PAGE_SIZE; + ASSERT_EQ(0, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + } +} + +TEST_F(iommufd_ioas, area) +{ + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .ioas_id = self->ioas_id, + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .length = PAGE_SIZE, + .user_va = (uintptr_t)buffer, + }; + struct iommu_ioas_unmap unmap_cmd = { + .size = sizeof(unmap_cmd), + .ioas_id = self->ioas_id, + .length = PAGE_SIZE, + }; + int i; + + /* Unmap fails if nothing is mapped */ + for (i = 0; i != 10; i++) { + unmap_cmd.iova = i * PAGE_SIZE; + EXPECT_ERRNO(ENOENT, ioctl(self->fd, IOMMU_IOAS_UNMAP, + &unmap_cmd)); + } + + /* Unmap works */ + for (i = 0; i != 10; i++) { + map_cmd.iova = self->base_iova + i * PAGE_SIZE; + ASSERT_EQ(0, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + } + for (i = 0; i != 10; i++) { + unmap_cmd.iova = self->base_iova + i * PAGE_SIZE; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_UNMAP, + &unmap_cmd)); + } + + /* Split fails */ + map_cmd.length = PAGE_SIZE * 2; + map_cmd.iova = self->base_iova + 16 * PAGE_SIZE; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + unmap_cmd.iova = self->base_iova + 16 * PAGE_SIZE; + EXPECT_ERRNO(ENOENT, + ioctl(self->fd, IOMMU_IOAS_UNMAP, &unmap_cmd)); + unmap_cmd.iova = self->base_iova + 17 * PAGE_SIZE; + EXPECT_ERRNO(ENOENT, + ioctl(self->fd, IOMMU_IOAS_UNMAP, &unmap_cmd)); + + /* Over map fails */ + map_cmd.length = PAGE_SIZE * 2; + map_cmd.iova = self->base_iova + 16 * PAGE_SIZE; + EXPECT_ERRNO(EADDRINUSE, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + map_cmd.length = PAGE_SIZE; + map_cmd.iova = self->base_iova + 16 * PAGE_SIZE; + EXPECT_ERRNO(EADDRINUSE, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + map_cmd.length = PAGE_SIZE; + map_cmd.iova = self->base_iova + 17 * PAGE_SIZE; + EXPECT_ERRNO(EADDRINUSE, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + map_cmd.length = PAGE_SIZE * 2; + map_cmd.iova = self->base_iova + 15 * PAGE_SIZE; + EXPECT_ERRNO(EADDRINUSE, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + map_cmd.length = PAGE_SIZE * 3; + map_cmd.iova = self->base_iova + 15 * PAGE_SIZE; + EXPECT_ERRNO(EADDRINUSE, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + + /* unmap all works */ + unmap_cmd.iova = 0; + unmap_cmd.length = UINT64_MAX; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_UNMAP, &unmap_cmd)); +} + +TEST_F(iommufd_ioas, area_auto_iova) +{ + struct iommu_test_cmd test_cmd = { + .size = sizeof(test_cmd), + .op = IOMMU_TEST_OP_ADD_RESERVED, + .id = self->ioas_id, + .add_reserved = { .start = PAGE_SIZE * 4, + .length = PAGE_SIZE * 100 }, + }; + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .ioas_id = self->ioas_id, + .length = PAGE_SIZE, + .user_va = (uintptr_t)buffer, + }; + struct iommu_ioas_unmap unmap_cmd = { + .size = sizeof(unmap_cmd), + .ioas_id = self->ioas_id, + .length = PAGE_SIZE, + }; + uint64_t iovas[10]; + int i; + + /* Simple 4k pages */ + for (i = 0; i != 10; i++) { + ASSERT_EQ(0, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + iovas[i] = map_cmd.iova; + } + for (i = 0; i != 10; i++) { + unmap_cmd.iova = iovas[i]; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_UNMAP, + &unmap_cmd)); + } + + /* Kernel automatically aligns IOVAs properly */ + if (self->domain_id) + map_cmd.user_va = (uintptr_t)buffer; + else + map_cmd.user_va = 1UL << 31; + for (i = 0; i != 10; i++) { + map_cmd.length = PAGE_SIZE * (i + 1); + ASSERT_EQ(0, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + iovas[i] = map_cmd.iova; + EXPECT_EQ(0, map_cmd.iova % (1UL << (ffs(map_cmd.length)-1))); + } + for (i = 0; i != 10; i++) { + unmap_cmd.length = PAGE_SIZE * (i + 1); + unmap_cmd.iova = iovas[i]; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_UNMAP, + &unmap_cmd)); + } + + /* Avoids a reserved region */ + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_ADD_RESERVED), + &test_cmd)); + for (i = 0; i != 10; i++) { + map_cmd.length = PAGE_SIZE * (i + 1); + ASSERT_EQ(0, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + iovas[i] = map_cmd.iova; + EXPECT_EQ(0, map_cmd.iova % (1UL << (ffs(map_cmd.length)-1))); + EXPECT_EQ(false, + map_cmd.iova > test_cmd.add_reserved.start && + map_cmd.iova < + test_cmd.add_reserved.start + + test_cmd.add_reserved.length); + } + for (i = 0; i != 10; i++) { + unmap_cmd.length = PAGE_SIZE * (i + 1); + unmap_cmd.iova = iovas[i]; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_UNMAP, + &unmap_cmd)); + } +} + +TEST_F(iommufd_ioas, copy_area) +{ + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .ioas_id = self->ioas_id, + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .length = PAGE_SIZE, + .user_va = (uintptr_t)buffer, + }; + struct iommu_ioas_copy copy_cmd = { + .size = sizeof(copy_cmd), + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .dst_ioas_id = self->ioas_id, + .src_ioas_id = self->ioas_id, + .length = PAGE_SIZE, + }; + struct iommu_ioas_alloc alloc_cmd = { + .size = sizeof(alloc_cmd), + }; + + map_cmd.iova = self->base_iova; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + + /* Copy inside a single IOAS */ + copy_cmd.src_iova = self->base_iova; + copy_cmd.dst_iova = self->base_iova + PAGE_SIZE; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_COPY, ©_cmd)); + + /* Copy between IOAS's */ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_ALLOC, &alloc_cmd)); + ASSERT_NE(0, alloc_cmd.out_ioas_id); + copy_cmd.src_iova = self->base_iova; + copy_cmd.dst_iova = 0; + copy_cmd.dst_ioas_id = alloc_cmd.out_ioas_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_COPY, ©_cmd)); +} + +TEST_F(iommufd_ioas, iova_ranges) +{ + struct iommu_test_cmd test_cmd = { + .size = sizeof(test_cmd), + .op = IOMMU_TEST_OP_ADD_RESERVED, + .id = self->ioas_id, + .add_reserved = { .start = PAGE_SIZE, .length = PAGE_SIZE }, + }; + struct iommu_ioas_iova_ranges *cmd = (void *)buffer; + + *cmd = (struct iommu_ioas_iova_ranges){ + .size = BUFFER_SIZE, + .ioas_id = self->ioas_id, + }; + + /* Range can be read */ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_IOVA_RANGES, cmd)); + EXPECT_EQ(1, cmd->out_num_iovas); + if (!self->domain_id) { + EXPECT_EQ(0, cmd->out_valid_iovas[0].start); + EXPECT_EQ(SIZE_MAX, cmd->out_valid_iovas[0].last); + } else { + EXPECT_EQ(MOCK_APERTURE_START, cmd->out_valid_iovas[0].start); + EXPECT_EQ(MOCK_APERTURE_LAST, cmd->out_valid_iovas[0].last); + } + memset(cmd->out_valid_iovas, 0, + sizeof(cmd->out_valid_iovas[0]) * cmd->out_num_iovas); + + /* Buffer too small */ + cmd->size = sizeof(*cmd); + EXPECT_ERRNO(EMSGSIZE, + ioctl(self->fd, IOMMU_IOAS_IOVA_RANGES, cmd)); + EXPECT_EQ(1, cmd->out_num_iovas); + EXPECT_EQ(0, cmd->out_valid_iovas[0].start); + EXPECT_EQ(0, cmd->out_valid_iovas[0].last); + + /* 2 ranges */ + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_ADD_RESERVED), + &test_cmd)); + cmd->size = BUFFER_SIZE; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_IOVA_RANGES, cmd)); + if (!self->domain_id) { + EXPECT_EQ(2, cmd->out_num_iovas); + EXPECT_EQ(0, cmd->out_valid_iovas[0].start); + EXPECT_EQ(PAGE_SIZE - 1, cmd->out_valid_iovas[0].last); + EXPECT_EQ(PAGE_SIZE * 2, cmd->out_valid_iovas[1].start); + EXPECT_EQ(SIZE_MAX, cmd->out_valid_iovas[1].last); + } else { + EXPECT_EQ(1, cmd->out_num_iovas); + EXPECT_EQ(MOCK_APERTURE_START, cmd->out_valid_iovas[0].start); + EXPECT_EQ(MOCK_APERTURE_LAST, cmd->out_valid_iovas[0].last); + } + memset(cmd->out_valid_iovas, 0, + sizeof(cmd->out_valid_iovas[0]) * cmd->out_num_iovas); + + /* Buffer too small */ + cmd->size = sizeof(*cmd) + sizeof(cmd->out_valid_iovas[0]); + if (!self->domain_id) { + EXPECT_ERRNO(EMSGSIZE, + ioctl(self->fd, IOMMU_IOAS_IOVA_RANGES, cmd)); + EXPECT_EQ(2, cmd->out_num_iovas); + EXPECT_EQ(0, cmd->out_valid_iovas[0].start); + EXPECT_EQ(PAGE_SIZE - 1, cmd->out_valid_iovas[0].last); + } else { + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_IOVA_RANGES, cmd)); + EXPECT_EQ(1, cmd->out_num_iovas); + EXPECT_EQ(MOCK_APERTURE_START, cmd->out_valid_iovas[0].start); + EXPECT_EQ(MOCK_APERTURE_LAST, cmd->out_valid_iovas[0].last); + } + EXPECT_EQ(0, cmd->out_valid_iovas[1].start); + EXPECT_EQ(0, cmd->out_valid_iovas[1].last); +} + +TEST_F(iommufd_ioas, access) +{ + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .ioas_id = self->ioas_id, + .user_va = (uintptr_t)buffer, + .length = BUFFER_SIZE, + .iova = MOCK_APERTURE_START, + }; + struct iommu_test_cmd access_cmd = { + .size = sizeof(access_cmd), + .op = IOMMU_TEST_OP_ACCESS_PAGES, + .id = self->ioas_id, + .access_pages = { .iova = MOCK_APERTURE_START, + .length = BUFFER_SIZE, + .uptr = (uintptr_t)buffer }, + }; + struct iommu_test_cmd mock_cmd = { + .size = sizeof(mock_cmd), + .op = IOMMU_TEST_OP_MOCK_DOMAIN, + .id = self->ioas_id, + }; + struct iommu_test_cmd check_map_cmd = { + .size = sizeof(check_map_cmd), + .op = IOMMU_TEST_OP_MD_CHECK_MAP, + .check_map = { .iova = MOCK_APERTURE_START, + .length = BUFFER_SIZE, + .uptr = (uintptr_t)buffer }, + }; + struct iommu_destroy destroy_cmd = { .size = sizeof(destroy_cmd) }; + uint32_t id; + + /* Single map/unmap */ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_ACCESS_PAGES), + &access_cmd)); + destroy_cmd.id = access_cmd.access_pages.out_access_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + + /* Double user */ + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_ACCESS_PAGES), + &access_cmd)); + id = access_cmd.access_pages.out_access_id; + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_ACCESS_PAGES), + &access_cmd)); + destroy_cmd.id = access_cmd.access_pages.out_access_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + destroy_cmd.id = id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + + /* Add/remove a domain with a user */ + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_ACCESS_PAGES), + &access_cmd)); + ASSERT_EQ(0, ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_MOCK_DOMAIN), + &mock_cmd)); + check_map_cmd.id = mock_cmd.id; + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_MAP), + &check_map_cmd)); + destroy_cmd.id = mock_cmd.mock_domain.device_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + destroy_cmd.id = mock_cmd.id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + destroy_cmd.id = access_cmd.access_pages.out_access_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); +} + +FIXTURE(iommufd_mock_domain) { + int fd; + uint32_t ioas_id; + uint32_t domain_id; + uint32_t domain_ids[2]; + int mmap_flags; + size_t mmap_buf_size; +}; + +FIXTURE_VARIANT(iommufd_mock_domain) { + unsigned int mock_domains; + bool hugepages; +}; + +FIXTURE_SETUP(iommufd_mock_domain) +{ + struct iommu_ioas_alloc alloc_cmd = { + .size = sizeof(alloc_cmd), + }; + struct iommu_test_cmd test_cmd = { + .size = sizeof(test_cmd), + .op = IOMMU_TEST_OP_MOCK_DOMAIN, + }; + unsigned int i; + + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_ALLOC, &alloc_cmd)); + ASSERT_NE(0, alloc_cmd.out_ioas_id); + self->ioas_id = alloc_cmd.out_ioas_id; + + ASSERT_GE(ARRAY_SIZE(self->domain_ids), variant->mock_domains); + + for (i = 0; i != variant->mock_domains; i++) { + test_cmd.id = self->ioas_id; + ASSERT_EQ(0, ioctl(self->fd, + _IOMMU_TEST_CMD(IOMMU_TEST_OP_MOCK_DOMAIN), + &test_cmd)); + EXPECT_NE(0, test_cmd.id); + self->domain_ids[i] = test_cmd.id; + } + self->domain_id = self->domain_ids[0]; + + self->mmap_flags = MAP_SHARED | MAP_ANONYMOUS; + self->mmap_buf_size = PAGE_SIZE * 8; + if (variant->hugepages) { + /* + * MAP_POPULATE will cause the kernel to fail mmap if THPs are + * not available. + */ + self->mmap_flags |= MAP_HUGETLB | MAP_POPULATE; + self->mmap_buf_size = HUGEPAGE_SIZE * 2; + } +} + +FIXTURE_TEARDOWN(iommufd_mock_domain) { + ASSERT_EQ(0, close(self->fd)); + + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + check_refs(buffer, BUFFER_SIZE, 0); + ASSERT_EQ(0, close(self->fd)); +} + +FIXTURE_VARIANT_ADD(iommufd_mock_domain, one_domain) { + .mock_domains = 1, + .hugepages = false, +}; + +FIXTURE_VARIANT_ADD(iommufd_mock_domain, two_domains) { + .mock_domains = 2, + .hugepages = false, +}; + +FIXTURE_VARIANT_ADD(iommufd_mock_domain, one_domain_hugepage) { + .mock_domains = 1, + .hugepages = true, +}; + +FIXTURE_VARIANT_ADD(iommufd_mock_domain, two_domains_hugepage) { + .mock_domains = 2, + .hugepages = true, +}; + +/* Have the kernel check that the user pages made it to the iommu_domain */ +#define check_mock_iova(_ptr, _iova, _length) \ + ({ \ + struct iommu_test_cmd check_map_cmd = { \ + .size = sizeof(check_map_cmd), \ + .op = IOMMU_TEST_OP_MD_CHECK_MAP, \ + .id = self->domain_id, \ + .check_map = { .iova = _iova, \ + .length = _length, \ + .uptr = (uintptr_t)(_ptr) }, \ + }; \ + ASSERT_EQ(0, \ + ioctl(self->fd, \ + _IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_MAP), \ + &check_map_cmd)); \ + if (self->domain_ids[1]) { \ + check_map_cmd.id = self->domain_ids[1]; \ + ASSERT_EQ(0, \ + ioctl(self->fd, \ + _IOMMU_TEST_CMD( \ + IOMMU_TEST_OP_MD_CHECK_MAP), \ + &check_map_cmd)); \ + } \ + }) + +TEST_F(iommufd_mock_domain, basic) +{ + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .ioas_id = self->ioas_id, + }; + struct iommu_ioas_unmap unmap_cmd = { + .size = sizeof(unmap_cmd), + .ioas_id = self->ioas_id, + }; + size_t buf_size = self->mmap_buf_size; + uint8_t *buf; + + /* Simple one page map */ + map_cmd.user_va = (uintptr_t)buffer; + map_cmd.length = PAGE_SIZE; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + check_mock_iova(buffer, map_cmd.iova, map_cmd.length); + + buf = mmap(0, buf_size, PROT_READ | PROT_WRITE, self->mmap_flags, -1, + 0); + ASSERT_NE(MAP_FAILED, buf); + + /* EFAULT half way through mapping */ + ASSERT_EQ(0, munmap(buf + buf_size / 2, buf_size / 2)); + map_cmd.user_va = (uintptr_t)buf; + map_cmd.length = buf_size; + EXPECT_ERRNO(EFAULT, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + + /* EFAULT on first page */ + ASSERT_EQ(0, munmap(buf, buf_size / 2)); + EXPECT_ERRNO(EFAULT, + ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); +} + +TEST_F(iommufd_mock_domain, all_aligns) +{ + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .ioas_id = self->ioas_id, + }; + struct iommu_ioas_unmap unmap_cmd = { + .size = sizeof(unmap_cmd), + .ioas_id = self->ioas_id, + }; + size_t test_step = + variant->hugepages ? (self->mmap_buf_size / 16) : MOCK_PAGE_SIZE; + size_t buf_size = self->mmap_buf_size; + unsigned int start; + unsigned int end; + uint8_t *buf; + + buf = mmap(0, buf_size, PROT_READ | PROT_WRITE, self->mmap_flags, -1, 0); + ASSERT_NE(MAP_FAILED, buf); + check_refs(buf, buf_size, 0); + + /* + * Map every combination of page size and alignment within a big region, + * less for hugepage case as it takes so long to finish. + */ + for (start = 0; start < buf_size; start += test_step) { + map_cmd.user_va = (uintptr_t)buf + start; + if (variant->hugepages) + end = buf_size; + else + end = start + MOCK_PAGE_SIZE; + for (; end < buf_size; end += MOCK_PAGE_SIZE) { + map_cmd.length = end - start; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, + &map_cmd)); + check_mock_iova(buf + start, map_cmd.iova, + map_cmd.length); + check_refs(buf + start / PAGE_SIZE * PAGE_SIZE, + end / PAGE_SIZE * PAGE_SIZE - + start / PAGE_SIZE * PAGE_SIZE, + 1); + + unmap_cmd.iova = map_cmd.iova; + unmap_cmd.length = end - start; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_UNMAP, + &unmap_cmd)); + } + } + check_refs(buf, buf_size, 0); + ASSERT_EQ(0, munmap(buf, buf_size)); +} + +TEST_F(iommufd_mock_domain, all_aligns_copy) +{ + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .ioas_id = self->ioas_id, + }; + struct iommu_ioas_unmap unmap_cmd = { + .size = sizeof(unmap_cmd), + .ioas_id = self->ioas_id, + }; + struct iommu_test_cmd add_mock_pt = { + .size = sizeof(add_mock_pt), + .op = IOMMU_TEST_OP_MOCK_DOMAIN, + }; + struct iommu_destroy destroy_cmd = { + .size = sizeof(destroy_cmd), + }; + size_t test_step = + variant->hugepages ? self->mmap_buf_size / 16 : MOCK_PAGE_SIZE; + size_t buf_size = self->mmap_buf_size; + unsigned int start; + unsigned int end; + uint8_t *buf; + + buf = mmap(0, buf_size, PROT_READ | PROT_WRITE, self->mmap_flags, -1, 0); + ASSERT_NE(MAP_FAILED, buf); + check_refs(buf, buf_size, 0); + + /* + * Map every combination of page size and alignment within a big region, + * less for hugepage case as it takes so long to finish. + */ + for (start = 0; start < buf_size; start += test_step) { + map_cmd.user_va = (uintptr_t)buf + start; + if (variant->hugepages) + end = buf_size; + else + end = start + MOCK_PAGE_SIZE; + for (; end < buf_size; end += MOCK_PAGE_SIZE) { + unsigned int old_id; + + map_cmd.length = end - start; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, + &map_cmd)); + + /* Add and destroy a domain while the area exists */ + add_mock_pt.id = self->ioas_id; + ASSERT_EQ(0, ioctl(self->fd, + _IOMMU_TEST_CMD( + IOMMU_TEST_OP_MOCK_DOMAIN), + &add_mock_pt)); + old_id = self->domain_ids[1]; + self->domain_ids[1] = add_mock_pt.id; + + check_mock_iova(buf + start, map_cmd.iova, + map_cmd.length); + check_refs(buf + start / PAGE_SIZE * PAGE_SIZE, + end / PAGE_SIZE * PAGE_SIZE - + start / PAGE_SIZE * PAGE_SIZE, + 1); + + destroy_cmd.id = add_mock_pt.mock_domain.device_id; + ASSERT_EQ(0, + ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + destroy_cmd.id = add_mock_pt.id; + ASSERT_EQ(0, + ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + self->domain_ids[1] = old_id; + + unmap_cmd.iova = map_cmd.iova; + unmap_cmd.length = end - start; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_UNMAP, + &unmap_cmd)); + } + } + check_refs(buf, buf_size, 0); + ASSERT_EQ(0, munmap(buf, buf_size)); +} + +TEST_F(iommufd_mock_domain, user_copy) +{ + struct iommu_ioas_alloc alloc_cmd = { + .size = sizeof(alloc_cmd), + }; + struct iommu_ioas_map map_cmd = { + .size = sizeof(map_cmd), + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .ioas_id = self->ioas_id, + .user_va = (uintptr_t)buffer, + .length = BUFFER_SIZE, + .iova = MOCK_APERTURE_START, + }; + struct iommu_test_cmd access_cmd = { + .size = sizeof(access_cmd), + .op = IOMMU_TEST_OP_ACCESS_PAGES, + .id = self->ioas_id, + .access_pages = { .iova = MOCK_APERTURE_START, + .length = BUFFER_SIZE, + .uptr = (uintptr_t)buffer }, + }; + struct iommu_ioas_copy copy_cmd = { + .size = sizeof(copy_cmd), + .flags = IOMMU_IOAS_MAP_FIXED_IOVA, + .dst_ioas_id = self->ioas_id, + .src_iova = MOCK_APERTURE_START, + .dst_iova = MOCK_APERTURE_START, + .length = BUFFER_SIZE, + }; + struct iommu_destroy destroy_cmd = { .size = sizeof(destroy_cmd) }; + + /* Pin the pages in an IOAS with no domains then copy to an IOAS with domains */ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_ALLOC, &alloc_cmd)); + map_cmd.ioas_id = alloc_cmd.out_ioas_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_MAP, &map_cmd)); + access_cmd.id = alloc_cmd.out_ioas_id; + + ASSERT_EQ(0, + ioctl(self->fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_ACCESS_PAGES), + &access_cmd)); + copy_cmd.src_ioas_id = alloc_cmd.out_ioas_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_COPY, ©_cmd)); + check_mock_iova(buffer, map_cmd.iova, BUFFER_SIZE); + + destroy_cmd.id = access_cmd.access_pages.out_access_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); + destroy_cmd.id = alloc_cmd.out_ioas_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_DESTROY, &destroy_cmd)); +} + +FIXTURE(vfio_compat_nodev) { + int fd; +}; + +FIXTURE_SETUP(vfio_compat_nodev) { + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); +} + +FIXTURE_TEARDOWN(vfio_compat_nodev) { + ASSERT_EQ(0, close(self->fd)); +} + +TEST_F(vfio_compat_nodev, simple_ioctls) +{ + ASSERT_EQ(VFIO_API_VERSION, ioctl(self->fd, VFIO_GET_API_VERSION)); + ASSERT_EQ(1, ioctl(self->fd, VFIO_CHECK_EXTENSION, VFIO_TYPE1v2_IOMMU)); +} + +TEST_F(vfio_compat_nodev, unmap_cmd) +{ + struct vfio_iommu_type1_dma_unmap unmap_cmd = { + .iova = MOCK_APERTURE_START, + .size = PAGE_SIZE, + }; + + unmap_cmd.argsz = 1; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, VFIO_IOMMU_UNMAP_DMA, &unmap_cmd)); + + unmap_cmd.argsz = sizeof(unmap_cmd); + unmap_cmd.flags = 1 << 31; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, VFIO_IOMMU_UNMAP_DMA, &unmap_cmd)); + + unmap_cmd.flags = 0; + EXPECT_ERRNO(ENODEV, ioctl(self->fd, VFIO_IOMMU_UNMAP_DMA, &unmap_cmd)); +} + +TEST_F(vfio_compat_nodev, map_cmd) +{ + struct vfio_iommu_type1_dma_map map_cmd = { + .iova = MOCK_APERTURE_START, + .size = PAGE_SIZE, + .vaddr = (__u64)buffer, + }; + + map_cmd.argsz = 1; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, VFIO_IOMMU_MAP_DMA, &map_cmd)); + + map_cmd.argsz = sizeof(map_cmd); + map_cmd.flags = 1 << 31; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, VFIO_IOMMU_MAP_DMA, &map_cmd)); + + /* Requires a domain to be attached */ + map_cmd.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE; + EXPECT_ERRNO(ENODEV, ioctl(self->fd, VFIO_IOMMU_MAP_DMA, &map_cmd)); +} + +TEST_F(vfio_compat_nodev, info_cmd) +{ + struct vfio_iommu_type1_info info_cmd = {}; + + /* Invalid argsz */ + info_cmd.argsz = 1; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, VFIO_IOMMU_GET_INFO, &info_cmd)); + + info_cmd.argsz = sizeof(info_cmd); + EXPECT_ERRNO(ENODEV, ioctl(self->fd, VFIO_IOMMU_GET_INFO, &info_cmd)); +} + +TEST_F(vfio_compat_nodev, set_iommu_cmd) +{ + /* Requires a domain to be attached */ + EXPECT_ERRNO(ENODEV, ioctl(self->fd, VFIO_SET_IOMMU, VFIO_TYPE1v2_IOMMU)); +} + +TEST_F(vfio_compat_nodev, vfio_ioas) +{ + struct iommu_ioas_alloc alloc_cmd = { + .size = sizeof(alloc_cmd), + }; + struct iommu_vfio_ioas vfio_ioas_cmd = { + .size = sizeof(vfio_ioas_cmd), + .op = IOMMU_VFIO_IOAS_GET, + }; + + /* ENODEV if there is no compat ioas */ + EXPECT_ERRNO(ENODEV, ioctl(self->fd, IOMMU_VFIO_IOAS, &vfio_ioas_cmd)); + + /* Invalid id for set */ + vfio_ioas_cmd.op = IOMMU_VFIO_IOAS_SET; + EXPECT_ERRNO(ENOENT, ioctl(self->fd, IOMMU_VFIO_IOAS, &vfio_ioas_cmd)); + + /* Valid id for set*/ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_ALLOC, &alloc_cmd)); + vfio_ioas_cmd.ioas_id = alloc_cmd.out_ioas_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_VFIO_IOAS, &vfio_ioas_cmd)); + + /* Same id comes back from get */ + vfio_ioas_cmd.op = IOMMU_VFIO_IOAS_GET; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_VFIO_IOAS, &vfio_ioas_cmd)); + ASSERT_EQ(alloc_cmd.out_ioas_id, vfio_ioas_cmd.ioas_id); + + /* Clear works */ + vfio_ioas_cmd.op = IOMMU_VFIO_IOAS_CLEAR; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_VFIO_IOAS, &vfio_ioas_cmd)); + vfio_ioas_cmd.op = IOMMU_VFIO_IOAS_GET; + EXPECT_ERRNO(ENODEV, ioctl(self->fd, IOMMU_VFIO_IOAS, &vfio_ioas_cmd)); +} + +FIXTURE(vfio_compat_mock_domain) { + int fd; + uint32_t ioas_id; +}; + +FIXTURE_SETUP(vfio_compat_mock_domain) { + struct iommu_ioas_alloc alloc_cmd = { + .size = sizeof(alloc_cmd), + }; + struct iommu_test_cmd test_cmd = { + .size = sizeof(test_cmd), + .op = IOMMU_TEST_OP_MOCK_DOMAIN, + }; + struct iommu_vfio_ioas vfio_ioas_cmd = { + .size = sizeof(vfio_ioas_cmd), + .op = IOMMU_VFIO_IOAS_SET, + }; + + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + + /* Create what VFIO would consider a group */ + ASSERT_EQ(0, ioctl(self->fd, IOMMU_IOAS_ALLOC, &alloc_cmd)); + ASSERT_NE(0, alloc_cmd.out_ioas_id); + self->ioas_id = alloc_cmd.out_ioas_id; + test_cmd.id = self->ioas_id; + ASSERT_EQ(0, ioctl(self->fd, + _IOMMU_TEST_CMD(IOMMU_TEST_OP_MOCK_DOMAIN), + &test_cmd)); + EXPECT_NE(0, test_cmd.id); + + /* Attach it to the vfio compat */ + vfio_ioas_cmd.ioas_id = self->ioas_id; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_VFIO_IOAS, &vfio_ioas_cmd)); + ASSERT_EQ(0, ioctl(self->fd, VFIO_SET_IOMMU, VFIO_TYPE1v2_IOMMU)); +} + +FIXTURE_TEARDOWN(vfio_compat_mock_domain) { + ASSERT_EQ(0, close(self->fd)); + + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + check_refs(buffer, BUFFER_SIZE, 0); + ASSERT_EQ(0, close(self->fd)); +} + +TEST_F(vfio_compat_mock_domain, simple_close) +{ +} + +/* + * Execute an ioctl command stored in buffer and check that the result does not + * overflow memory. + */ +static bool is_filled(const void *buf, uint8_t c, size_t len) +{ + const uint8_t *cbuf = buf; + + for (; len; cbuf++, len--) + if (*cbuf != c) + return false; + return true; +} + +#define ioctl_check_buf(fd, cmd) \ + ({ \ + size_t _cmd_len = *(__u32 *)buffer; \ + \ + memset(buffer + _cmd_len, 0xAA, BUFFER_SIZE - _cmd_len); \ + ASSERT_EQ(0, ioctl(fd, cmd, buffer)); \ + ASSERT_EQ(true, is_filled(buffer + _cmd_len, 0xAA, \ + BUFFER_SIZE - _cmd_len)); \ + }) + +static void check_vfio_info_cap_chain(struct __test_metadata *_metadata, + struct vfio_iommu_type1_info *info_cmd) +{ + const struct vfio_info_cap_header *cap; + + ASSERT_GE(info_cmd->argsz, info_cmd->cap_offset + sizeof(*cap)); + cap = buffer + info_cmd->cap_offset; + while (true) { + size_t cap_size; + + if (cap->next) + cap_size = (buffer + cap->next) - (void *)cap; + else + cap_size = (buffer + info_cmd->argsz) - (void *)cap; + + switch (cap->id) { + case VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE: { + struct vfio_iommu_type1_info_cap_iova_range *data = + (void *)cap; + + ASSERT_EQ(1, data->header.version); + ASSERT_EQ(1, data->nr_iovas); + EXPECT_EQ(MOCK_APERTURE_START, + data->iova_ranges[0].start); + EXPECT_EQ(MOCK_APERTURE_LAST, + data->iova_ranges[0].end); + break; + } + case VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL: { + struct vfio_iommu_type1_info_dma_avail *data = + (void *)cap; + + ASSERT_EQ(1, data->header.version); + ASSERT_EQ(sizeof(*data), cap_size); + break; + } + default: + ASSERT_EQ(false, true); + break; + } + if (!cap->next) + break; + + ASSERT_GE(info_cmd->argsz, cap->next + sizeof(*cap)); + ASSERT_GE(buffer + cap->next, (void *)cap); + cap = buffer + cap->next; + } +} + +TEST_F(vfio_compat_mock_domain, get_info) +{ + struct vfio_iommu_type1_info *info_cmd = buffer; + unsigned int i; + size_t caplen; + + /* Pre-cap ABI */ + *info_cmd = (struct vfio_iommu_type1_info){ + .argsz = offsetof(struct vfio_iommu_type1_info, cap_offset), + }; + ioctl_check_buf(self->fd, VFIO_IOMMU_GET_INFO); + ASSERT_NE(0, info_cmd->iova_pgsizes); + ASSERT_EQ(VFIO_IOMMU_INFO_PGSIZES | VFIO_IOMMU_INFO_CAPS, + info_cmd->flags); + + /* Read the cap chain size */ + *info_cmd = (struct vfio_iommu_type1_info){ + .argsz = sizeof(*info_cmd), + }; + ioctl_check_buf(self->fd, VFIO_IOMMU_GET_INFO); + ASSERT_NE(0, info_cmd->iova_pgsizes); + ASSERT_EQ(VFIO_IOMMU_INFO_PGSIZES | VFIO_IOMMU_INFO_CAPS, + info_cmd->flags); + ASSERT_EQ(0, info_cmd->cap_offset); + ASSERT_LT(sizeof(*info_cmd), info_cmd->argsz); + + /* Read the caps, kernel should never create a corrupted caps */ + caplen = info_cmd->argsz; + for (i = sizeof(*info_cmd); i < caplen; i++) { + *info_cmd = (struct vfio_iommu_type1_info){ + .argsz = i, + }; + ioctl_check_buf(self->fd, VFIO_IOMMU_GET_INFO); + ASSERT_EQ(VFIO_IOMMU_INFO_PGSIZES | VFIO_IOMMU_INFO_CAPS, + info_cmd->flags); + if (!info_cmd->cap_offset) + continue; + check_vfio_info_cap_chain(_metadata, info_cmd); + } +} + +/* FIXME use fault injection to test memory failure paths */ +/* FIXME test VFIO_IOMMU_MAP_DMA */ +/* FIXME test VFIO_IOMMU_UNMAP_DMA */ +/* FIXME test 2k iova alignment */ + +TEST_HARNESS_MAIN