From patchwork Mon Mar 21 14:32:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12787319 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BE26369 for ; Mon, 21 Mar 2022 14:32:34 +0000 (UTC) Received: by mail-wr1-f49.google.com with SMTP id p9so20929294wra.12 for ; Mon, 21 Mar 2022 07:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jPNbf4VBXaKauQrD5GdOw/7C1sM2aDR3HnxDjhZ0elg=; b=K04KZ2llvCIBVjpLXRbj+FItZXFlk4ZVLcXMU/n3uOzyXQkjIt2p8UQRjAN1JRYeHw odN5bc3b7y61QwvNr5Voo9HYGe+n6sUBYkPIHRCLkL2b8MpipkOPtqLac92fMqy93U/2 9Xve7ZthNZPcBZUKdMEkBljxtgCh7T6f6FGbg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jPNbf4VBXaKauQrD5GdOw/7C1sM2aDR3HnxDjhZ0elg=; b=hcgejUBkePF+cF7hTZXkoDwZvq5tklOC1osZdLyPhwFuBQcSBKMqNsNvZ/6MW3gQYU S/UKwTZxVvYlOfvpojHC5UGv+Bgi19/zidXoG8/BoTThe6L0QIWk52+6Z4Lch5a4wKaE f3svdOafPpkB9ZRTOy9lQVwhwx9UCQ8ZiLjjCnwAsIkFItL6/pGjwaOdhkglxs1T/ZOw LP987SY81uDv43gUwcjqkGecQqvr7/MS1RT85M5yMej35VgF2+/fl4yRkB21AEwWsv49 ENDI4rMDjCScDQy7v+QPRGcFrgjvFTpKMbkSpiDj3ldRKpujThW49L7ZcZi8/INX+O8J Po2g== X-Gm-Message-State: AOAM5335cbvGQM3CXhzeB/Ti19hqfGySj4H6/AkHHjEKe3CAFYsSA1Ee wP9H3JfeEqK8g2OA9ofpOdiL0g== X-Google-Smtp-Source: ABdhPJxAUNMAkxYkB4uOST35byIe9LqZT6SPgd/wDbe3ZFo/1vnlqpEDwMr6f9llJhrZuMausBRxrg== X-Received: by 2002:adf:ea06:0:b0:203:ed67:6093 with SMTP id q6-20020adfea06000000b00203ed676093mr15652317wrm.596.1647873152722; Mon, 21 Mar 2022 07:32:32 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id u11-20020a05600c19cb00b00389efe9c512sm19092793wmq.23.2022.03.21.07.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 07:32:32 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 1/4] dt-bindings: add mfd/cros_ec definitions Date: Mon, 21 Mar 2022 14:32:19 +0000 Message-Id: <20220321143222.2523373-2-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a dt-bindings include file for cros_ec devicetree definition, define a pair of special purpose PWM channels in it. Signed-off-by: Fabio Baltieri --- include/dt-bindings/mfd/cros_ec.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/mfd/cros_ec.h diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cros_ec.h new file mode 100644 index 000000000000..e02414eae622 --- /dev/null +++ b/include/dt-bindings/mfd/cros_ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * DTS binding definitions used for the Chromium OS Embedded Controller. + * + * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MFD_CROS_EC_H +#define _DT_BINDINGS_MFD_CROS_EC_H + +/* Typed channel for keyboard backlight. */ +#define CROS_EC_PWM_DT_KB_LIGHT 0 +/* Typed channel for display backlight. */ +#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 +/* Number of typed channels. */ +#define CROS_EC_PWM_DT_COUNT 2 + +#endif From patchwork Mon Mar 21 14:32:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12787320 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE203369 for ; Mon, 21 Mar 2022 14:32:36 +0000 (UTC) Received: by mail-wm1-f50.google.com with SMTP id 125so356598wmc.3 for ; Mon, 21 Mar 2022 07:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=327v7tDtO2GmRxGp/EXz/K90M6uOA2heqpeDOYqPsME=; b=Gme6ELhnFvcMetNZIUvxqYQsfLCOlxkDNaNo+piNbLOzDEbxYZBKO6vEpqZAaB1WnN 81V4Ep3yPDZjGFeOmzqqRtolKOxSDjPAHW/wEE0CCraGO1m2C9LiWpUNwrBLOJV9kAnJ q2gkGbLvZoDdcx7pc6uK07DEGKdqU8qh23TAo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=327v7tDtO2GmRxGp/EXz/K90M6uOA2heqpeDOYqPsME=; b=KuGGM/NetdTha0YZd0eUipfgG0x2fBQFmi9qk7G3wjvauKZziuoBP57yN2PIof0s8V JnH8s750OJu4sZW377+tfJ6EKlmp9zg5W2kOhr3KhI7dGXcZbgk6kHOhEyTxJrEYqOnu PqnJHKV+rcGPu42R1HFq8xk4vTavmGwVC8Fxs2bgDChGtdvsV/wd1HAX6bmtPmoKirZZ EcKFhQoVtdd2xjZ0uG66f9UUrlr4Th7himgTI+ohV09XNxcy6Iwtp4RPy5y6DrPSw5tS k6/9D0GVCSZb9y19dDLySOjqUtN5mHl6kwpzWFW2a8td7GoWEpY7zkdPWOR7iDZmTUDc dPLQ== X-Gm-Message-State: AOAM531EWf6ZIKOnwVYsZhSYDzdYhT3hF9ISrDc7IjGiu3AG4JdbpUqg I1BA8ao0cKBQgUCJDsGrM5zA0A== X-Google-Smtp-Source: ABdhPJwzl2vh0K7GQ4OXRU1D1Fb+QB9pHhfF1JMG2/3unQTFxnQYcqU9FeomC+1Y42B7ORX5cObwuQ== X-Received: by 2002:a1c:e915:0:b0:37b:d847:e127 with SMTP id q21-20020a1ce915000000b0037bd847e127mr20044602wmc.180.1647873154996; Mon, 21 Mar 2022 07:32:34 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id u11-20020a05600c19cb00b00389efe9c512sm19092793wmq.23.2022.03.21.07.32.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 07:32:34 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 2/4] drivers: pwm: pwm-cros-ec: add channel type support Date: Mon, 21 Mar 2022 14:32:20 +0000 Message-Id: <20220321143222.2523373-3-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for EC_PWM_TYPE_DISPLAY_LIGHT and EC_PWM_TYPE_KB_LIGHT pwm types to the PWM cros_ec_pwm driver. This allows specifying one of these PWM channel by functionality, and let the EC firmware pick the correct channel, thus abstracting the hardware implementation from the kernel driver. Signed-off-by: Fabio Baltieri --- drivers/pwm/pwm-cros-ec.c | 80 +++++++++++++++++++++++++++++++-------- 1 file changed, 65 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 5e29d9c682c3..77867fd16c49 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -12,17 +12,21 @@ #include #include +#include + /** * struct cros_ec_pwm_device - Driver data for EC PWM * * @dev: Device node * @ec: Pointer to EC device * @chip: PWM controller chip + * @use_pwm_type: Use PWM types instead of generic channels */ struct cros_ec_pwm_device { struct device *dev; struct cros_ec_device *ec; struct pwm_chip chip; + bool use_pwm_type; }; /** @@ -58,14 +62,31 @@ static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) kfree(channel); } -static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) +static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type) { + switch (dt_index) { + case CROS_EC_PWM_DT_KB_LIGHT: + *pwm_type = EC_PWM_TYPE_KB_LIGHT; + return 0; + case CROS_EC_PWM_DT_DISPLAY_LIGHT: + *pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT; + return 0; + default: + return -EINVAL; + } +} + +static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index, + u16 duty) +{ + struct cros_ec_device *ec = ec_pwm->ec; struct { struct cros_ec_command msg; struct ec_params_pwm_set_duty params; } __packed buf; struct ec_params_pwm_set_duty *params = &buf.params; struct cros_ec_command *msg = &buf.msg; + int ret; memset(&buf, 0, sizeof(buf)); @@ -75,14 +96,25 @@ static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) msg->outsize = sizeof(*params); params->duty = duty; - params->pwm_type = EC_PWM_TYPE_GENERIC; - params->index = index; + + if (ec_pwm->use_pwm_type) { + ret = cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index = 0; + } else { + params->pwm_type = EC_PWM_TYPE_GENERIC; + params->index = index; + } return cros_ec_cmd_xfer_status(ec, msg); } -static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) +static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 index) { + struct cros_ec_device *ec = ec_pwm->ec; struct { struct cros_ec_command msg; union { @@ -102,8 +134,17 @@ static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) msg->insize = sizeof(*resp); msg->outsize = sizeof(*params); - params->pwm_type = EC_PWM_TYPE_GENERIC; - params->index = index; + if (ec_pwm->use_pwm_type) { + ret = cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index = 0; + } else { + params->pwm_type = EC_PWM_TYPE_GENERIC; + params->index = index; + } ret = cros_ec_cmd_xfer_status(ec, msg); if (ret < 0) @@ -133,7 +174,7 @@ static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, */ duty_cycle = state->enabled ? state->duty_cycle : 0; - ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle); + ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle); if (ret < 0) return ret; @@ -149,7 +190,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct cros_ec_pwm *channel = pwm_get_chip_data(pwm); int ret; - ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm); + ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm); if (ret < 0) { dev_err(chip->dev, "error getting initial duty: %d\n", ret); return; @@ -204,13 +245,13 @@ static const struct pwm_ops cros_ec_pwm_ops = { * of PWMs it supports directly, so we have to read the pwm duty cycle for * subsequent channels until we get an error. */ -static int cros_ec_num_pwms(struct cros_ec_device *ec) +static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm) { int i, ret; /* The index field is only 8 bits */ for (i = 0; i <= U8_MAX; i++) { - ret = cros_ec_pwm_get_duty(ec, i); + ret = cros_ec_pwm_get_duty(ec_pwm, i); /* * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM * responses; everything else is treated as an error. @@ -251,17 +292,26 @@ static int cros_ec_pwm_probe(struct platform_device *pdev) chip = &ec_pwm->chip; ec_pwm->ec = ec; + ec_pwm->use_pwm_type = of_property_read_bool( + dev->of_node, "google,use_pwm_type"); + /* PWM chip */ chip->dev = dev; chip->ops = &cros_ec_pwm_ops; chip->of_xlate = cros_ec_pwm_xlate; chip->of_pwm_n_cells = 1; - ret = cros_ec_num_pwms(ec); - if (ret < 0) { - dev_err(dev, "Couldn't find PWMs: %d\n", ret); - return ret; + + if (ec_pwm->use_pwm_type) { + chip->npwm = CROS_EC_PWM_DT_COUNT; + } else { + ret = cros_ec_num_pwms(ec_pwm); + if (ret < 0) { + dev_err(dev, "Couldn't find PWMs: %d\n", ret); + return ret; + } + chip->npwm = ret; } - chip->npwm = ret; + dev_dbg(dev, "Probed %u PWMs\n", chip->npwm); ret = pwmchip_add(chip); From patchwork Mon Mar 21 14:32:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12787321 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C44157D0 for ; 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Mon, 21 Mar 2022 07:32:36 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id u11-20020a05600c19cb00b00389efe9c512sm19092793wmq.23.2022.03.21.07.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 07:32:36 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 3/4] dt-bindings: update google,cros-ec-pwm documentation Date: Mon, 21 Mar 2022 14:32:21 +0000 Message-Id: <20220321143222.2523373-4-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update google,cros-ec-pwm node documentation to mention the google,use_pwm_type property. Signed-off-by: Fabio Baltieri --- .../devicetree/bindings/pwm/google,cros-ec-pwm.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 4cfbffd8414a..2224e8e07029 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -19,6 +19,12 @@ description: | properties: compatible: const: google,cros-ec-pwm + + google,use_pwm_type: + description: + Use PWM types (CROS_EC_PWM_DT_<...>) instead of generic channels. + type: boolean + "#pwm-cells": description: The cell specifies the PWM index. const: 1 From patchwork Mon Mar 21 14:32:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12787322 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFF715CC6 for ; Mon, 21 Mar 2022 14:32:39 +0000 (UTC) Received: by mail-wr1-f48.google.com with SMTP id h23so20351626wrb.8 for ; Mon, 21 Mar 2022 07:32:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RccDfbuFs/Yz2WrfhL+KkjoyAgUu2DNhvPj6SzPznLY=; b=MTu7SXp2mMCpLDiDwJeKrjiCt7ymx7U0UG1x1U6bTcaLMpAK5p8CBpfjbxlZvnr36d maBuFhYOfQZReSuaI9sCQW4R/chbZxL9lDaimRIeZ2mhkIgo0yiaaGr3nf1tGZJy7yQW 7CdcJCwmF/gQa/Miq1bugA74rDusfk870DyVw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RccDfbuFs/Yz2WrfhL+KkjoyAgUu2DNhvPj6SzPznLY=; b=feGXZWnbXX3tLIWHsU1xtVVBMEZJDGCFNBCREr1k05CihADwJvDimkN0353HoYHCLO v6kHoc0PBZeXyR1po/MhBWJSxd2eq5+9YnGRDEydKIB/31IKt1Ore9ll5ULM3BlEIpxd MMcwrJi+Q/MPChzIcR8Os2vOZIMrUkGdnOMjy9bsA/CSwPSNv5AV4ROOjq1xUhoa2iv1 I6MajIAvliCfF98++ooZqNuHcbmVjJCRk2JV0zrpY+DoiPdFMSEE5FeMC2ibgVNC360z GvpBUdigStE2jKutyr8Jwfg3piEbUgwF4N2GpEkULU8kWOFii3wc2h6SLKe0AF1DIT5+ xo9Q== X-Gm-Message-State: AOAM532+TteUKwdMFlMiWFH9Eg2gDOX53ZWSrA2l5pkrrIJwLOddFLa+ TiORrmo/9nFXbmRX4UezOT9iFA== X-Google-Smtp-Source: ABdhPJwOqVlJwIVTX5II/TL9iAxFRONy6Vxcp8R+6SJpH47T6+n5NfKeVrNnW5xISpuY3ByAgkxtJg== X-Received: by 2002:a5d:4e89:0:b0:204:2ee:d87 with SMTP id e9-20020a5d4e89000000b0020402ee0d87mr8406009wru.9.1647873158156; Mon, 21 Mar 2022 07:32:38 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id u11-20020a05600c19cb00b00389efe9c512sm19092793wmq.23.2022.03.21.07.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 07:32:37 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 4/4] arm64: dts: address cros-ec-pwm channels by type Date: Mon, 21 Mar 2022 14:32:22 +0000 Message-Id: <20220321143222.2523373-5-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update various cros-ec-pwm board definitions to address the keyboard and screen backlight PWM channels by type rather than channel number. This makes the instance independent by the actual hardware configuration, relying on the EC firmware to pick the right channel, and allows dropping few dtsi overrides as a consequence. Changed the node label used to cros_ec_pwm_type to avoid ambiguity about the pwm cell meaning. Signed-off-by: Fabio Baltieri --- .../dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 3 ++- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 8 +++++--- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 6 ++++-- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 4 +++- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 12 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index dec11a4eb59e..e2554a313deb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -15,13 +15,13 @@ pwmleds { compatible = "pwm-leds"; keyboard_backlight: keyboard-backlight { label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; }; -&cros_ec_pwm { +&cros_ec_pwm_type { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..eaea09d0f8cd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,10 +92,11 @@ volume_up { }; &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; status = "disabled"; + google,use_pwm_type; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..ff54687ab8bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include "mt8183.dtsi" #include "mt6358.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 14ed09f30a73..bcdfabe1860d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -77,10 +77,6 @@ &ap_spi_fp { status = "okay"; }; -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - &camcc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index bd5909ffb3dc..3deddbf97cb3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -222,7 +223,7 @@ backlight: backlight { num-interpolated-steps = <64>; default-brightness-level = <951>; - pwms = <&cros_ec_pwm 1>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; pinctrl-names = "default"; @@ -260,7 +261,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -543,9 +544,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use_pwm_type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 4619fa9fcacd..8676c8a677b9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -379,7 +380,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -771,9 +772,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use_pwm_type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index 0896a6151817..48bb2159e126 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,9 +20,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use_pwm_type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 4a6285a25f77..e6dc4bc57f01 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include "sdm845.dtsi" @@ -27,7 +28,7 @@ chosen { backlight: backlight { compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; pinctrl-names = "default"; @@ -708,9 +709,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use_pwm_type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts index 31ebb4e5fd33..5a076c2564f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -55,10 +55,6 @@ trackpad: trackpad@15 { }; }; -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - &cpu_alert0 { temperature = <65000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 9b2c679f5eca..324bb8871fe2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -198,6 +198,7 @@ backlight: backlight { power-supply = <&pp3300_disp>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; pwm-delay-us = <10000>; }; @@ -462,9 +463,10 @@ ap_i2c_tp: &i2c5 { }; &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use_pwm_type; }; usbc_extcon1: extcon1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 6863689df06f..e959a33af34b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -84,10 +84,6 @@ thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { }; }; -&backlight { - pwms = <&cros_ec_pwm 1>; -}; - &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..181159e9982d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include "rk3399.dtsi" #include "rk3399-op1-opp.dtsi"