From patchwork Mon Mar 21 15:38:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02B13C4321E for ; Mon, 21 Mar 2022 16:08:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350659AbiCUQJp (ORCPT ); Mon, 21 Mar 2022 12:09:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350653AbiCUQJo (ORCPT ); Mon, 21 Mar 2022 12:09:44 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DB8125283; Mon, 21 Mar 2022 09:08:18 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id n35so7232212wms.5; Mon, 21 Mar 2022 09:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=U4m+zDn0GTX0mHwwqebuxJ0M5yHycuBxla1Ij/IkSns436XbVHpzO/tD1qSFT1EUHe 4CniCwgSqdJZ0CKwNnAZkgNeHlPJB+6xd25ktJ7Vvy7JXcKmNNcr40d7lg0EZ5A6NGfy NQZvQlhC9fovzdDqD3EX3T5sNa8zTpjMrk0D6+U5qG6Lg+udHIGNWB/ivzDpiXyhSKDe J9CbxKf5VTnGv5t7BqhkNjuKRxRsOv4V2LsTzbxIP3WbMQ7zyTvJul5RCDZv/8I6DSM2 jqL0PNoGLClUDQJrvPWR881YN4xR42oyfp3lH7PlBdJCC6F4P/Hedz0ErRhoDEI216Rc S4Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=xaVDHa8AFB8v3COJEYS3fRBLkeMElk+V+0HFYylESpV+sMQbUM/bBrVjeE66wI9Z5s 60bnHhxjol9HnnzUFdxyXBHQi9fTWNeYPJxhFPAtNcr02X0+B0UpZYRl1aRVNYtUPzLt VOQiaeJFisMy4tPVxNe9AiAJqcmMfOdbN4qMTm+ty6P1CgsvMZi4VmCQfvRGLk3XkIzz onVh2/UsIvfZuf0rf9Qv7fK2+o+GWATxLmW9aK2LnaLhw8SVV2fV5Ev2Da27eHzbY7pT J3J5fXM05CSZh5CoZdNb1/ra7e23YVCq6lV6LQ26xIYBFGdE1B7mtwG8ncYS1BwkcAGk akiQ== X-Gm-Message-State: AOAM531nMYuiyxC34zGUDQt4uf0zYjshQLyuK3r8I4T3FzsSk7WqOQoZ 92hHniPj1S4TByi4wcwkH4I= X-Google-Smtp-Source: ABdhPJwf6q/ji2LpZQxcWUGLZjMQmKqUcqRq5So17hNmqC9FvBC10Z2s+FJKuosbJSHGxSJyW/0DUA== X-Received: by 2002:a05:600c:1d9f:b0:389:a1c4:f400 with SMTP id p31-20020a05600c1d9f00b00389a1c4f400mr27615563wms.171.1647878896550; Mon, 21 Mar 2022 09:08:16 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:16 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 01/18] clk: introduce clk_hw_get_index_of_parent new API Date: Mon, 21 Mar 2022 16:38:38 +0100 Message-Id: <20220321153855.12082-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Clk can have multiple parents. Some clk may require to get the cached index of other parent that are not current associated with the clk. We have clk_hw_get_parent_index() that returns the index of the current parent but we can't get the index of other parents of the provided clk. Introduce clk_hw_get_index_of_parent() to get the cached index of the parent of the provided clk. This permits a direct access of the internal clk_fetch_parent_index(). Signed-off-by: Ansuel Smith --- drivers/clk/clk.c | 14 ++++++++++++++ include/linux/clk-provider.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8de6a22498e7..bdd70a88394c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1726,6 +1726,20 @@ int clk_hw_get_parent_index(struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_get_parent_index); +/** + * clk_hw_get_index_of_parent - return the index of the parent clock + * @hw: clk_hw associated with the clk being consumed + * @parent: clk_hw of the parent to be fetched the index of + * + * Fetches and returns the index of parent clock provided. + * Returns -EINVAL if the given parent index can't be provided. + */ +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent) +{ + return clk_fetch_parent_index(hw->core, parent->core); +} +EXPORT_SYMBOL_GPL(clk_hw_get_index_of_parent); + /* * Update the orphan status of @core and all its children. */ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2faa6f7aa8a8..5708c0b3ef1c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1198,6 +1198,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent); int clk_hw_get_parent_index(struct clk_hw *hw); int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); From patchwork Mon Mar 21 15:38:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B084C4167B for ; Mon, 21 Mar 2022 16:08:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350666AbiCUQJq (ORCPT ); Mon, 21 Mar 2022 12:09:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350654AbiCUQJo (ORCPT ); Mon, 21 Mar 2022 12:09:44 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F0BE26127; Mon, 21 Mar 2022 09:08:19 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id l7-20020a05600c1d0700b0038c99618859so1561175wms.2; Mon, 21 Mar 2022 09:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=PRxcN0YNqKTcaPjS0fn0z0+BAh24QLYfgc7tCFaUIUeirq+WgcTYaaPR5xBOBrQ37O mZEf5NhpLWOAeOMNXZaAtup6p8iYbmcFAx7+nDcFlzHAOlkbAdbQwvnhidkreZvJSF41 l3a1SRIp6XOKo+FKzOs0UvjcM45dYZHiRHBURWd9DjYWadg4VTqGfyhnGmZegRf8j72A CN1QTPm1JDR8DE659hbJLf42IeiDlmuLP2sBsh1zUqpaHiMRTnhAhyXGhzWBo7KniSJ4 kPappCdFCUyo95amfaAE5GcJSk5viWXQNqRWRctm+IBlLwI/AMaIc3Zvj6YjwIXOV7nS /LsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=IXuUWMx5sZV37mafhHN4xvO5M3Z0G1Dq07MejXSfPD5bOWfr1r5N26ogGMb+YtQW5H cakzyH4wpBwHLep106S92+SaqHJaNC+YhEJYOOu4KgYOhcQL7mQVeo8bL977o4mI9QHM HGModriV/zkfuoWGmgbyHHGluQ7r9wVF3RBa2oK63JoRWA2Wo3cuZpsQ/rhU5wfQMVNq QW2TY9aHgVkaaSibU7NsHtGQ82WHcWO7kXMlvxCnGPP2f2Wj90ZtdSoqzTKMKumxNTTs cgp0LRh7ofg6iyjyiZY+YjMJf2oQYDWXXjGC6uCn6sW0oEs4NEVZu4tpytzRuthX4lZ3 uhGA== X-Gm-Message-State: AOAM531XKMSVwKydXvY4j7T93ZH6wnCVKv0CyT93inybgeg4Zk5NTMdG sGlB9xgXlMqKLv7MiAtyC7w= X-Google-Smtp-Source: ABdhPJzmmXYtPahfLRvOnqB6/yj41g20w5qnbJ6O5r6QRbfydnecXu5FG6FeZnUGX9jQvmC42c/tAA== X-Received: by 2002:a05:600c:4f47:b0:381:6c3e:19dc with SMTP id m7-20020a05600c4f4700b003816c3e19dcmr19786922wmq.155.1647878897647; Mon, 21 Mar 2022 09:08:17 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:17 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 02/18] clk: qcom: gcc-ipq806x: skip pxo/cxo fixed clk if already present Date: Mon, 21 Mar 2022 16:38:39 +0100 Message-Id: <20220321153855.12082-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Skip pxo/cxo clock registration if they are already defined in DTS as fixed clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..27f6d7626abb 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -3061,15 +3062,22 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct regmap *regmap; + struct clk *clk; int ret; - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "cxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); + if (ret) + return ret; + } - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "pxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); + if (ret) + return ret; + } ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) From patchwork Mon Mar 21 15:38:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32C74C433FE for ; Mon, 21 Mar 2022 16:08:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350677AbiCUQJr (ORCPT ); Mon, 21 Mar 2022 12:09:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350669AbiCUQJq (ORCPT ); Mon, 21 Mar 2022 12:09:46 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B70624F2D; Mon, 21 Mar 2022 09:08:20 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id o7-20020a05600c4fc700b0038c87edc21eso229851wmq.0; Mon, 21 Mar 2022 09:08:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=TAwE5HW6hYVyPsz24A2O6MJaAg5DkdubLsxsGaW8MPzHT9izKqCVZtk9NE3ufH3Lrm v/zum8mDWlnL/t2LGk5gZp93yBImDtOs2d+OAz6lHeVUT0vjWJzLOQFnrhuSTST1Tl5m JRlyBrjTyyTqF6J68S7fDjwr8frjwd9pmRx/7kThZ6OOKqzqlh4WZdxzHVcZVhdwvfbz mQzE83JtQPGl5qMr3+P7pQywrM6gLobO91tnR7eLbHySbXzkpj3uBdHX0Art9ZGF5eSb kXBuef1YP8QEXm2ATeWz+J4VFk8nftiSZ+ba1/50v0lKAUlKwAhp08tgV2nr5ctrjpZ+ xmeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=QMbhqbjRQ915tAkRpAWXvM+Qy3TnXcZ9xJHwkWH/MNRjgv8AQ23OtKI13bj6HiqPsN t8fYQNjsupZ6fybV4DdH9oVBHDLd0yC8tUEtRyw8FrFUBNSPs0cnKrA00h8qsoWkw1g/ pdPippii+DzBVGIfkGK3qy2xfx0ueyBkE2VuAEO7KqLz0EKPntRBmmiRUpcaC6YWMwmK uR56f+e4oTBSzMtYkHPwNBCkUp8fL2rhCewW7Jp0E1YNWZpdzwIp9i76ZoHbdcLOzDyM dh1jI8t1XwMFJq16Beo57DAmboD4flLrsUt+1YtW4D3tkVOoPydYKZO+/CjUxMdZXZUb mVcA== X-Gm-Message-State: AOAM531m138QERqcQTdZEshnZzDqxMyMEjr5xfdNl5Qn1JqAdc3b6Krn pjEvbRqBfs5yAqZpeUw32c0i1KKv2og= X-Google-Smtp-Source: ABdhPJyYkhegl30L+1lL5DkDI/Rh7twroqIbQpDVFtxsOnOOKPlDn9cLg3jSKRvxWcGWP+TaBsstFA== X-Received: by 2002:a1c:f30b:0:b0:37b:b5de:c804 with SMTP id q11-20020a1cf30b000000b0037bb5dec804mr27432722wmq.166.1647878898645; Mon, 21 Mar 2022 09:08:18 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:18 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 03/18] clk: qcom: gcc-ipq806x: add PXO_SRC in clk table Date: Mon, 21 Mar 2022 16:38:40 +0100 Message-Id: <20220321153855.12082-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PXO_SRC is currently defined in the gcc include and referenced in the ipq8064 DTSI. Correctly provide a clk after gcc probe to fix kernel panic if a driver starts to actually use it. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 27f6d7626abb..7271d3afdc89 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -26,6 +26,8 @@ #include "clk-hfpll.h" #include "reset.h" +static struct clk_regmap pxo = { }; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -2754,6 +2756,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }; static struct clk_regmap *gcc_ipq806x_clks[] = { + [PXO_SRC] = NULL, [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, [PLL3] = &pll3.clkr, @@ -3083,6 +3086,10 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) if (ret) return ret; + clk = clk_get(dev, "pxo"); + pxo.hw = *__clk_get_hw(clk); + gcc_ipq806x_clks[PXO_SRC] = &pxo; + regmap = dev_get_regmap(dev, NULL); if (!regmap) return -ENODEV; From patchwork Mon Mar 21 15:38:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BE7DC4332F for ; Mon, 21 Mar 2022 16:08:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350702AbiCUQJv (ORCPT ); Mon, 21 Mar 2022 12:09:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350670AbiCUQJq (ORCPT ); Mon, 21 Mar 2022 12:09:46 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39ADD26545; Mon, 21 Mar 2022 09:08:21 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id j13-20020a05600c1c0d00b0038c8f94aac2so4410128wms.3; Mon, 21 Mar 2022 09:08:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=eMAAW4T4i4c8oUssXYgx110V91CsAvVQIGvLX9z3GI4RjCZxiOD8oqh7MCh/KNudSP piLBrwD9JIdDhfg2mXpo1bxKazBL6l+RlaK/YMcMyiEgKMtLzJ4nWi0F1v9+UiB9t5Ux kgjz6xybMBM3Sfi91CzFYpD0aewMPoKPFfhq0PgyU+/GpNJNyiqhleXpCBgxRa5Z7B+D 3jDfre4Feyr0Fx7KzUW3Rcwc4WctWEVCb9iPZmJRfCQG/j0Cb8sMEc2T2otMC0a0Iuor A7Yc5al4ZvQeBQhe+RbqY5BuiZdHCQ20dTiHEgfEQ6gW1NMhFsB3xK9UcQ8v1G6bJgXd aZzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=Tanwq7c6wwXTA0aXLqm8K7vyvGbvnVBntd0Jb1D/ISzw/BGLMF6jvQzSZSsm6LDzs7 +O8g8M1/tzoYfdiwgxc1dGEOJubBgXiYN+nYsRC38KBY8YrjfDWKz4wwTN5UkglLZVT6 QU0H9bz9dfgHYgY9GYbeSbVypJOrrnZl70n2lW6+H/vvGQ9GW+eSpEA3u4i5iETs+pmM dehRRhUbRhX53pobVk+mlzSJcS058Y1S3WRGkD5h1+xuBNa9XxnHQ2pZYwsEHsHWq/Tw 7Y5c2RxzWBBR/TKLt2foASPUHf1sd3f9IXuDrb28F/AYRPLntoTW2ap+2IYh3lHwPWZO 5RmQ== X-Gm-Message-State: AOAM531ylOu7GCVQxQW//W8tHKNrGE28ZluyTb2TzQ3upyJ1HMgQBBZC m+zv8IcRvwigDOZP8J0xCtt5CDJclAo= X-Google-Smtp-Source: ABdhPJxs9iuvoQvrH/GpiNtxgRTLeoY4ZANQsUUXCIClS/8QRGTs+yHtpGU28ZIKTAHfyBFfnDbcbA== X-Received: by 2002:a05:600c:3d0e:b0:38c:9b5e:52c0 with SMTP id bh14-20020a05600c3d0e00b0038c9b5e52c0mr8366210wmb.3.1647878899660; Mon, 21 Mar 2022 09:08:19 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:19 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 04/18] clk: qcom: clk-hfpll: use poll_timeout macro Date: Mon, 21 Mar 2022 16:38:41 +0100 Message-Id: <20220321153855.12082-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use regmap_read_poll_timeout macro instead of do-while structure. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-hfpll.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index e847d586a73a..a4e347eb4d4d 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -12,6 +12,8 @@ #include "clk-regmap.h" #include "clk-hfpll.h" +#define HFPLL_BUSY_WAIT_TIMEOUT 100 + #define PLL_OUTCTRL BIT(0) #define PLL_BYPASSNL BIT(1) #define PLL_RESET_N BIT(2) @@ -72,13 +74,12 @@ static void __clk_hfpll_enable(struct clk_hw *hw) regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); /* Wait for PLL to lock. */ - if (hd->status_reg) { - do { - regmap_read(regmap, hd->status_reg, &val); - } while (!(val & BIT(hd->lock_bit))); - } else { + if (hd->status_reg) + regmap_read_poll_timeout(regmap, hd->status_reg, val, + !(val & BIT(hd->lock_bit)), USEC_PER_MSEC * 2, + HFPLL_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); + else udelay(60); - } /* Enable PLL output. */ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); From patchwork Mon Mar 21 15:38:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22CECC43219 for ; Mon, 21 Mar 2022 16:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350711AbiCUQJw (ORCPT ); Mon, 21 Mar 2022 12:09:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350680AbiCUQJs (ORCPT ); Mon, 21 Mar 2022 12:09:48 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C96F26AFD; Mon, 21 Mar 2022 09:08:22 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id l1-20020a05600c4f0100b00389645443d2so8666761wmq.2; Mon, 21 Mar 2022 09:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=qtxn9wGOGQrzvmBXl6/3MZDDb0difxVX7vVZ1tfjO1Xvx9+DiIQw+uSwfNncvh7mmt X3dgcEICqi2t91JsYM4J8PcxZbgKckgH8cUv+IxkPl4KP7N9AxvfA0AjwtevXioiK40Z VVB9hNUoH/6VhyW1Oo5xlrx5zZGSUrHazhdwYdEOEALO0R+GFBwArY45UYIuF6IB9/H6 2j3zyd3MtshgasETkPDP9NepbRQoVvjnivRnyMCcvvHH+LH1xSutOvhzJ4Fy/YlooBs7 2AxsW4NB4xctChB7W58cohStzLUzGyJpA83tX3ajivfvn8yBFhQ06LX48kbiG0o8vUCd 3vLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=MAjr8lFnyQod2h/inbE+VFP3yxmvL/yA6pRKl0tKYn0/ktzlqViGUZpPbBjXXP6Drx 4ATj4z4HGTA1WpcEaFbP217MowJVh1zMDo43ILP4Hl0jY10EefKRRuGHVivgGllNwXLs fZxV8YCatgNPpTXoXez8n/NkfBAxD1hQDkeQFrBaes3wosoqvuo+r/ySNFWt845A7cuO owNifhdnu/+Y+yfHQIDFeIixuu/J3wjzh67vbr66odzJDJPRmTdUcRrYtr26jFohLyeH TmrmveH+A3/gId2KLrSL2lG9a613gacwkr9b35sD4scUmAnZVcaBu+DRaKyYjrzeldAV F9uw== X-Gm-Message-State: AOAM532SD6hFm+bUp39RDJOVxk6fuNpvyPqCwkxZcu3BfLDwAB9Z60Zq ZDLY+3JDJl6uowO2WKBHqh4= X-Google-Smtp-Source: ABdhPJwMdwK+Xc3LVIdaevR72KFlksW5UfZWSO57kyHVMquIlBBbrK6LFXKqJTnZAPedDVWtjmkiNA== X-Received: by 2002:a05:600c:4e53:b0:38c:987e:cdc with SMTP id e19-20020a05600c4e5300b0038c987e0cdcmr9845192wmq.154.1647878900699; Mon, 21 Mar 2022 09:08:20 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:20 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 05/18] clk: qcom: kpss-xcc: convert to parent data API Date: Mon, 21 Mar 2022 16:38:42 +0100 Message-Id: <20220321153855.12082-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. Name is still used to save regression on old definition. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/kpss-xcc.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c index 4fec1f9142b8..347f70e9f5fe 100644 --- a/drivers/clk/qcom/kpss-xcc.c +++ b/drivers/clk/qcom/kpss-xcc.c @@ -12,9 +12,9 @@ #include #include -static const char *aux_parents[] = { - "pll8_vote", - "pxo", +static const struct clk_parent_data aux_parents[] = { + { .name = "pll8_vote", .fw_name = "pll8_vote" }, + { .name = "pxo", .fw_name = "pxo" }, }; static unsigned int aux_parent_map[] = { @@ -32,8 +32,8 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); static int kpss_xcc_driver_probe(struct platform_device *pdev) { const struct of_device_id *id; - struct clk *clk; void __iomem *base; + struct clk_hw *hw; const char *name; id = of_match_device(kpss_xcc_match_table, &pdev->dev); @@ -55,24 +55,15 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev) base += 0x28; } - clk = clk_register_mux_table(&pdev->dev, name, aux_parents, - ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, - 0, aux_parent_map, NULL); + hw = __devm_clk_hw_register_mux(&pdev->dev, NULL, name, ARRAY_SIZE(aux_parents), + NULL, NULL, aux_parents, 0, base, 0, 0x3, + 0, aux_parent_map, NULL); - platform_set_drvdata(pdev, clk); - - return PTR_ERR_OR_ZERO(clk); -} - -static int kpss_xcc_driver_remove(struct platform_device *pdev) -{ - clk_unregister_mux(platform_get_drvdata(pdev)); - return 0; + return PTR_ERR_OR_ZERO(hw); } static struct platform_driver kpss_xcc_driver = { .probe = kpss_xcc_driver_probe, - .remove = kpss_xcc_driver_remove, .driver = { .name = "kpss-xcc", .of_match_table = kpss_xcc_match_table, From patchwork Mon Mar 21 15:38:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AA9FC43217 for ; Mon, 21 Mar 2022 16:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350720AbiCUQJx (ORCPT ); Mon, 21 Mar 2022 12:09:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350690AbiCUQJu (ORCPT ); Mon, 21 Mar 2022 12:09:50 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC6E2286F7; Mon, 21 Mar 2022 09:08:23 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id t11so21391391wrm.5; Mon, 21 Mar 2022 09:08:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=VTFoGgHy46VG05v3mlZ7Rbg1Ij/iZQAYDOclaiGTVO2GXpFbGJ0w5UMnLQ54FQfBny 7HLTl8eUQ1oObSKvzrkutp15cFbKTLWcUm6L8V3lPHpfp3UpHIlpXQfBePq4bJZt8TLb l2z9UMU4J3DG0X8xiM4gtbVvrIybZOS/jI25v3YW1EmjO0f9+fFiqFD0omrf8ZXVpj4W Blo7usEyvfuFXtp+nAsAyM5jPL0AR4ylK7J/olkQJSyV4DFcnZBXj45JVeANKFKfvMyy 96HtDzA7RnTiDC24+INRc7Uy+UEVMy57GPnxWpUMC4ZEwyy3XcHNITGZCqlVk/pPJb/1 B5zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=wrL3rw871CQGu9HlIYDb+9CucuY+XGGOJ6pDr0XNNejJJV4orTHuQljXVyph3jWuyl 9YaRl2M6Z0nwT4s13NH8MPln4Q11gOwflWAjw4OqgQUlaCDGcCZfZSubnUeTkV7iBEM7 ZCkIWbxxy/i/xsQrm3FAs/tg7IlEbFE4gdA3EC7rlSQlalKMgtlaDJKDnPU/9orCXlyY WzjQ01wk16oBJtCayXC4g5by6EpSEjq1vcz8px2QE1je5OFD0hEWP8C1Cwa0iva0ooV3 ceyA8en2QZ2rjiEewfnvRb/FAYgJAzxm3Pjw/U8R5pGRgw31AOa4V4qxgg+K6YTcJBXn B0UQ== X-Gm-Message-State: AOAM532gNALKQPS2Oi4CRAxiAeNoFv0X4bogWWHEKnWXL8jvxaXc0GIm qslGcnfTNK+br0VkvI9KOvs= X-Google-Smtp-Source: ABdhPJxQl95223QIhrmEBBoQM5AbNKYcBBiv7qPwdMS5iIhOtA/y5V32KHAWTkxw8GRm9Agd55dtUw== X-Received: by 2002:a5d:59a5:0:b0:203:d46b:f27a with SMTP id p5-20020a5d59a5000000b00203d46bf27amr19357992wrr.126.1647878901726; Mon, 21 Mar 2022 09:08:21 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:21 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 06/18] clk: qcom: clk-krait: unlock spin after mux completion Date: Mon, 21 Mar 2022 16:38:43 +0100 Message-Id: <20220321153855.12082-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Unlock spinlock after the mux switch is completed to prevent any corner case of mux request while the switch still needs to be done. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 59f1af415b58..e447fcc3806d 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -32,11 +32,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); } krait_set_l2_indirect_reg(mux->offset, regval); - spin_unlock_irqrestore(&krait_clock_reg_lock, flags); /* Wait for switch to complete. */ mb(); udelay(1); + + spin_unlock_irqrestore(&krait_clock_reg_lock, flags); } static int krait_mux_set_parent(struct clk_hw *hw, u8 index) From patchwork Mon Mar 21 15:38:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA400C35278 for ; Mon, 21 Mar 2022 16:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350678AbiCUQJz (ORCPT ); Mon, 21 Mar 2022 12:09:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350696AbiCUQJv (ORCPT ); Mon, 21 Mar 2022 12:09:51 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53E06289A4; Mon, 21 Mar 2022 09:08:24 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id d7so21372249wrb.7; Mon, 21 Mar 2022 09:08:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uKLqUE0HqMblkYxTDEoLkraH8fYkNKsZ80vlgdu8msQ=; b=pPQBa78YGPtspBAIwSYLH3sOjVqFmTH2f8C0gFoZvX/PVsvFeGhgYea1CT/qyovtU1 86NC6amFLmb3bZB2iUc0YiXtQXIONJEjCxizGOx8emPmgk+ej1/ZG+gtrDH+wg3PEKeQ QBe8sWtR91uETw08N1DmXx+4xF6r68ShR02w8vYCN4jgh1eHphPwRKssaCHgw3dYf7zB PZYTyIn3IxQf7MLkZndv1VrVNwNTdscSdUfxjUpAWOizc5zqXYrZ30maoi9hA9at7fiH Sxoa0oTzVA1EO0nTfFjYRPrXoCC0YektC93Zt287WVP2GYWTw3fdDkTnwyILo8git/nD 070w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uKLqUE0HqMblkYxTDEoLkraH8fYkNKsZ80vlgdu8msQ=; b=BSWRXLH3XUoNDzTPyzvezRL1YSa8gIeEGfAC/8C5NGf6eWDNBqjSwUzRkqlWZmh0be 8ZcwAnBcrV8hQb0A92zuLtS+zCBxMZoMAtI+u+SYVJwsMDAwoS+KeOB9IVJf7yJdyqME FTkajy85dWFXSwtDViWbta7N2zIz3UUKpIcNe+gWvCLs0pTE67w7TzP1PHnKIkLCqarX Jw4gYQXXsXmXRrMPhj4Jv+bwCUfSWowA/CwmW36qlbN2nN8DQRL2P1eWLPcMJYIiTFWt 2dS3jfgkcP69NCAnhFMFBwcH9gqn3BjMXsoi0/ds7iEfrHtg/+9ngeyWJ9fyT/az0mim 3ylQ== X-Gm-Message-State: AOAM531ev1Vxq5dnxmbQthohC2fszJblFPWd7Bn/N/FG0cNXyj9JWG// V8Wc8tT1JsNWcJJngNOIhHU= X-Google-Smtp-Source: ABdhPJytAlmKqsU78d+ZiKESAIbMPYYAdAO5Iu5OxAzit5428s8wkU1OO7zQxDkB/ofhfxfZ+oyAOA== X-Received: by 2002:adf:d4c2:0:b0:203:da50:12c5 with SMTP id w2-20020adfd4c2000000b00203da5012c5mr19321170wrk.100.1647878902712; Mon, 21 Mar 2022 09:08:22 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:22 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 07/18] clk: qcom: clk-krait: add hw_parent check for div2_round_rate Date: Mon, 21 Mar 2022 16:38:44 +0100 Message-Id: <20220321153855.12082-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Check if hw_parent is present before calculating the round_rate to prevent kernel panic. On error -EINVAL is reported. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index e447fcc3806d..b6b7650dbf15 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -80,7 +80,12 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops); static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); + struct clk_hw *hw_parent = clk_hw_get_parent(hw); + + if (!hw_parent) + return -EINVAL; + + *parent_rate = clk_hw_round_rate(hw_parent, rate * 2); return DIV_ROUND_UP(*parent_rate, 2); } From patchwork Mon Mar 21 15:38:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 017C8C433EF for ; Mon, 21 Mar 2022 16:08:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350739AbiCUQJ5 (ORCPT ); Mon, 21 Mar 2022 12:09:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350699AbiCUQJv (ORCPT ); Mon, 21 Mar 2022 12:09:51 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AA7A28E1B; Mon, 21 Mar 2022 09:08:25 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id h189so88173wmh.3; Mon, 21 Mar 2022 09:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=SfJl/86cPzI9BaAZjLQH92XV0QTa7gDPuhbb5TKYkBAPkXhgYHgg/SkSZv1fN8VAZp Rz/ktPfjE6lBQh7PbOblW2I++fpm7FDMhphs7/6SjkSAOCmnoQ+HKvYmjylJkGz5Ohau 8JWnmCfHYKL38JXs/VhJZpPs7m13CvKphbkCQ6pdsSYEKjhFTudHwuAA6n54Y0arDY/P /fjf7eNbn1fNvr3mKRmVzMQEJMG0EuIl5qLx2G2daLd4uoUcN18CxF0Ajos5BrtsopqS w/mxh8oRe1lDZ3+K++anmVtC5X4ECq4vLq+MB94MNGPgi/N0yCkwzb8iiUJAR/MJCNGK Z2Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=UZ9MwKPqWDZCFaY8YDfHwOCdl6WyPNCXbFMg4e3HABpqrZX2UGckSFrG7HC1SfWtYw oLVPFu+1/AGr4bzDfyVU/hJgz3Mc2jXF9V+t//0pn/YDHbLTFT5XBgQd6hMXiBIrhjJ4 3R3Ay72AUTJ98ZeRLXvlEtgudXZ/+S4cxrygHVCQcuoT2jL6Yq3CrQneQY0p0Vvmcpzi nHvZFWBziOD22WGOGg4GGIhsLnO3yvh4r1l0FWzTlSa5icRvSNZiub4Irqnm20vlFxnv KLZ8MMUajiiznNQ7aTzqZXrQ0h1bTAso9bC1Q/zXafDp8K4kkVRdnEv20Y4MITL/xpEI 2O2Q== X-Gm-Message-State: AOAM533MXcEr0FMUYBjQPEHfSqjKuQBN3ufDN6HQ7IR2zJmhVnJ1+lza r/O8uMKRTvjHYpC5QAdsvq5PBG7FonI= X-Google-Smtp-Source: ABdhPJz4UYKT8iwzmtMpkQ+eSWmqC2tIqo5+yQvBGG8VilUzWnk/ilfjk4DBImJ0XiK9YJuRxKvqtQ== X-Received: by 2002:a05:600c:3ac7:b0:38b:f9c6:27b8 with SMTP id d7-20020a05600c3ac700b0038bf9c627b8mr19741082wms.75.1647878903706; Mon, 21 Mar 2022 09:08:23 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:23 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 08/18] clk: qcom: krait-cc: convert to parent_data API Date: Mon, 21 Mar 2022 16:38:45 +0100 Message-Id: <20220321153855.12082-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Modernize the krait-cc driver to parent-data API and refactor to drop any use of clk_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. Name is also declared to save compatibility with old implementation. Also fix the parent order of the sec_mux that was wrong and incorrectly report the wrong safe parent if it's not hardcoded. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 126 +++++++++++++++++++----------------- 1 file changed, 66 insertions(+), 60 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 4d4b657d33c3..645ad9e8dd73 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -69,21 +69,22 @@ static int krait_notifier_register(struct device *dev, struct clk *clk, return ret; } -static int +static struct clk * krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) { struct krait_div2_clk *div; + static struct clk_parent_data p_data[1]; struct clk_init_data init = { - .num_parents = 1, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_div2_clk_ops, .flags = CLK_SET_RATE_PARENT, }; - const char *p_names[1]; struct clk *clk; + char *parent_name; div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) - return -ENOMEM; + return ERR_PTR(-ENOMEM); div->width = 2; div->shift = 6; @@ -93,43 +94,49 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - init.parent_names = p_names; - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { - kfree(init.name); - return -ENOMEM; + init.parent_data = p_data; + parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!parent_name) { + clk = ERR_PTR(-ENOMEM); + goto err_parent_name; } + p_data[0].fw_name = parent_name; + p_data[0].name = parent_name; + clk = devm_clk_register(dev, &div->hw); - kfree(p_names[0]); + + kfree(parent_name); +err_parent_name: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } -static int +static struct clk * krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { - "acpu_aux", - "qsb", + static struct clk_parent_data sec_mux_list[2] = { + { .name = "qsb", .fw_name = "qsb" }, + {}, }; struct clk_init_data init = { - .parent_names = sec_mux_list, + .parent_data = sec_mux_list, .num_parents = ARRAY_SIZE(sec_mux_list), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *parent_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) - return -ENOMEM; + return ERR_PTR(-ENOMEM); mux->offset = offset; mux->lpl = id >= 0; @@ -141,44 +148,51 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); if (unique_aux) { - sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); - if (!sec_mux_list[0]) { + parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); + if (!parent_name) { clk = ERR_PTR(-ENOMEM); goto err_aux; } + sec_mux_list[1].fw_name = parent_name; + sec_mux_list[1].name = parent_name; + } else { + sec_mux_list[1].name = "apu_aux"; } clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto unique_aux; + clk = ERR_PTR(ret); -unique_aux: +err_clk: if (unique_aux) - kfree(sec_mux_list[0]); + kfree(parent_name); err_aux: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } static struct clk * -krait_add_pri_mux(struct device *dev, int id, const char *s, - unsigned int offset) +krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux, + int id, const char *s, unsigned int offset) { int ret; struct krait_mux_clk *mux; - const char *p_names[3]; + static struct clk_parent_data p_data[3]; struct clk_init_data init = { - .parent_names = p_names, - .num_parents = ARRAY_SIZE(p_names), + .parent_data = p_data, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *hfpll_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) @@ -196,36 +210,29 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, if (!init.name) return ERR_PTR(-ENOMEM); - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { + hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!hfpll_name) { clk = ERR_PTR(-ENOMEM); - goto err_p0; + goto err_hfpll; } - p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!p_names[1]) { - clk = ERR_PTR(-ENOMEM); - goto err_p1; - } + p_data[0].fw_name = hfpll_name; + p_data[0].name = hfpll_name; - p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!p_names[2]) { - clk = ERR_PTR(-ENOMEM); - goto err_p2; - } + p_data[1].hw = __clk_get_hw(hfpll_div); + p_data[2].hw = __clk_get_hw(sec_mux); clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto err_p3; -err_p3: - kfree(p_names[2]); -err_p2: - kfree(p_names[1]); -err_p1: - kfree(p_names[0]); -err_p0: + clk = ERR_PTR(ret); + +err_clk: + kfree(hfpll_name); +err_hfpll: kfree(init.name); return clk; } @@ -233,11 +240,10 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, /* id < 0 for L2, otherwise id == physical CPU number */ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) { - int ret; unsigned int offset; void *p = NULL; const char *s; - struct clk *clk; + struct clk *hfpll_div, *sec_mux, *clk; if (id >= 0) { offset = 0x4501 + (0x1000 * id); @@ -249,19 +255,19 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) s = "_l2"; } - ret = krait_add_div(dev, id, s, offset); - if (ret) { - clk = ERR_PTR(ret); + hfpll_div = krait_add_div(dev, id, s, offset); + if (IS_ERR(hfpll_div)) { + clk = hfpll_div; goto err; } - ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); - if (ret) { - clk = ERR_PTR(ret); + sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + if (IS_ERR(sec_mux)) { + clk = sec_mux; goto err; } - clk = krait_add_pri_mux(dev, id, s, offset); + clk = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); err: kfree(p); return clk; From patchwork Mon Mar 21 15:38:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BD70C433EF for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:24 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 09/18] clk: qcom: krait-cc: drop pr_info and register qsb only if needed Date: Mon, 21 Mar 2022 16:38:46 +0100 Message-Id: <20220321153855.12082-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace pr_info() with dev_info() to provide better diagnostics. Register qsb fixed clk only if it's not declared in DTS. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 645ad9e8dd73..e9508e3104ea 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -308,7 +308,9 @@ static int krait_cc_probe(struct platform_device *pdev) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk_get(dev, "qsb"))) + clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk)) return PTR_ERR(clk); @@ -363,25 +365,25 @@ static int krait_cc_probe(struct platform_device *pdev) cur_rate = clk_get_rate(l2_pri_mux_clk); aux_rate = 384000000; if (cur_rate == 1) { - pr_info("L2 @ QSB rate. Forcing new rate.\n"); + dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate = aux_rate; } clk_set_rate(l2_pri_mux_clk, aux_rate); clk_set_rate(l2_pri_mux_clk, 2); clk_set_rate(l2_pri_mux_clk, cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); + dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); for_each_possible_cpu(cpu) { clk = clks[cpu]; cur_rate = clk_get_rate(clk); if (cur_rate == 1) { - pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); + dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate = aux_rate; } clk_set_rate(clk, aux_rate); clk_set_rate(clk, 2); clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); + dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); } of_clk_add_provider(dev->of_node, krait_of_get, clks); From patchwork Mon Mar 21 15:38:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9CBBC43217 for ; Mon, 21 Mar 2022 16:08:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350695AbiCUQKH (ORCPT ); Mon, 21 Mar 2022 12:10:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350719AbiCUQJx (ORCPT ); Mon, 21 Mar 2022 12:09:53 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD830286F7; Mon, 21 Mar 2022 09:08:27 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id j13-20020a05600c1c0d00b0038c8f94aac2so4410338wms.3; Mon, 21 Mar 2022 09:08:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HxwJ/rmGXQIKgHQmjTVr7v/2TGpe+xuVVbkVjt0eYLU=; b=Uulaq8+I7KFpLzJsuS1QMflEMpO/JE3uFRWkkEyqZCy7wJYwBuB2/vcHm3HNUKVVGg n8p9rRZU389RHDdPj9rrnWPX3obt2G/GNoE+IjgHKknWEGvdTR5sUZvJWZM84wiRKZhF u9HwH1RSV469J6Ej838Ar8vYlRY/d3L3Q6I/CpnlKp6oitQE+Xt9wdXSJLXbopSQ3/uC kGwETvGH/uQWlZVUKXYNGNkvpGkviYOzvu4VZMAipGfF+Lg+fhx+nw/UsZDddt7BAslB k9QpDSmSHRpdnJpNcVfbmMueKZJCYIYO7Vrk6+OBll7wqcfTVFJHqAvHxVBAtwoF8I30 iGdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HxwJ/rmGXQIKgHQmjTVr7v/2TGpe+xuVVbkVjt0eYLU=; b=N7qNcSucxsQb+qkvRrjvQqP4djjZbS9VlDiwU6+sPF7mmr3GFrhqK608YLIR1y7BrQ FtXa8yf8lPrNltfZ3UV4+lss/GD8DEn0V25eNh6MduWhdTPER9cmlF1HTO0djq32lYeK KRafAw2bLCnBfG+JTXtJ+ee3BfKksqD7Wn/nZV82jxWt0+MSm+9kxKGmo1dxFC0gjUDu laAqpztZMKPbh8sg7qLKjOMBIFIal83beGVKhoZN3kVY3yqDtkYh+kqDw2GuINFGlt4K z/RquhlwSUIIBByiRJGe3V3Bf+nhOEpyocautjQ3mshLY639Yso5kJRl8kRTziRfjfom miuA== X-Gm-Message-State: AOAM533tgq6oav9wc3bkiKoyWWut6eq+tIcfBwHFuIqw1WJujaO3l92M /m5OSk11SZLTUtlqmy6jtiU= X-Google-Smtp-Source: ABdhPJwDsT7Y8FuRv51EWORB+hZD9lvAHmPvfkVeCvZ2Q56Q/9x7538/wbgJQLjqEqKX6dFI2sJahw== X-Received: by 2002:a05:600c:4f47:b0:381:6c3e:19dc with SMTP id m7-20020a05600c4f4700b003816c3e19dcmr19787431wmq.155.1647878906158; Mon, 21 Mar 2022 09:08:26 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:25 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 10/18] clk: qcom: krait-cc: drop hardcoded safe_sel Date: Mon, 21 Mar 2022 16:38:47 +0100 Message-Id: <20220321153855.12082-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop hardcoded safe_sel definition and use helper to correctly calculate it. We assume qsb clk is always present as it should be declared in DTS per Documentation and in the absence of that, it's declared as a fixed clk. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 40 +++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index e9508e3104ea..5f98ee1c3681 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -26,6 +26,17 @@ static unsigned int pri_mux_map[] = { 0, }; +static u8 krait_get_mux_sel(struct krait_mux_clk *mux, struct clk *safe_clk) +{ + struct clk_hw *safe_hw = __clk_get_hw(safe_clk); + + /* + * We can ignore errors from clk_hw_get_index_of_parent() + * as we create these parents in this driver. + */ + return clk_hw_get_index_of_parent(&mux->hw, safe_hw); +} + /* * Notifier function for switching the muxes to safe parent * while the hfpll is getting reprogrammed. @@ -116,8 +127,8 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) } static struct clk * -krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) +krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, + const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; @@ -144,7 +155,6 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; - mux->safe_sel = 0; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) @@ -166,6 +176,7 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, qsb); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -204,7 +215,6 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux mux->lpl = id >= 0; mux->parent_map = pri_mux_map; mux->hw.init = &init; - mux->safe_sel = 2; init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); if (!init.name) @@ -226,6 +236,7 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, sec_mux); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -238,7 +249,9 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux } /* id < 0 for L2, otherwise id == physical CPU number */ -static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) +static struct clk * +krait_add_clks(struct device *dev, struct clk *qsb, int id, + bool unique_aux) { unsigned int offset; void *p = NULL; @@ -261,7 +274,7 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) goto err; } - sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + sec_mux = krait_add_sec_mux(dev, qsb, id, s, offset, unique_aux); if (IS_ERR(sec_mux)) { clk = sec_mux; goto err; @@ -301,18 +314,19 @@ static int krait_cc_probe(struct platform_device *pdev) int cpu; struct clk *clk; struct clk **clks; - struct clk *l2_pri_mux_clk; + struct clk *l2_pri_mux_clk, *qsb; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - if (IS_ERR(clk_get(dev, "qsb"))) - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + qsb = clk_get(dev, "qsb"); + if (IS_ERR(qsb)) + qsb = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(qsb)) + return PTR_ERR(qsb); if (!id->data) { clk = clk_register_fixed_factor(dev, "acpu_aux", @@ -327,13 +341,13 @@ static int krait_cc_probe(struct platform_device *pdev) return -ENOMEM; for_each_possible_cpu(cpu) { - clk = krait_add_clks(dev, cpu, id->data); + clk = krait_add_clks(dev, qsb, cpu, id->data); if (IS_ERR(clk)) return PTR_ERR(clk); clks[cpu] = clk; } - l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); + l2_pri_mux_clk = krait_add_clks(dev, qsb, -1, id->data); if (IS_ERR(l2_pri_mux_clk)) return PTR_ERR(l2_pri_mux_clk); clks[4] = l2_pri_mux_clk; From patchwork Mon Mar 21 15:38:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7D8BC433F5 for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:26 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 11/18] clk: qcom: krait-cc: force sec_mux to QSB Date: Mon, 21 Mar 2022 16:38:48 +0100 Message-Id: <20220321153855.12082-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that we have converted every driver to parent_data, it was notice that the bootloader can't really leave the system in a strange state where l2 or the cpu0/1 can be sourced in a number of ways for example cpu1 sourcing out of qsb, l2 sourcing out of pxo. To correctly reset the mux and the HFPLL force the sec_mux to QSB. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 5f98ee1c3681..299eb4c81d96 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -15,6 +15,8 @@ #include "clk-krait.h" +#define QSB_RATE 1 + static unsigned int sec_mux_map[] = { 2, 0, @@ -181,6 +183,13 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, if (ret) clk = ERR_PTR(ret); + /* + * Force the sec_mux to be set to QSB rate. + * This is needed to correctly set the parents and + * to later reset mux and HFPLL to a known freq. + */ + clk_set_rate(clk, QSB_RATE); + err_clk: if (unique_aux) kfree(parent_name); @@ -378,7 +387,7 @@ static int krait_cc_probe(struct platform_device *pdev) */ cur_rate = clk_get_rate(l2_pri_mux_clk); aux_rate = 384000000; - if (cur_rate == 1) { + if (cur_rate == QSB_RATE) { dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate = aux_rate; } @@ -389,7 +398,7 @@ static int krait_cc_probe(struct platform_device *pdev) for_each_possible_cpu(cpu) { clk = clks[cpu]; cur_rate = clk_get_rate(clk); - if (cur_rate == 1) { + if (cur_rate == QSB_RATE) { dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate = aux_rate; } From patchwork Mon Mar 21 15:38:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE97AC433EF for ; Mon, 21 Mar 2022 16:08:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350753AbiCUQKD (ORCPT ); Mon, 21 Mar 2022 12:10:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350735AbiCUQJ4 (ORCPT ); Mon, 21 Mar 2022 12:09:56 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 315F92983C; Mon, 21 Mar 2022 09:08:29 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id d7so21372658wrb.7; Mon, 21 Mar 2022 09:08:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/RImxULSEIcXltj7eh82B63gODFmYdSpUPrpbmj5VVA=; b=D1EyxBoNy9rnwvliXwI3sDoqfwUV2eqJrguiEC4wDRzt+p1KxhQxnWErSwJ9ef1TFL xateIY4De7ZDOzmC/U/nBTMMrt3gW8cBGbmmXXJ+5K66yz63l1jgS/7RogvBE71/o8uJ R/WNTcinisWarPaQgEtZPaMGc4n8Cll6hFN05tNTTDm0oPU2ckNgldJClIeoCUOcYR6X h99XaPh65EA+yFb/rJ1TLNHJj4Sh5qdarey9Pq/mbGAArZJo73I6vyjT7xkIF1ZDMgum Z1IOcSJ7/zzd6wUCUX/EbH/i+zx44Fiv5WwzOI2q/M2R+t+yNm8YKTzrpv8GRNchAdka jeRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/RImxULSEIcXltj7eh82B63gODFmYdSpUPrpbmj5VVA=; b=0C9dmepM0Jh+tvMyVrFOyy2abNUjiR8+8QvsrPnY7GdLdUZhRlmjOWr3YcRfhZArBc TnAd8ta153NugOkfU3slJ4gX4tsLSzIZW2cxmpReIlFeaAH89eHsVF9zG1dd17rJAc+O juocOXS1nn28YxQq6D958aJI1A+g/V8bawQ/wVsRC63c36wM9jd/kDh+3M02Smz+QJB2 lZFycwWb22mtm/Yn373Hh4GWSMsC94704R8OPXFapbp0V4RVrH/UVJX+ilnrsx+ygHuN OjPsVccaX+33/n9NNsp9uJVesgaqXCv3SL258sPNgM1GpI9q0roN2RNp7zK14RZj0+/2 kbcA== X-Gm-Message-State: AOAM533Uvia/cDQsF+iGVBIyMfvaSjfTvhqQgFRBIQYDW1kHVYzMFPUT vj97+/nnexjdYW01vVi+Ovw= X-Google-Smtp-Source: ABdhPJzwGoe3r1UPqUrHoV9XO70tVxS7iM9rErpYXORaXUrC54pyWi6i9EdZQoe2vHnDte6zn3dFAA== X-Received: by 2002:adf:eb48:0:b0:203:f854:86cc with SMTP id u8-20020adfeb48000000b00203f85486ccmr12661949wrn.102.1647878908236; Mon, 21 Mar 2022 09:08:28 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:27 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 12/18] clk: qcom: clk-krait: add apq/ipq8064 errata workaround Date: Mon, 21 Mar 2022 16:38:49 +0100 Message-Id: <20220321153855.12082-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add apq/ipq8064 errata workaround where the sec_src clock gating needs to be disabled during switching. To enable this set disable_sec_src_gating in the mux struct. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ drivers/clk/qcom/clk-krait.h | 1 + drivers/clk/qcom/krait-cc.c | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index b6b7650dbf15..7ba5dbc72bce 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -18,13 +18,23 @@ static DEFINE_SPINLOCK(krait_clock_reg_lock); #define LPL_SHIFT 8 +#define SECCLKAGD BIT(4) + static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) { unsigned long flags; u32 regval; spin_lock_irqsave(&krait_clock_reg_lock, flags); + regval = krait_get_l2_indirect_reg(mux->offset); + + /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ + if (mux->disable_sec_src_gating) { + regval |= SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + regval &= ~(mux->mask << mux->shift); regval |= (sel & mux->mask) << mux->shift; if (mux->lpl) { @@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) } krait_set_l2_indirect_reg(mux->offset, regval); + /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ + if (mux->disable_sec_src_gating) { + regval &= ~SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + /* Wait for switch to complete. */ mb(); udelay(1); diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h index 9120bd2f5297..f930538c539e 100644 --- a/drivers/clk/qcom/clk-krait.h +++ b/drivers/clk/qcom/clk-krait.h @@ -15,6 +15,7 @@ struct krait_mux_clk { u8 safe_sel; u8 old_index; bool reparent; + bool disable_sec_src_gating; struct clk_hw hw; struct notifier_block clk_nb; diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 299eb4c81d96..cb8b267f1dc5 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -157,6 +157,7 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; + mux->disable_sec_src_gating = true; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) From patchwork Mon Mar 21 15:38:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32720C4332F for ; Mon, 21 Mar 2022 16:08:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350742AbiCUQJ7 (ORCPT ); Mon, 21 Mar 2022 12:09:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350737AbiCUQJ5 (ORCPT ); Mon, 21 Mar 2022 12:09:57 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE2C728E1B; Mon, 21 Mar 2022 09:08:30 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id j18so11741005wrd.6; Mon, 21 Mar 2022 09:08:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QkfgyebL6ZDeFyix3jLmVd6pOSFa+uhSyC95dgb9bxk=; b=Xy7btiTOmGxwpKCPRMyNOEmU43iq6KqMdSjxxbMx2tfdQZUfVCDyvrSnyfWJcIxdbl EH6tRWlZL6QTCAUhCO9A7BNlKp2oipTIziduV/XaeCdqdma4bK/hzcbg4Cu85GpNaxD5 wFDN6K8HFq+yVp8jVJcKIqXviwoTyLkSKtWC/36sGpVivyUWeVFgUzddqkau1EsHOFE0 KT0vvzo3BxWSTtbKSR2ma4qMmFZC5NIwpBTHWjNmCFlVjDBvYlmCasmb74m83cwaR0XZ 5zxtKkq99AI1/sFWRhug35FEB0DsvhnUVnw4XW0qZKsF7kxh+GMBFS3/AEGKAxeKoDKX eKWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QkfgyebL6ZDeFyix3jLmVd6pOSFa+uhSyC95dgb9bxk=; b=sRcjdoB/tWINpZv90qgmgudJVh3Da+vOL8bBOofKYYVPgCS6JZDZDlC0p5TVJ3hivG VZbnvk8Hx30Ft0HLbhVAOtCjPxc42ShQD7NtTsTRNDyeJr8UlanCQ654XQJYFcB2q90y 2jTWYdGrmmwTYxZrK6Ct4Pp2S0Zdpb1bp+yPiVOpTxcfEd6zbRBiPeZ127YSKBZAzqxc JtnC7Rfo4Y8dTmEivAivW0bVnQIT5JzpjZs0kAxBGv1n+cwfD8ooKQb4cZ5CUbLZkm6k 56rCqXpBGZsJpO83+EKoQvP6HOzex0yc87PMkPQRNqbid3988WyVnXVUZm5ZD+wILDX0 0M0Q== X-Gm-Message-State: AOAM531zaTh6uz/mDrhF6nrU8n532Tx4BjYw234ecbOnjxJ8UughXeye UDTU4ADwJU/zh9xzBZPBdC4= X-Google-Smtp-Source: ABdhPJwnoYA15mOBjwq6yKBPgoqniTSCmwQ9Mkz8feT//Dxhgvf2CEQBKFYz0HNRAupHjSaRyzLxTQ== X-Received: by 2002:a5d:4609:0:b0:203:e792:3add with SMTP id t9-20020a5d4609000000b00203e7923addmr18527741wrq.657.1647878909233; Mon, 21 Mar 2022 09:08:29 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:28 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 13/18] clk: qcom: clk-krait: add enable disable ops Date: Mon, 21 Mar 2022 16:38:50 +0100 Message-Id: <20220321153855.12082-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add enable/disable ops for krait mux. On disable the mux is set to the safe selection. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 7ba5dbc72bce..061af57b0ec2 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -85,7 +85,25 @@ static u8 krait_mux_get_parent(struct clk_hw *hw) return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); } +static int krait_mux_enable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux = to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->en_mask); + + return 0; +} + +static void krait_mux_disable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux = to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->safe_sel); +} + const struct clk_ops krait_mux_clk_ops = { + .enable = krait_mux_enable, + .disable = krait_mux_disable, .set_parent = krait_mux_set_parent, .get_parent = krait_mux_get_parent, .determine_rate = __clk_mux_determine_rate_closest, From patchwork Mon Mar 21 15:38:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16B36C433F5 for ; Mon, 21 Mar 2022 16:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244869AbiCUQKE (ORCPT ); Mon, 21 Mar 2022 12:10:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350743AbiCUQKB (ORCPT ); Mon, 21 Mar 2022 12:10:01 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A38C626545; Mon, 21 Mar 2022 09:08:31 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id q8so10014255wrc.0; Mon, 21 Mar 2022 09:08:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1jgvLflAAxvBosKOEF7kDL1G6ja5R1z9b1ecY6UNmPM=; b=HW6g5DmXYm7CObQoSgVn4zPDpAjFD3bDdHCh+llYXBmJSRTYYHRkFltc3dwFjJjYZx Ox9u/GjIEHVXROUztfH2Utsz+7jTPJGbJJdG/jpfaHRe6tB2cUBRzkmxtzsI5KB8hrHI KsaIa6IIt6vHGxPwHyJTkRMrZlV/OnAf/9iUL1RM53ByEI4qexM6i0izKZf7lK4yVbr7 tOYP14HOW9kUUm82k4yzzFjThFyMsb9HvCHZf7kstfFAbatwPW3zYjXosxVoFliJ9PrP gSKDyNd1Jgbw7th2cyVfT8bMNwCs60IYduYZty0kIqBeObRNyAgwLbEmHHUy8Z7D78Eg fFrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1jgvLflAAxvBosKOEF7kDL1G6ja5R1z9b1ecY6UNmPM=; b=s9h2r7nwv3h1OWGSb5GTnjZakBPyZzG7spbIxbN6fIscjzUiO8+DBx01KNmEwx+k1X KA3Bp/N5Je5qUdeQvcavxDDja7WHlK2l/jCn7yf9R7TPx5kmrygrPVmYZ3grEQnyMEGj r40mlMpEWf4DSYXCkhjOwNe5Pq+Qzb4PBz4qe5/STkYQwa2SBqyMMGIFc7BJNRirgxGK /sDwvgyvZk6qCBTvpSBccrqArp2IJ5PGp2dCqXo0XRvQ5bPeSdxepWhhWO1aEsfV4kfv Rfe0ugt8UcdnvWdtR90rg4uG7S5a7ruYQ3UwrWcXyHVHXyP0u81SMcahiZzNWEyz08XF LO3A== X-Gm-Message-State: AOAM533KDOyhdkWG6aR5uFTYcUMlk951sXZlX04aic5oAJTzLucO0tN2 KGxpt5tj5zv2SNe5atG0Wb0= X-Google-Smtp-Source: ABdhPJxUuasmpEvkC2pyxaysuBRVgcCYvD4XZuImNMGvntedUuWyzkyZ/Wiqi7uTLeB1LwqssBL58g== X-Received: by 2002:adf:c10b:0:b0:1ed:c40f:7f91 with SMTP id r11-20020adfc10b000000b001edc40f7f91mr18536219wre.276.1647878910252; Mon, 21 Mar 2022 09:08:30 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:29 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v5 14/18] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Mon, 21 Mar 2022 16:38:51 +0100 Message-Id: <20220321153855.12082-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert qcom,krait-cc to yaml Documentation. Signed-off-by: Ansuel Smith Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../bindings/clock/qcom,krait-cc.txt | 34 ----------- .../bindings/clock/qcom,krait-cc.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..e879bfbe67ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Ansuel Smith + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: acpu0_aux + - const: acpu1_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&hfpll0>, <&hfpll1>, + <&acpu0_aux>, <&acpu1_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", + "acpu0_aux", "acpu1_aux", "qsb"; + #clock-cells = <1>; + }; +... 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:30 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v5 15/18] dt-bindings: clock: Add L2 clocks to qcom,krait-cc Documentation Date: Mon, 21 Mar 2022 16:38:52 +0100 Message-Id: <20220321153855.12082-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Krait-cc qcom driver provide also L2 clocks and require the acpu_l2_aux and the hfpll_l2 clock to be provided. Add these missing clocks to the Documentation. The driver keep support for both old and this new implementation and should prevent any regression by this fixup. Signed-off-by: Ansuel Smith Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,krait-cc.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml index e879bfbe67ac..f89b70ab01ae 100644 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -23,16 +23,20 @@ properties: items: - description: phandle to hfpll for CPU0 mux - description: phandle to hfpll for CPU1 mux + - description: phandle to hfpll for L2 mux - description: phandle to CPU0 aux clock - description: phandle to CPU1 aux clock + - description: phandle to L2 aux clock - description: phandle to QSB fixed clk clock-names: items: - const: hfpll0 - const: hfpll1 + - const: hfpll_l2 - const: acpu0_aux - const: acpu1_aux + - const: acpu_l2_aux - const: qsb '#clock-cells': @@ -50,10 +54,10 @@ examples: - | clock-controller { compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, - <&acpu0_aux>, <&acpu1_aux>, <&qsb>; - clock-names = "hfpll0", "hfpll1", - "acpu0_aux", "acpu1_aux", "qsb"; + clocks = <&hfpll0>, <&hfpll1>, <&hfpll_l2>, + <&acpu0_aux>, <&acpu1_aux>, <&acpu_l2_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", "hfpll_l2", + "acpu0_aux", "acpu1_aux", "acpu_l2_aux", "qsb"; #clock-cells = <1>; }; ... From patchwork Mon Mar 21 15:38:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B359C4167B for ; Mon, 21 Mar 2022 16:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350765AbiCUQKJ (ORCPT ); Mon, 21 Mar 2022 12:10:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350715AbiCUQKI (ORCPT ); Mon, 21 Mar 2022 12:10:08 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B17D12983C; Mon, 21 Mar 2022 09:08:33 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id r190-20020a1c2bc7000000b0038a1013241dso8672494wmr.1; Mon, 21 Mar 2022 09:08:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KF5KajzdUjlsueHw3PGEQrW6QOzbz3BzoTgHX03BJeo=; b=Wq2ZuLhEWV9Oh1GYkPcRjeiUs1VJkKuGaQ7sd9hkFLt0al93PXHrqUFp62gNPBH5fT 5xT59NYoBmZ5VRNpt+olIdKzsWEKuBdl/E5ikdS/OriFu6+YSgg86wZlF+Fv0EhLMkPH 7S1j44KxYr5Hr8d2EOYLJ22ZtMSul33sU3FIa0GI6zjFnbKoyGzIC1FK1j0meWWPwVZt /1ZGre9N409xgFno3Q9/PWevVFW7ra/ZeNOTs/vKR9VE09Db9fTeHCC53bDzuuAkv3IH XIvh0CLWS2fkg6syAxmeUpmxIhPZiLgo9GEtKcSYGqyGyt1q5Z+hsvMpk2q4fnXADVmw ubPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KF5KajzdUjlsueHw3PGEQrW6QOzbz3BzoTgHX03BJeo=; b=4x1LUzn6E32r9Z3QYN2XVQowK+LfPmNSASETYjCGATRBLhgCImzay4lMvOrgbtP+L4 ssgls0f1yYglzdo9Tf37enYEL5b2xfyEStY7NJb6YMxkM5/+xIdfA2yWWNG4s9oWbIQ/ v4TxPafhIVVWJdB5NTpObbHuTS+uMj6Fz+3CZc1q13EPzvHNIaKtaPnOgE1o60MGX+m3 YllvcSyUjrmdm/ykE2wzzR8y6/JKH21+ydokajF/uW6d6ta1cLiS22fnTTtRh6d4L9cv Oi/Ea+ws/DsomqjPe+og/KFfl3TD+d3OTPUALJDmHNrX+yLjEFDMbS1ZmmCmT2c8FIZM P52Q== X-Gm-Message-State: AOAM531iAd4+A4Di34gecbqCkxWprUK/bjqWo95An05HA6It6ppj5jJG zAD+CgJo09L6OV82/eRZhT9Ggo1Sltk= X-Google-Smtp-Source: ABdhPJzm8NfywMt+ZvIRkIQgbRFeUCVCYNOZ+QM1nXnq5kVRxBgrVaSbIFINbggsvME62wH+uNgiFg== X-Received: by 2002:a1c:2744:0:b0:382:a9b7:1c8a with SMTP id n65-20020a1c2744000000b00382a9b71c8amr19776122wmn.187.1647878912369; Mon, 21 Mar 2022 09:08:32 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:31 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 16/18] ARM: dts: qcom: qcom-ipq8064: add missing krait-cc compatible and clocks Date: Mon, 21 Mar 2022 16:38:53 +0100 Message-Id: <20220321153855.12082-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing krait-cc clock-controller and define missing aux clock for CPUs. Also change phandle for l2cc node to point to pxo_board instead of gcc PXO_SRC. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..888f17d64283 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -468,11 +468,19 @@ IRQ_TYPE_EDGE_RISING)>, acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; adm_dma: dma-controller@18300000 { @@ -782,11 +790,21 @@ tcsr: syscon@1a400000 { l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; clock-output-names = "acpu_l2_aux"; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, + <&acc0>, <&acc1>, <&l2cc>, <&qsb>; + clock-names = "hfpll0", "hfpll1", "hfpll_l2", + "acpu0_aux", "acpu1_aux", "acpu_l2_aux", + "qsb"; + #clock-cells = <1>; + }; + lcc: clock-controller@28000000 { compatible = "qcom,lcc-ipq8064"; reg = <0x28000000 0x1000>; From patchwork Mon Mar 21 15:38:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CB6BC4332F for ; Mon, 21 Mar 2022 16:09:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350827AbiCUQK2 (ORCPT ); Mon, 21 Mar 2022 12:10:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350770AbiCUQKI (ORCPT ); Mon, 21 Mar 2022 12:10:08 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93B7E2A24A; Mon, 21 Mar 2022 09:08:35 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id b19so21348082wrh.11; Mon, 21 Mar 2022 09:08:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=e6CBS8LdYYo1w7dXhFqcS8AmrcQet4Ln8lA/fEmtzfE=; b=oo3CAOucSS709pyI1ESUzQ1lg0kwjGX3NE9A3LXDfzgXAX4eHmoVSNqOrFYXgmX5B5 g80AIAnCoqVH8V27ks6dMqIgzH73lfae/qNckZa7ZQCiTcShDRBKuSXq3A7cq43CgmMY 20/tQbYEOeVF6hv2VwG5D7ulNOrqfq3ylzMHhhR0PCdNUHPCaXhYE8kUHoitVcGe8Hfl tB4WKXyWot9umgtiwiHLLiP7ZZaSBn9PKM1TDC0bkSIheEDsPpTtRzNPNFJDfoORmKOI wybVLaxZ8YEcKjZVioMAaXH4tXHo9PSx2bxYFK6RWGfhFONB1pZ4My8XC0vbChwXckiO Gk4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e6CBS8LdYYo1w7dXhFqcS8AmrcQet4Ln8lA/fEmtzfE=; b=p+3dA/XXV8w7yUzmvGFMmMUQbyq0ovP77GR6I2EE9k5CxQSPn2Mgrl9FLg3goIoI+7 1QMkxQ/W4K9E6RIWfHDYzYo6fzqtzkT3y7dhsll3MGFmwYoXZT+SI5mgXD6zPeaigxyQ KTRHzZYcPpd0FM3VhURt0jnrvE8f+QkxhR0zZTmBiAeOAs1jI/WfxPkNW2oM3eXuzX5W bJmhtWw9wyUHJAGsJoa82wU8t2lxblw/kVZ8AUSYY7G6nnKT2YkiGyTXnIq/P2AKjDbs 1sNDIaS91qP2UzinKIoeyviZTAk5Cls3RcqXLUa3uXtCZKHiJeUbz4ET1hwz1fFFqJIL eZQw== X-Gm-Message-State: AOAM530rqpmUXhriG9WB9XstiZ4Z5iS8GTCVeSsvmaGRfxJD5MxTAfO9 MRUiFNyVTHAvmzGCVj9E0os= X-Google-Smtp-Source: ABdhPJxRJ8THz6zCF9IMlECfHPlwDOBSeYfYUhDqo1K6UXzKMDAZDbB83Ez5YKY8HdmBkBTVvucgzQ== X-Received: by 2002:adf:fa87:0:b0:203:f28e:76c3 with SMTP id h7-20020adffa87000000b00203f28e76c3mr14754094wrr.579.1647878913351; Mon, 21 Mar 2022 09:08:33 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:32 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 17/18] dt-bindings: arm: msm: Convert kpss-acc driver Documentation to yaml Date: Mon, 21 Mar 2022 16:38:54 +0100 Message-Id: <20220321153855.12082-18-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, limit all the additional bindings (clocks, clock-names, clock-output-names and #clock-cells) to v1 and also flag that these bindings should NOT be used for v2. Signed-off-by: Ansuel Smith --- .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ---------- .../bindings/arm/msm/qcom,kpss-acc.yaml | 94 +++++++++++++++++++ 2 files changed, 94 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 7f696362a4a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: optional - Value type: - Definition: Name of the output clock. Typically acpuX_aux where X is a - CPU number starting at 0. - -Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml new file mode 100644 index 000000000000..707a81a6c30e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-acc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +maintainers: + - Ansuel Smith + +description: | + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. + +properties: + compatible: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,kpss-acc-v1 + then: + required: + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + else: + properties: + clocks: false + clock-names: false + clock-output-names: false + '#clock-cells': false + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + - | + clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; +... 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm2603864wmb.36.2022.03.21.09.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 09:08:34 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 18/18] dt-bindings: arm: msm: Convert kpss-gcc driver Documentation to yaml Date: Mon, 21 Mar 2022 16:38:55 +0100 Message-Id: <20220321153855.12082-19-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321153855.12082-1-ansuelsmth@gmail.com> References: <20220321153855.12082-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert kpss-gcc driver Documentation to yaml. Since kpss-gcc expose a clock add the required '#clock-cells' binding while converting it. Signed-off-by: Ansuel Smith --- .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 ------------ .../bindings/arm/msm/qcom,kpss-gcc.yaml | 68 +++++++++++++++++++ 2 files changed, 68 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..20ee182eb16f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Ansuel Smith + +description: | + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation). + +properties: + compatible: + items: + - enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 + - const: qcom,kpss-gcc + + reg: + maxItems: 1 + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + const: acpu_l2_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; + }; +... +