From patchwork Mon Mar 21 23:15:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3BB6C4321E for ; Mon, 21 Mar 2022 23:45:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233220AbiCUXql (ORCPT ); Mon, 21 Mar 2022 19:46:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233178AbiCUXqk (ORCPT ); Mon, 21 Mar 2022 19:46:40 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BB96814A1; Mon, 21 Mar 2022 16:45:14 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id q8so11398420wrc.0; Mon, 21 Mar 2022 16:45:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=nfnXXrJNDBHu6L3/3fnL54OTuTY/TOoyupK/y0ERfHUB5ubPg+IHTueg23BCOcpUJA MQlYbLnrR24YvkzaCAvJhMT6PnmyVSUOyP4xBQQAgxD6SDZ1JVYkqi3nK/QzbCYGRl07 IEXAqkQ0rtbFma5UBKPuK42mtYHscR+oMx3jX2v0GMuVF+chm3lHgjZ3OzFCDiqPIGiZ XNJrKS3R5ttsAH7CK/jJJdg7vWCmDnnYTEgXcyzojtXpTxzjYRMtOhXBAfP58gOHGu4s 37YSgTJURd+g5Yn//AvkAdHDxy2e14ZN6ll8LkuXCvFjFlgqwTsLUS9psAz0rQOSZUw4 NjKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=4p/6zB/fZQRLtN7rCaAfn1tOIeMzHb3oLyU0W/RwvPHxgufJYnc208GQHTRCIgMgdA u6nnY+Cibn71XkencMqftlalJyTf+evDP3SfjeDJN8NaRgepL0bywb3N6l4yUNyCdDoA 75IAUoNgtOmIvOmpFB3WpbJM7Q0stVVCjlvr19Pzde1AjdADwWnrSBGODymbP/lRBLR6 NpeNZKX0oXHAC9y5qsI3vLRoCwG07wo7v6lpjGfurHi6jZaClaW2OCWJ9jD89dDQogSg QEbU4TaE53me5bxtikLCk4WOlUXaMbz+lvqkNFJMq3SZVk68kDHixDUuLa5adItfJnJc TDXw== X-Gm-Message-State: AOAM533IHooV10K1imH0avxjQAcKLfr/FxfLr/UqJ1GQY22dP2yECGi4 tc5Jt3QNuAZrO38QQ2YMhHNh6EkOnqE= X-Google-Smtp-Source: ABdhPJz6fFRCSWvddMgG1C1fG5SdUZrT01T7lf/GjbY9YYA8kELNPFzSv3x9irwbdz+4n77HV4Tk8Q== X-Received: by 2002:a5d:64c2:0:b0:203:951c:17f2 with SMTP id f2-20020a5d64c2000000b00203951c17f2mr20466856wri.518.1647906312892; Mon, 21 Mar 2022 16:45:12 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:12 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 01/18] clk: introduce clk_hw_get_index_of_parent new API Date: Tue, 22 Mar 2022 00:15:31 +0100 Message-Id: <20220321231548.14276-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Clk can have multiple parents. Some clk may require to get the cached index of other parent that are not current associated with the clk. We have clk_hw_get_parent_index() that returns the index of the current parent but we can't get the index of other parents of the provided clk. Introduce clk_hw_get_index_of_parent() to get the cached index of the parent of the provided clk. This permits a direct access of the internal clk_fetch_parent_index(). Signed-off-by: Ansuel Smith --- drivers/clk/clk.c | 14 ++++++++++++++ include/linux/clk-provider.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8de6a22498e7..bdd70a88394c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1726,6 +1726,20 @@ int clk_hw_get_parent_index(struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_get_parent_index); +/** + * clk_hw_get_index_of_parent - return the index of the parent clock + * @hw: clk_hw associated with the clk being consumed + * @parent: clk_hw of the parent to be fetched the index of + * + * Fetches and returns the index of parent clock provided. + * Returns -EINVAL if the given parent index can't be provided. + */ +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent) +{ + return clk_fetch_parent_index(hw->core, parent->core); +} +EXPORT_SYMBOL_GPL(clk_hw_get_index_of_parent); + /* * Update the orphan status of @core and all its children. */ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2faa6f7aa8a8..5708c0b3ef1c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1198,6 +1198,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent); int clk_hw_get_parent_index(struct clk_hw *hw); int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); From patchwork Mon Mar 21 23:15:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60D83C4167B for ; Mon, 21 Mar 2022 23:45:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233226AbiCUXqn (ORCPT ); Mon, 21 Mar 2022 19:46:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233221AbiCUXqm (ORCPT ); Mon, 21 Mar 2022 19:46:42 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFAC778FD7; Mon, 21 Mar 2022 16:45:15 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id b19so22738153wrh.11; Mon, 21 Mar 2022 16:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=hi1U7vy+Z/G7HaX9Jgdh9FFV6s/SVC3iHxQighhGvy9F/4rhKwsNeB+PWRxBzy3RE/ jlwU4rDmTxLbX1ZSPpSSL6BulGJ7nxr971pNp5cu2aD2+2pjeY8GftuzLdDxpFRup5SB 5RvBsR9E7L2sZAvgdHct89raTo/Nod/4tNwbGj2z65++lb6UoyIfWb96omEpfjMSw4/V E46vaI/FxUJVVImLZQXhxQuyd2T8wsd6b2btAy9U+J6GWu4bqpxfvJdfUhcWqC9vnld2 U6pVdf7yReE1cOB0WfC7IbjcMEP4G2LJYjKWox1r+ja3om9Stm4EbM8jt1v5g9ixtPL4 rkPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=e+8/C727yPvIUej/hUGZccwqaDyfL+71/rn2bxjmkczznRLerl0Y78YPSDxAGWR4oP B7iYIm5bvpoSaQMoAB/10VJw6qNiuDk6aQQs1DZMEB37zSgCzIxL7ZZvXO0S7q6hO/Tj 5EVsVx0Mk+Hds2t9Z2P97yzGxhlVOn3MiEQ+3tU2hPEd6rjWQNqnxYSm616b3n5rUZn6 wZoeDNEomhvXYyCXK3FTFPaG6V3k3wgbpG/7UNDMVCzwAC7BUxwNd+SRpLqzhgekLSmb LkUUcvxwqw+cASnR7x2P0fEFg8OliJz1LsVD8NJIeNN8SZegYOA7qaoLQRnoe/SXDpF/ s/bQ== X-Gm-Message-State: AOAM532SLDUnmMTTLUS15rCREeaQ+C1gjJvW1CD7clNUJ9A/W/omPdas I61PXFIFaEIeLyzZUdGlLlw= X-Google-Smtp-Source: ABdhPJxCqoksIbuidDWuZ2vyRWDA/FC9D7WNQE/UQ+P3TesXaGZ3vwjVbSuJh4gCg82rE8TI1jGVhg== X-Received: by 2002:a5d:6d8b:0:b0:203:e242:5e38 with SMTP id l11-20020a5d6d8b000000b00203e2425e38mr20670632wrs.105.1647906314193; Mon, 21 Mar 2022 16:45:14 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:13 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 02/18] clk: qcom: gcc-ipq806x: skip pxo/cxo fixed clk if already present Date: Tue, 22 Mar 2022 00:15:32 +0100 Message-Id: <20220321231548.14276-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Skip pxo/cxo clock registration if they are already defined in DTS as fixed clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..27f6d7626abb 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -3061,15 +3062,22 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct regmap *regmap; + struct clk *clk; int ret; - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "cxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); + if (ret) + return ret; + } - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "pxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); + if (ret) + return ret; + } ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) From patchwork Mon Mar 21 23:15:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0089BC433EF for ; Mon, 21 Mar 2022 23:45:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233259AbiCUXqq (ORCPT ); Mon, 21 Mar 2022 19:46:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233168AbiCUXqp (ORCPT ); Mon, 21 Mar 2022 19:46:45 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D57BA6E4C5; Mon, 21 Mar 2022 16:45:16 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id r10so22793245wrp.3; Mon, 21 Mar 2022 16:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=VtKokik8jZoQyV3SXrJav2zsYascZDoAoeYdKhrVPhTBywjJOCILD+HBgks3+onIT1 zCCcMYlFIoSUiBK29Lpxhu2GpxBMCDnOmhbPeB0lYbYf06jpkkhKZwXM8kwz6oV6uiFx MAc+flCgvYR5hhxADs/2RgSYLxIr7a5HFnNkEwgSPzwAFvNSj8gtKotLB1gwPuFzTWut XxJ1TD58yW8yDoNA5WnqeRYT1Xodqcw+lVyfLg7ZK6GvVlMauyAzkF7qqu2ObKfxqbIR 9+FdZ+qTcQI6TuhU9V2TBuT74lAP5mswSJW0ikVXdMQqt+qTt+EPNTQ9ujHobVLpj5wa Aa1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=p3L+TtVXn+is4YB3hboLLYOwEx1F/5e/ZoChcXuwg65Qs9vzLYg65irIaKtNGdMYAU R2Vd7atlz94wEblEjmBQ93+GzDOT0QVnrqQDBOmNbwFITb87rpKTb4MnUGrf7IyPpcP2 FSQ7WWJ7e6JjP7iJ4Ge8oxU6feWAyHYsKY8wqFRl9thmMEUHB8iKdhxBtiPx8iRGujN1 BsTSWc9kWtddNZioRQuZiE8blBGrS4P/UUaP280Q+S9PSm1HCuoGkApnOxHkPUCQ4t8a 3WS9VFBC0Cd8U3LwZGPfRGUXYaiibcKAvKHl/xCWOZznl0Lr4PUsOp/p7x1ke5n47dCk 3iMQ== X-Gm-Message-State: AOAM531cZYYKp+YsJlIVw1gqxnij3HYHrOIGiKRFyBO0G5SIAi/Kawf/ /44GlQY1PgtM41yy0uJOEyo= X-Google-Smtp-Source: ABdhPJxTJFdJL1hfeET4DhPZVqmLCzIdHZguEiqvmbEyux3rIVGb5NsscxI0HS2N71uidvVTJspR+A== X-Received: by 2002:a5d:584a:0:b0:203:97f6:5975 with SMTP id i10-20020a5d584a000000b0020397f65975mr19790174wrf.612.1647906315315; Mon, 21 Mar 2022 16:45:15 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:14 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 03/18] clk: qcom: gcc-ipq806x: add PXO_SRC in clk table Date: Tue, 22 Mar 2022 00:15:33 +0100 Message-Id: <20220321231548.14276-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PXO_SRC is currently defined in the gcc include and referenced in the ipq8064 DTSI. Correctly provide a clk after gcc probe to fix kernel panic if a driver starts to actually use it. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 27f6d7626abb..7271d3afdc89 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -26,6 +26,8 @@ #include "clk-hfpll.h" #include "reset.h" +static struct clk_regmap pxo = { }; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -2754,6 +2756,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }; static struct clk_regmap *gcc_ipq806x_clks[] = { + [PXO_SRC] = NULL, [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, [PLL3] = &pll3.clkr, @@ -3083,6 +3086,10 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) if (ret) return ret; + clk = clk_get(dev, "pxo"); + pxo.hw = *__clk_get_hw(clk); + gcc_ipq806x_clks[PXO_SRC] = &pxo; + regmap = dev_get_regmap(dev, NULL); if (!regmap) return -ENODEV; From patchwork Mon Mar 21 23:15:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A770C4167D for ; Mon, 21 Mar 2022 23:45:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233281AbiCUXqu (ORCPT ); Mon, 21 Mar 2022 19:46:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233239AbiCUXqp (ORCPT ); Mon, 21 Mar 2022 19:46:45 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 193AF90FF3; Mon, 21 Mar 2022 16:45:18 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id b19so22738246wrh.11; Mon, 21 Mar 2022 16:45:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=QhmJY7LtPm+UvAuVmH0Cww45PV2j8fBGDZzJz0y2y8NId+Cd2mvbcbYsW0jWKvg0cT H5yZvlSLjtNd6YryThsWfap6lf9S595n3m12OhJ6ByBrw4SmgqiPtW9CoQyt7+FWQgxp pMn9Wo2SHTXpojc1YiHuyauPtb5JGp/j3JK4fdNYktj0X6J2JkbFwi5vZKZBsbNTTqad zch49jkz9Upu80QpWJlFWrDc2gbuLNXeuP/Q/4A/aXseR4aeGbvWFfMdkG+GWd0Rt50h WYGrGbQwdPTfHHbxt4E361MeP9qtRlymgDyPkZwadH5hN88ntwBCuIuRgpRg5JwW7y1R DC4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=g75Hh0CH0hETIjIofYLyTqydKl/PvOzy/UHGjdxY1o5KPeQ0V6FV1z+F95CNsrjdBr f5JzPrHCaZvHAPGrkt1iOCAMkeRP5jhfPlvtTXCcM4N7mep4K6WOwSEzDH61suqiEScy YCBstoGJp5DqUt122d7v7NbWIWTw0A4X/t9ZBfjTAUrakBq7zlNw3CBnBoAwXlm542jf 8gEaO/ZzWcY0Zl+yVUvY6FLVlBeGFxhoeDGdFsTdzMk6xQqnJ0RXBufEf7N1m7jlpFQ9 JnF0O+lF8sn8b9qy5Ywr0cIkzPJzLpD33FGWUDtU3BDc0DnziFIdyOCOdRmHq0RaxGpq wZ7w== X-Gm-Message-State: AOAM533jvCSHcAuO4YeoTPZhgSIARiOn8O6ZfTXEw0Y7WhgYvifeZY1y M1c8uGd9jRsDS9pl4dNxLEE= X-Google-Smtp-Source: ABdhPJxmRmoCgMsgyiwehFFD8Yzdprsgc3FoR5L8FzxPCvZuXmmLtGDZwpQkmpLlYovVVi/l7qu2fg== X-Received: by 2002:a05:6000:18a3:b0:204:1f84:287e with SMTP id b3-20020a05600018a300b002041f84287emr1940879wri.184.1647906316517; Mon, 21 Mar 2022 16:45:16 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:16 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 04/18] clk: qcom: clk-hfpll: use poll_timeout macro Date: Tue, 22 Mar 2022 00:15:34 +0100 Message-Id: <20220321231548.14276-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use regmap_read_poll_timeout macro instead of do-while structure. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-hfpll.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index e847d586a73a..a4e347eb4d4d 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -12,6 +12,8 @@ #include "clk-regmap.h" #include "clk-hfpll.h" +#define HFPLL_BUSY_WAIT_TIMEOUT 100 + #define PLL_OUTCTRL BIT(0) #define PLL_BYPASSNL BIT(1) #define PLL_RESET_N BIT(2) @@ -72,13 +74,12 @@ static void __clk_hfpll_enable(struct clk_hw *hw) regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); /* Wait for PLL to lock. */ - if (hd->status_reg) { - do { - regmap_read(regmap, hd->status_reg, &val); - } while (!(val & BIT(hd->lock_bit))); - } else { + if (hd->status_reg) + regmap_read_poll_timeout(regmap, hd->status_reg, val, + !(val & BIT(hd->lock_bit)), USEC_PER_MSEC * 2, + HFPLL_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); + else udelay(60); - } /* Enable PLL output. */ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); From patchwork Mon Mar 21 23:15:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51F8CC43217 for ; Mon, 21 Mar 2022 23:45:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233268AbiCUXqr (ORCPT ); Mon, 21 Mar 2022 19:46:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233244AbiCUXqp (ORCPT ); Mon, 21 Mar 2022 19:46:45 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D1669155D; Mon, 21 Mar 2022 16:45:19 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id r13so7718375wrr.9; Mon, 21 Mar 2022 16:45:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=lVO9HrJJ4uaEXgoPoWdmank4eHDo4BCCdWrs5Ekg1S/+9vexHt1mPqzANAhHY7/anH qav9bD2svlyvH/SA55ORQ8LcPEegLT98gtYxV1qq2jWWg5tNZ1tT1di6PmPQy5UvvJST G9x1ec6XcQMDFfpl3Li33IAYenzOg3nV5fHgkNlb7kEedL1Oqimt2KmuNmrvmiJTm0Cw D9r2XquJCegHA0/gEsyc6S2SobXe3a2vZZZAqEM/UP28iz8/1pZ2a9Gm4oIVmODcsXHW 3ps9qFBmNa9NWGu+ecaEw5cFq4ePnFzy9CTsyWEwLcj0d5/7Ed1CZEFT6LlihBeCFxfb U7IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=yiI3cfMEPlZP1PhpD+FqX7RMAUHVrcG6m8d2ZPYE+YAsln4BxkbrC06Aa/F/dmdQP0 qIwtseRXKKLU/SaEo1TM2bkqHaLJK+OSEBTgy6oDt1FcS6mEUDy5+sl5GSHNWR+TI4ov ti6qiu/ZgTWJwaGQAETYHlOkq/4+S9rN7mboDx+omMWy8BETdE9efaY3UtLdYaauVjP+ SGh8VPW/3jxZDqsjgJ5TgW3Pg1vUUE7AWsuQpbJLXuQPK5ikKtVDr9U4BUTWLy77dOEw Drw3qxDFGQ9c28q2GDkZ4wF6v/iZ6A3RUbPyRuSBTUOaN7wimzDRx5mmbt7NJ5mBWtQZ xD8w== X-Gm-Message-State: AOAM5333m2sYnPLMpH+dTjf7169bBh1ECm09HgT91HWTuL7NsvJ+uac6 p9zAlSRqoNTn18+SWIwoDmeQTc7zlng= X-Google-Smtp-Source: ABdhPJxZjFiCpmRSrWXQL0OXJ6c9dpG8YOoFBJg7rzTZsJoHYd5zEDmnMioKyaz2o1aTdPwZbPZ/XA== X-Received: by 2002:a5d:59a5:0:b0:203:d46b:f27a with SMTP id p5-20020a5d59a5000000b00203d46bf27amr20587276wrr.126.1647906317561; Mon, 21 Mar 2022 16:45:17 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:17 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 05/18] clk: qcom: kpss-xcc: convert to parent data API Date: Tue, 22 Mar 2022 00:15:35 +0100 Message-Id: <20220321231548.14276-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. Name is still used to save regression on old definition. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/kpss-xcc.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c index 4fec1f9142b8..347f70e9f5fe 100644 --- a/drivers/clk/qcom/kpss-xcc.c +++ b/drivers/clk/qcom/kpss-xcc.c @@ -12,9 +12,9 @@ #include #include -static const char *aux_parents[] = { - "pll8_vote", - "pxo", +static const struct clk_parent_data aux_parents[] = { + { .name = "pll8_vote", .fw_name = "pll8_vote" }, + { .name = "pxo", .fw_name = "pxo" }, }; static unsigned int aux_parent_map[] = { @@ -32,8 +32,8 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); static int kpss_xcc_driver_probe(struct platform_device *pdev) { const struct of_device_id *id; - struct clk *clk; void __iomem *base; + struct clk_hw *hw; const char *name; id = of_match_device(kpss_xcc_match_table, &pdev->dev); @@ -55,24 +55,15 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev) base += 0x28; } - clk = clk_register_mux_table(&pdev->dev, name, aux_parents, - ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, - 0, aux_parent_map, NULL); + hw = __devm_clk_hw_register_mux(&pdev->dev, NULL, name, ARRAY_SIZE(aux_parents), + NULL, NULL, aux_parents, 0, base, 0, 0x3, + 0, aux_parent_map, NULL); - platform_set_drvdata(pdev, clk); - - return PTR_ERR_OR_ZERO(clk); -} - -static int kpss_xcc_driver_remove(struct platform_device *pdev) -{ - clk_unregister_mux(platform_get_drvdata(pdev)); - return 0; + return PTR_ERR_OR_ZERO(hw); } static struct platform_driver kpss_xcc_driver = { .probe = kpss_xcc_driver_probe, - .remove = kpss_xcc_driver_remove, .driver = { .name = "kpss-xcc", .of_match_table = kpss_xcc_match_table, From patchwork Mon Mar 21 23:15:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB6B8C433F5 for ; Mon, 21 Mar 2022 23:45:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233302AbiCUXqv (ORCPT ); Mon, 21 Mar 2022 19:46:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233264AbiCUXqq (ORCPT ); Mon, 21 Mar 2022 19:46:46 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24AE991AF3; Mon, 21 Mar 2022 16:45:20 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id h4so4793993wrc.13; Mon, 21 Mar 2022 16:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=AeVv7fxFBnMYc6TyGPQJgqr6Os1ISVirKCBnb0cEjT23JRQiN3kzSkbJC0WGd3S7U3 vuFTIdYM6A1YIEX5acudsY8cHSuJRoMOa9mi+QoIsisQ6LwKy03eGnozYKYM6/GHetaQ N1pdi/Lojc3qRPlYDHAPF82xNp76yMtyK+ujOYFzMR6Rhq7+gVN8rtlHEcDZtsuw5TNk mteDjvKEamD61BrgfDvh7G1hSK3Ah7yaYskBUKoewGEuf2CEane2pVgy+1/orAIx7vcm HWJiToqyVRIWr6Tjm8c0Lr0tMk1YIz2D1ysWr6JYXdnJPWS/h4EjCIK8QpBtkm40tK0s rcMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=7BOmn4wgmsrVr2HVChFUjDloGy1xrHjyp5UuA4zpUxv+USlKNpoRba6V2kP6Jeq1BY ne8fzVT8fMqJIKBEdS6RCrczqXzAVcfdR8kNIIPREK6oMKNkrHQ6VbLsAGCkvfxkUvVE HjDp1wj3ZVet927E3ayaRGxFICTNT9br+6QsRa/2276xEvU1Rlar7IeuI/bQVRZQSxP1 MhEZ0JgjyW1zLf41rJcfe//GdX9onLXXXvlP1CJ3d6B+J59Hb/Vr60XME3iFlin3gwjS 3EkAjLLCDTLMIhKWbN3jmiAFGMbCHpgIHtRC+kosQIcNUj2P5hRr+nZQXpbEKQP9b6m7 gtog== X-Gm-Message-State: AOAM533rQzXQSxBf9Ew+6vTldQ/pWyqNOEc4qDBcLDPAYVRQSUAu/ZPv C2bc84o22naC1NICELRvUpU= X-Google-Smtp-Source: ABdhPJxNPd77bvjDTqhT6guQSbqvAquPuH8wDOmtU4K7LLM2fm96J7tPK8SxTOhH8GsSmBY3HCimNw== X-Received: by 2002:a5d:6c66:0:b0:204:93b:5dee with SMTP id r6-20020a5d6c66000000b00204093b5deemr7880786wrz.332.1647906318565; Mon, 21 Mar 2022 16:45:18 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:18 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 06/18] clk: qcom: clk-krait: unlock spin after mux completion Date: Tue, 22 Mar 2022 00:15:36 +0100 Message-Id: <20220321231548.14276-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Unlock spinlock after the mux switch is completed to prevent any corner case of mux request while the switch still needs to be done. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 59f1af415b58..e447fcc3806d 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -32,11 +32,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); } krait_set_l2_indirect_reg(mux->offset, regval); - spin_unlock_irqrestore(&krait_clock_reg_lock, flags); /* Wait for switch to complete. */ mb(); udelay(1); + + spin_unlock_irqrestore(&krait_clock_reg_lock, flags); } static int krait_mux_set_parent(struct clk_hw *hw, u8 index) From patchwork Mon Mar 21 23:15:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18302C4332F for ; Mon, 21 Mar 2022 23:45:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233318AbiCUXqx (ORCPT ); Mon, 21 Mar 2022 19:46:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233231AbiCUXqu (ORCPT ); Mon, 21 Mar 2022 19:46:50 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2ED829155C; Mon, 21 Mar 2022 16:45:21 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id v22so8847821wra.2; Mon, 21 Mar 2022 16:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uKLqUE0HqMblkYxTDEoLkraH8fYkNKsZ80vlgdu8msQ=; b=PSd5RElnYKdfT7JJ4xRmSZsf3s4ZZ2M6RghbeBlNBFjRzifBRgCWiDV7DrMIm4b7eX +s+QJOlASeV7W5CEHDrrK18BOw/rSPYOQpWO2ewmXSnwQzVb0XlkJttSS62WbzINMXjH fM2MYijB/38Dk4gB5R1MXNPmTK1c0Bg1V4ge4p1dZQtgEqQPV1BI4CicnnJfC3yJkPtZ IXQL1Mz/4H+QwCEhMSAOb2RQ3OOokFFBNsGeiOOt7Uh1lOPR5hu/V5R4pdhJHi1szrd3 hkIxMzx7ihaKt3cI6rHaVeorrGgc9w4z3sHmRS2vykSBNMoSvlq2kIut1PDcHDSjkZeX X90w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uKLqUE0HqMblkYxTDEoLkraH8fYkNKsZ80vlgdu8msQ=; b=gw1Xt8clpNeyB2ei15HtJDmI/8E8OvUjuUIVPnwc9FEL/GW0Q6smSqjzuTdtmH0bMY gJKc3YHOTKSVSGjPWXvTD45CfcE3lg1hvjGzSM/XpsUfwkPFqmzGgXBB7+uGafbFLm4S +TnhF75TRmBhVSU/u73wVeujez7CV9J4SqgpRp90gdAlV7kVJA6JJIF7hF8JXFIQ3x30 bkGKqjPsRr65NO14/NdrtcHEYs+9xuOoNURQsS1B6f69mPc2J2ja7uEfUvPJm9jSh8V9 jiPMw1gUHGrMhUX6ysYI41n3+c/M+h22LS7+8LJeRCAhE8NjuWxnWb6CaoCxmSyJ1zjl JcSQ== X-Gm-Message-State: AOAM531nGAMN+0N/D0oaBLQhuK0b71cDMoApsT9uIQNUB7Ry6PUTgF6b W0uA0pJpCgFi0BTXa1DJq7L6QrUQPz4= X-Google-Smtp-Source: ABdhPJygX3L7achtlpOONDVhOVZGbv6VOE93/ieKdwpP8aYhxet/ApXPkN9SKzQ40eRhSJNKomj63Q== X-Received: by 2002:adf:9581:0:b0:1ed:c341:4ed1 with SMTP id p1-20020adf9581000000b001edc3414ed1mr19797135wrp.299.1647906319637; Mon, 21 Mar 2022 16:45:19 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:19 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 07/18] clk: qcom: clk-krait: add hw_parent check for div2_round_rate Date: Tue, 22 Mar 2022 00:15:37 +0100 Message-Id: <20220321231548.14276-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Check if hw_parent is present before calculating the round_rate to prevent kernel panic. On error -EINVAL is reported. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index e447fcc3806d..b6b7650dbf15 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -80,7 +80,12 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops); static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); + struct clk_hw *hw_parent = clk_hw_get_parent(hw); + + if (!hw_parent) + return -EINVAL; + + *parent_rate = clk_hw_round_rate(hw_parent, rate * 2); return DIV_ROUND_UP(*parent_rate, 2); } From patchwork Mon Mar 21 23:15:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86F0CC3527A for ; Mon, 21 Mar 2022 23:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233309AbiCUXqv (ORCPT ); Mon, 21 Mar 2022 19:46:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233103AbiCUXqu (ORCPT ); Mon, 21 Mar 2022 19:46:50 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 743FB71A28; Mon, 21 Mar 2022 16:45:22 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id m26-20020a05600c3b1a00b0038c8b999f58so476445wms.1; Mon, 21 Mar 2022 16:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=hiHC7+u/O24dlx4PK+OqYlwl6uxRb8W8TVVZWptCo0U5aJL/JCwsPUoMc7TE7hakKq h/DVVo/xiuraA+a27ZBsZqennJZYkbZpYDnSXUvoi5TM4c4R5f7V3SbWQviqtJTa0+bd /g55sMFS2AGlnUNZZrEnoKeiYj1ArKbBpmorZ6NCL1gMeuULmnDJ8qzSEtrQ7lAJd/fx jyf0hgk74i/XOr01u5+64Ay1OWpYcaxylRl4OLYsthbbVMt1TRsCAWcK2lRJ0K44e3aT GvxssQZE6IEJPCP1WZpWbHoypbvNIen+ynQI9R1m7w3sF2cDBIAvmy/uTxmn7NHC8bqZ xGjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=van/Btj+n0srX6gtUdVO7R8/dv8zORESf9nxVjfjCqlt7amQVzGoTx/5NIWXXBB7zy VMIpfrTny5e1pq3LSipNmMhwOVfzGm4WIe8/kiwUogeJ5FUT6xpR6Czmve4MHuJg0x3L PxUAalIDREZrZt5Tpb/nKA+jzuLNVyIqlrSo0g63ngEJfKyTcKDLOYGOyr0ML+U3Q6/L uF9ZVXpVVBw8EHaTcREDB2UNqHET39pF0N7VtdmtyOgwqZas96gWDjLCxhwXGiKR40ag 5Ia7XPa6/xCz/kZBzg01HNj6iDMKlbYwZDCvrHnRejrhImg5AVAvo4jM2tm9uhScy0HT o7pg== X-Gm-Message-State: AOAM5317X+qBo+Gv2+2o+lpEX6+Qxy6Skyywl6hy9Ri0y0KJU2X3nCq3 IU7XnCJDjv0dGIqsWWHcew8= X-Google-Smtp-Source: ABdhPJzUv3E3jl8lD4lGmwXkPhUZ4o9yNgEr8fA7dVqQch4mCECRPQ/C2fl9aw/BuwfZymA7W9uCJQ== X-Received: by 2002:a05:600c:378d:b0:38b:e12f:edde with SMTP id o13-20020a05600c378d00b0038be12feddemr1219889wmr.69.1647906320758; Mon, 21 Mar 2022 16:45:20 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:20 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 08/18] clk: qcom: krait-cc: convert to parent_data API Date: Tue, 22 Mar 2022 00:15:38 +0100 Message-Id: <20220321231548.14276-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Modernize the krait-cc driver to parent-data API and refactor to drop any use of clk_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. Name is also declared to save compatibility with old implementation. Also fix the parent order of the sec_mux that was wrong and incorrectly report the wrong safe parent if it's not hardcoded. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 126 +++++++++++++++++++----------------- 1 file changed, 66 insertions(+), 60 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 4d4b657d33c3..645ad9e8dd73 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -69,21 +69,22 @@ static int krait_notifier_register(struct device *dev, struct clk *clk, return ret; } -static int +static struct clk * krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) { struct krait_div2_clk *div; + static struct clk_parent_data p_data[1]; struct clk_init_data init = { - .num_parents = 1, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_div2_clk_ops, .flags = CLK_SET_RATE_PARENT, }; - const char *p_names[1]; struct clk *clk; + char *parent_name; div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) - return -ENOMEM; + return ERR_PTR(-ENOMEM); div->width = 2; div->shift = 6; @@ -93,43 +94,49 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - init.parent_names = p_names; - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { - kfree(init.name); - return -ENOMEM; + init.parent_data = p_data; + parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!parent_name) { + clk = ERR_PTR(-ENOMEM); + goto err_parent_name; } + p_data[0].fw_name = parent_name; + p_data[0].name = parent_name; + clk = devm_clk_register(dev, &div->hw); - kfree(p_names[0]); + + kfree(parent_name); +err_parent_name: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } -static int +static struct clk * krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { - "acpu_aux", - "qsb", + static struct clk_parent_data sec_mux_list[2] = { + { .name = "qsb", .fw_name = "qsb" }, + {}, }; struct clk_init_data init = { - .parent_names = sec_mux_list, + .parent_data = sec_mux_list, .num_parents = ARRAY_SIZE(sec_mux_list), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *parent_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) - return -ENOMEM; + return ERR_PTR(-ENOMEM); mux->offset = offset; mux->lpl = id >= 0; @@ -141,44 +148,51 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); if (unique_aux) { - sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); - if (!sec_mux_list[0]) { + parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); + if (!parent_name) { clk = ERR_PTR(-ENOMEM); goto err_aux; } + sec_mux_list[1].fw_name = parent_name; + sec_mux_list[1].name = parent_name; + } else { + sec_mux_list[1].name = "apu_aux"; } clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto unique_aux; + clk = ERR_PTR(ret); -unique_aux: +err_clk: if (unique_aux) - kfree(sec_mux_list[0]); + kfree(parent_name); err_aux: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } static struct clk * -krait_add_pri_mux(struct device *dev, int id, const char *s, - unsigned int offset) +krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux, + int id, const char *s, unsigned int offset) { int ret; struct krait_mux_clk *mux; - const char *p_names[3]; + static struct clk_parent_data p_data[3]; struct clk_init_data init = { - .parent_names = p_names, - .num_parents = ARRAY_SIZE(p_names), + .parent_data = p_data, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *hfpll_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) @@ -196,36 +210,29 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, if (!init.name) return ERR_PTR(-ENOMEM); - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { + hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!hfpll_name) { clk = ERR_PTR(-ENOMEM); - goto err_p0; + goto err_hfpll; } - p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!p_names[1]) { - clk = ERR_PTR(-ENOMEM); - goto err_p1; - } + p_data[0].fw_name = hfpll_name; + p_data[0].name = hfpll_name; - p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!p_names[2]) { - clk = ERR_PTR(-ENOMEM); - goto err_p2; - } + p_data[1].hw = __clk_get_hw(hfpll_div); + p_data[2].hw = __clk_get_hw(sec_mux); clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto err_p3; -err_p3: - kfree(p_names[2]); -err_p2: - kfree(p_names[1]); -err_p1: - kfree(p_names[0]); -err_p0: + clk = ERR_PTR(ret); + +err_clk: + kfree(hfpll_name); +err_hfpll: kfree(init.name); return clk; } @@ -233,11 +240,10 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, /* id < 0 for L2, otherwise id == physical CPU number */ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) { - int ret; unsigned int offset; void *p = NULL; const char *s; - struct clk *clk; + struct clk *hfpll_div, *sec_mux, *clk; if (id >= 0) { offset = 0x4501 + (0x1000 * id); @@ -249,19 +255,19 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) s = "_l2"; } - ret = krait_add_div(dev, id, s, offset); - if (ret) { - clk = ERR_PTR(ret); + hfpll_div = krait_add_div(dev, id, s, offset); + if (IS_ERR(hfpll_div)) { + clk = hfpll_div; goto err; } - ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); - if (ret) { - clk = ERR_PTR(ret); + sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + if (IS_ERR(sec_mux)) { + clk = sec_mux; goto err; } - clk = krait_add_pri_mux(dev, id, s, offset); + clk = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); err: kfree(p); return clk; From patchwork Mon Mar 21 23:15:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EA98C4321E for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:21 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 09/18] clk: qcom: krait-cc: drop pr_info and register qsb only if needed Date: Tue, 22 Mar 2022 00:15:39 +0100 Message-Id: <20220321231548.14276-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace pr_info() with dev_info() to provide better diagnostics. Register qsb fixed clk only if it's not declared in DTS. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 645ad9e8dd73..e9508e3104ea 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -308,7 +308,9 @@ static int krait_cc_probe(struct platform_device *pdev) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk_get(dev, "qsb"))) + clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk)) return PTR_ERR(clk); @@ -363,25 +365,25 @@ static int krait_cc_probe(struct platform_device *pdev) cur_rate = clk_get_rate(l2_pri_mux_clk); aux_rate = 384000000; if (cur_rate == 1) { - pr_info("L2 @ QSB rate. Forcing new rate.\n"); + dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate = aux_rate; } clk_set_rate(l2_pri_mux_clk, aux_rate); clk_set_rate(l2_pri_mux_clk, 2); clk_set_rate(l2_pri_mux_clk, cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); + dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); for_each_possible_cpu(cpu) { clk = clks[cpu]; cur_rate = clk_get_rate(clk); if (cur_rate == 1) { - pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); + dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate = aux_rate; } clk_set_rate(clk, aux_rate); clk_set_rate(clk, 2); clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); + dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); } of_clk_add_provider(dev->of_node, krait_of_get, clks); From patchwork Mon Mar 21 23:15:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64E63C4332F for ; Mon, 21 Mar 2022 23:45:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233330AbiCUXqz (ORCPT ); Mon, 21 Mar 2022 19:46:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233291AbiCUXqv (ORCPT ); Mon, 21 Mar 2022 19:46:51 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F04EA27D2; Mon, 21 Mar 2022 16:45:24 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id m26-20020a05600c3b1a00b0038c8b999f58so476473wms.1; Mon, 21 Mar 2022 16:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HxwJ/rmGXQIKgHQmjTVr7v/2TGpe+xuVVbkVjt0eYLU=; b=nStquK6TyNYcOv5GJ1NxuIx/DoXoT4yjOTTkZ2xEmnVYjhaS24fYn4vBwM8DpsMg8r TR1v449Ynvl9NcMxcqhcJHoQ4vrDKi3ttElhP3+GHU0Iy0bbGizOS3etmAcZhbAkQNX3 cYI7B1GBiEn2u/47JqJuM0ZhUconBHCLDMjHjidiLdczOCcFMwm6feOoWiH9YdUwf8jd y4D0I/yupR49Dz3H5TJLdTzRTXLpHk5U7gtU0EXTdxTu96RZ+KFpJhqZg8KM/lKQuz2O fsTET5lQEIf7++R0k0XFkmaf9jgi3VWVOdaMPAvCM01sC62Vcfgfoh3hDrumUoD4ZPkF HqCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HxwJ/rmGXQIKgHQmjTVr7v/2TGpe+xuVVbkVjt0eYLU=; b=zdJBzb66mDcMiNBpDWzR1cZIOXK25tviqYwsZhVMKxvk4sOp4Tk10qOuHuYSdwu3Sc D36a3/uxu1B08LKZlvukuyWTBOpGjWvRcNQb4BQ5H1bBejDqZMxW8TqehJULJP04O6KX AMZsGy3+qQap2I0c2Exo+CVufwMUCjpipbuVXfoWT0pJ5/aM0ThHpoelvo+RP1lqYhet zzwiieNXVkFYrFY+8XxZfXOHzCflh5ZAVtFrqFVY/yp+fjT+p7SJXdVsg6ylKbjzXkCJ /d+DPhRdy18ow8Ek00SgPKlC3951y6LTcNihWzP/l5qzzOX1TsfDpLzT+AM/WRp8ymln QQsA== X-Gm-Message-State: AOAM533gSMmh9kfMRPePkw4a0GirNtPGp6gtaXzoeB2SZo6UJCtOD7eh Nita3LHLrmbRN1xYL31vJtA= X-Google-Smtp-Source: ABdhPJwRMi2XdYQnQNNkReksZJVk5TUny/4ToUYciihKHRF5DRh7NJqvvxhnotXrvmsj6ZzbI18drA== X-Received: by 2002:a7b:ce02:0:b0:381:2007:f75c with SMTP id m2-20020a7bce02000000b003812007f75cmr1291711wmc.6.1647906322774; Mon, 21 Mar 2022 16:45:22 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:22 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 10/18] clk: qcom: krait-cc: drop hardcoded safe_sel Date: Tue, 22 Mar 2022 00:15:40 +0100 Message-Id: <20220321231548.14276-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop hardcoded safe_sel definition and use helper to correctly calculate it. We assume qsb clk is always present as it should be declared in DTS per Documentation and in the absence of that, it's declared as a fixed clk. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 40 +++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index e9508e3104ea..5f98ee1c3681 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -26,6 +26,17 @@ static unsigned int pri_mux_map[] = { 0, }; +static u8 krait_get_mux_sel(struct krait_mux_clk *mux, struct clk *safe_clk) +{ + struct clk_hw *safe_hw = __clk_get_hw(safe_clk); + + /* + * We can ignore errors from clk_hw_get_index_of_parent() + * as we create these parents in this driver. + */ + return clk_hw_get_index_of_parent(&mux->hw, safe_hw); +} + /* * Notifier function for switching the muxes to safe parent * while the hfpll is getting reprogrammed. @@ -116,8 +127,8 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) } static struct clk * -krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) +krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, + const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; @@ -144,7 +155,6 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; - mux->safe_sel = 0; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) @@ -166,6 +176,7 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, qsb); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -204,7 +215,6 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux mux->lpl = id >= 0; mux->parent_map = pri_mux_map; mux->hw.init = &init; - mux->safe_sel = 2; init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); if (!init.name) @@ -226,6 +236,7 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, sec_mux); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -238,7 +249,9 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux } /* id < 0 for L2, otherwise id == physical CPU number */ -static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) +static struct clk * +krait_add_clks(struct device *dev, struct clk *qsb, int id, + bool unique_aux) { unsigned int offset; void *p = NULL; @@ -261,7 +274,7 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) goto err; } - sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + sec_mux = krait_add_sec_mux(dev, qsb, id, s, offset, unique_aux); if (IS_ERR(sec_mux)) { clk = sec_mux; goto err; @@ -301,18 +314,19 @@ static int krait_cc_probe(struct platform_device *pdev) int cpu; struct clk *clk; struct clk **clks; - struct clk *l2_pri_mux_clk; + struct clk *l2_pri_mux_clk, *qsb; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - if (IS_ERR(clk_get(dev, "qsb"))) - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + qsb = clk_get(dev, "qsb"); + if (IS_ERR(qsb)) + qsb = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(qsb)) + return PTR_ERR(qsb); if (!id->data) { clk = clk_register_fixed_factor(dev, "acpu_aux", @@ -327,13 +341,13 @@ static int krait_cc_probe(struct platform_device *pdev) return -ENOMEM; for_each_possible_cpu(cpu) { - clk = krait_add_clks(dev, cpu, id->data); + clk = krait_add_clks(dev, qsb, cpu, id->data); if (IS_ERR(clk)) return PTR_ERR(clk); clks[cpu] = clk; } - l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); + l2_pri_mux_clk = krait_add_clks(dev, qsb, -1, id->data); if (IS_ERR(l2_pri_mux_clk)) return PTR_ERR(l2_pri_mux_clk); clks[4] = l2_pri_mux_clk; From patchwork Mon Mar 21 23:15:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A6E3C433EF for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:23 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 11/18] clk: qcom: krait-cc: force sec_mux to QSB Date: Tue, 22 Mar 2022 00:15:41 +0100 Message-Id: <20220321231548.14276-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that we have converted every driver to parent_data, it was notice that the bootloader can't really leave the system in a strange state where l2 or the cpu0/1 can be sourced in a number of ways for example cpu1 sourcing out of qsb, l2 sourcing out of pxo. To correctly reset the mux and the HFPLL force the sec_mux to QSB. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 5f98ee1c3681..299eb4c81d96 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -15,6 +15,8 @@ #include "clk-krait.h" +#define QSB_RATE 1 + static unsigned int sec_mux_map[] = { 2, 0, @@ -181,6 +183,13 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, if (ret) clk = ERR_PTR(ret); + /* + * Force the sec_mux to be set to QSB rate. + * This is needed to correctly set the parents and + * to later reset mux and HFPLL to a known freq. + */ + clk_set_rate(clk, QSB_RATE); + err_clk: if (unique_aux) kfree(parent_name); @@ -378,7 +387,7 @@ static int krait_cc_probe(struct platform_device *pdev) */ cur_rate = clk_get_rate(l2_pri_mux_clk); aux_rate = 384000000; - if (cur_rate == 1) { + if (cur_rate == QSB_RATE) { dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate = aux_rate; } @@ -389,7 +398,7 @@ static int krait_cc_probe(struct platform_device *pdev) for_each_possible_cpu(cpu) { clk = clks[cpu]; cur_rate = clk_get_rate(clk); - if (cur_rate == 1) { + if (cur_rate == QSB_RATE) { dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate = aux_rate; } From patchwork Mon Mar 21 23:15:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D58A8C43219 for ; Mon, 21 Mar 2022 23:45:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233319AbiCUXq6 (ORCPT ); Mon, 21 Mar 2022 19:46:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233192AbiCUXqx (ORCPT ); Mon, 21 Mar 2022 19:46:53 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A44849680E; Mon, 21 Mar 2022 16:45:26 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id r190-20020a1c2bc7000000b0038a1013241dso416136wmr.1; Mon, 21 Mar 2022 16:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/RImxULSEIcXltj7eh82B63gODFmYdSpUPrpbmj5VVA=; b=jT8RgMISQDjRNDcRrqAokCQH0i2UNigwlMocsqfEHXQLW5VSAEPDEOQO1dTn+vxDD/ zsFL4P7xIIk974szJEwNcxbw67WFBDJyFA21HSeEaUHdjDu6Hhi7zo2zzTE0L3NLESmz hyuaq93dNO+38/sEg31Ut6w9nOtPETbit0XsCr+Z1eX4rvnRwIyGpPHT05cllPFTgU3n 0mNCVCBurhC4Iy03d81Nr6F/kew7VWLiU1ocy05b3CZrvv5kJPdtFD+OO3xAKDs6NNqa +Zz+hicc3iz4fk/Pf9K8ZNGTmUg2RjKt8l6A9EFcMDJc+sITlSjj1dACPJJ3R252nyHU HdbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/RImxULSEIcXltj7eh82B63gODFmYdSpUPrpbmj5VVA=; b=ee+SUTSM9RNXZG1ym9LhrDgBKIGpdmXmXSDdIT+8DJK0dkGgZrzd2wUr5RHjRH5D9O AbejzcCJK1aZHKAoiQFadgJMSko7QkTTGQo+aThmES3jWR2CIqWaIY4jfWGnB3WgO8/K N8zCItJG1TzcfjYXMnUuboABhzTCTctAKYVeyJ7Q5JAZZzgYabrrhPglWDC8Vc/gwN0h jz6Z8f/tefajb1OxGw432i8zG4teeAMO6RN+MayJTRhlsmlw/fKji9DjkRcHpiDXSbg5 M0W8/KvcfsYUyZYwYxiRLezQUIUbzkD0pKysgmjUZRvWcRmgZ8uK9uimjUcfqH6niHSB VPXg== X-Gm-Message-State: AOAM530cMmuA5lebbkPVB8P04e3+dPx2AxTyNgKxx7lYpGuXXohupeDZ OXKPaFsu26parKkE4lTYxg8= X-Google-Smtp-Source: ABdhPJwATjUZNJIuk7EjZPvgWAjvfl/FZpAz2RfXwPuyrBEv6wLzrqBlm2oO+VvYsEDNsCj1Hu8TCQ== X-Received: by 2002:a05:600c:500e:b0:38c:6d79:d5ac with SMTP id n14-20020a05600c500e00b0038c6d79d5acmr1303350wmr.42.1647906324864; Mon, 21 Mar 2022 16:45:24 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:24 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 12/18] clk: qcom: clk-krait: add apq/ipq8064 errata workaround Date: Tue, 22 Mar 2022 00:15:42 +0100 Message-Id: <20220321231548.14276-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add apq/ipq8064 errata workaround where the sec_src clock gating needs to be disabled during switching. To enable this set disable_sec_src_gating in the mux struct. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ drivers/clk/qcom/clk-krait.h | 1 + drivers/clk/qcom/krait-cc.c | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index b6b7650dbf15..7ba5dbc72bce 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -18,13 +18,23 @@ static DEFINE_SPINLOCK(krait_clock_reg_lock); #define LPL_SHIFT 8 +#define SECCLKAGD BIT(4) + static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) { unsigned long flags; u32 regval; spin_lock_irqsave(&krait_clock_reg_lock, flags); + regval = krait_get_l2_indirect_reg(mux->offset); + + /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ + if (mux->disable_sec_src_gating) { + regval |= SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + regval &= ~(mux->mask << mux->shift); regval |= (sel & mux->mask) << mux->shift; if (mux->lpl) { @@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) } krait_set_l2_indirect_reg(mux->offset, regval); + /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ + if (mux->disable_sec_src_gating) { + regval &= ~SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + /* Wait for switch to complete. */ mb(); udelay(1); diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h index 9120bd2f5297..f930538c539e 100644 --- a/drivers/clk/qcom/clk-krait.h +++ b/drivers/clk/qcom/clk-krait.h @@ -15,6 +15,7 @@ struct krait_mux_clk { u8 safe_sel; u8 old_index; bool reparent; + bool disable_sec_src_gating; struct clk_hw hw; struct notifier_block clk_nb; diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 299eb4c81d96..cb8b267f1dc5 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -157,6 +157,7 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; + mux->disable_sec_src_gating = true; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) From patchwork Mon Mar 21 23:15:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 259F7C433FE for ; Mon, 21 Mar 2022 23:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233356AbiCUXrA (ORCPT ); Mon, 21 Mar 2022 19:47:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233178AbiCUXqy (ORCPT ); Mon, 21 Mar 2022 19:46:54 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C292B53F1; Mon, 21 Mar 2022 16:45:27 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id o30-20020a05600c511e00b0038c9cfb79cbso501308wms.1; Mon, 21 Mar 2022 16:45:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QkfgyebL6ZDeFyix3jLmVd6pOSFa+uhSyC95dgb9bxk=; b=bge0TBx2KjLdT9bxG+d3B5PQrNAM+swGbZbw7/73YAo/TJh+4n+fSfEjHb8k44lo6m mZK8pJlbbwcz0YhVHXI+i7ER3FbBbwAXEJ95bYaT4+32AKUVJX/IDxD0EDtls5HUxkPL K2a0/wmLDaDY1j/c8EJ20IeMpL6CWq21X6c4N79csGgJ9NgJ9BCLQVA8RXNQHeDZUB9e +Fdo11CYYc2CwKRUqSluf2rynkK428wRIe158HA+WQSXO4ltMQiApDGsrTXQCHCuM7wx ZwSahXQp+zGBAzYacz3Bj5pgiDb2g58igMlKEO3FDmOidvY0ZsuoGaAgHimA0bKaf+e4 79vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QkfgyebL6ZDeFyix3jLmVd6pOSFa+uhSyC95dgb9bxk=; b=wuVhWPHQqep3k7cimQ5CCF6g7RxN9/GpbaxhqThr58gZEaqjS+5ds1R0Dpr+RNM0vX lAKWd8FH24FRXejS5DGUortJ6JbRo9lhHh8c75tMMIpFw1kEcKUWT/ssaAfgNj5UZHLr 9buntucdkRoZIogsdP5uGOGop8ziu+PNQf7Ci/3/vH1+ZNdvw09b25lZ4kl5OQ0bgVDz e9fspUf/PSYOTOAexEE5Q3x5VzqfxJKVwIx61BmjY95/Oa7cnhpy/7dtFQSEiR4yOn8c hYYzN/vEJxuovK0ZzWZeKTXgrKz86+NkPV+c53IPFB+05ZNEh6NxaT2Jc1glNyZcT/9e tQMw== X-Gm-Message-State: AOAM530P9Rlz+6DCCglXgIGjriIeDgPmcSCyV6XC68y+ie8L7qN+Zcbb 6Nn6PfaxSn/f19Wb4jAuOTc= X-Google-Smtp-Source: ABdhPJwkW2p7PHJBwZCI9ei0rE/h0snTHL1QPZPHV8gfqAHhnM2mPHcGMoJOR9bqyon0jUX13coDUg== X-Received: by 2002:a05:600c:a0b:b0:389:dd65:66f1 with SMTP id z11-20020a05600c0a0b00b00389dd6566f1mr1190829wmp.95.1647906325852; Mon, 21 Mar 2022 16:45:25 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:25 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 13/18] clk: qcom: clk-krait: add enable disable ops Date: Tue, 22 Mar 2022 00:15:43 +0100 Message-Id: <20220321231548.14276-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add enable/disable ops for krait mux. On disable the mux is set to the safe selection. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 7ba5dbc72bce..061af57b0ec2 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -85,7 +85,25 @@ static u8 krait_mux_get_parent(struct clk_hw *hw) return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); } +static int krait_mux_enable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux = to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->en_mask); + + return 0; +} + +static void krait_mux_disable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux = to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->safe_sel); +} + const struct clk_ops krait_mux_clk_ops = { + .enable = krait_mux_enable, + .disable = krait_mux_disable, .set_parent = krait_mux_set_parent, .get_parent = krait_mux_get_parent, .determine_rate = __clk_mux_determine_rate_closest, From patchwork Mon Mar 21 23:15:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 399ECC3527C for ; Mon, 21 Mar 2022 23:45:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233369AbiCUXrB (ORCPT ); Mon, 21 Mar 2022 19:47:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233338AbiCUXqz (ORCPT ); Mon, 21 Mar 2022 19:46:55 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C75691AF4; Mon, 21 Mar 2022 16:45:28 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id l1-20020a05600c4f0100b00389645443d2so412938wmq.2; Mon, 21 Mar 2022 16:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e6HTTfg5BzZgVlVHutoMY6UjT5iplTny53rcKCZeVPU=; b=PVL1e/yLpcERWhKSxxjbLncs/sUbbCuOGNWZoBrH+lQWJ8L3CaMJbUExRQsfRYaLoB 0DFL4THwUWhveGMgSWE+euxJ12GQkwDQAOLTKQ7peZMmmFXKUxoODlqrq0D2H486HPR7 prT3SFQvnDNq4M+3vGAVEAmVQawrMbN3NiUx7ESd5FPopCgQ3Ajb0YdADbK6zNmyO11K nJcs3EdfOTzzan439a8sLPSU5JavBYegzirEtRI5tfnY/TWCan6A+o0WkFz5PbMgKIqM Wn7d9DJUP89gJX6f8j2xp1sLI/dPzei7APXejubxa8VAqPkPtUeIr1PEb2TYScMPjno+ 76mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e6HTTfg5BzZgVlVHutoMY6UjT5iplTny53rcKCZeVPU=; b=NB3/0O8bLjDFcL9g6Oo/KP5UgOw+ah5W9sylqebuG6mliZBtMmTR0oGqA2wqo9ROlp nbi/uuXGw97SARGX/gaabAohmBG0k+fty0Ed2QSUHTmSPiR32gbzeDOwh3W3U8GgHVDl AuRAI8TqS4eIxLxZazSmXp31oSBMcBH8DfRfCDUIj+MmHiaWJ1gVlOBNAymwOyALTx5I x7DcRYzlj/1do+gZ63OSvQprT2Z2SF1Is4NAwuOlSCOLuCRwNDa4lBSuv5Ix88F+IW4a d//XR71CQ+3W0hmtyO9CKJFaGWz8TI4sHJNvDEgy1u7jBPQAuh43E0BjpCsc+II7y94v xdfw== X-Gm-Message-State: AOAM532U0skQFKKnu5AN76hD68bB5q+f8SM8ZDn/94OHK/x+dEug0hnl ziQxytpkR2H6WD5TbsSuGgHz/x8g3q0= X-Google-Smtp-Source: ABdhPJy0hf1F18M/HatE6xJRAfR3mCABejssZyLB0WBGrEFeK/UdvrtJTRki5nF5ClDunFnJWR4yFQ== X-Received: by 2002:a1c:7715:0:b0:380:ed9b:debd with SMTP id t21-20020a1c7715000000b00380ed9bdebdmr1265154wmi.54.1647906326931; Mon, 21 Mar 2022 16:45:26 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:26 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v6 14/18] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Tue, 22 Mar 2022 00:15:44 +0100 Message-Id: <20220321231548.14276-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert qcom,krait-cc to yaml Documentation. Signed-off-by: Ansuel Smith Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../bindings/clock/qcom,krait-cc.txt | 34 ----------- .../bindings/clock/qcom,krait-cc.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..e879bfbe67ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Ansuel Smith + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: acpu0_aux + - const: acpu1_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&hfpll0>, <&hfpll1>, + <&acpu0_aux>, <&acpu1_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", + "acpu0_aux", "acpu1_aux", "qsb"; + #clock-cells = <1>; + }; +... From patchwork Mon Mar 21 23:15:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC509C4332F for ; Mon, 21 Mar 2022 23:45:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233351AbiCUXq7 (ORCPT ); Mon, 21 Mar 2022 19:46:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233252AbiCUXq4 (ORCPT ); Mon, 21 Mar 2022 19:46:56 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DB27DE09B; Mon, 21 Mar 2022 16:45:29 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id d7so22756302wrb.7; Mon, 21 Mar 2022 16:45:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K/YdzwT6SzO2Fufqs+3VjNkZ7pK2lc35vBubZjd9sSo=; b=qpCSDArJms2zr0r7JCBIwZbWYktgyNWaD+UYTox41F+eoSSHLpHWuIsAJgfshcGHLP SE5K8ag3YOdyO662rINwWMtyXK6xx6hcNeGvd21cyCrH88775/jvotIOPPmb15YMUisa Nn2PsFfNZOLiUwGjVdU5w7TBdyAaLbniOzgvZFp8p6LNONda7INuMplQxLYxG8WnZzH9 +bMtiKhfL0lQPxbZHOsDJHwDweNKwMoU+Qjn6mX4qALSFqR8vBijGFzy3gLbfa7QGoir CXWq2ZS8eeVCa74m+DEiLzOoBY8TdYK+UZVJlVFaV3h77ou8JrUfA5SGpHMLvO+eVeNX WgLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K/YdzwT6SzO2Fufqs+3VjNkZ7pK2lc35vBubZjd9sSo=; b=IkoN4MRQQClIbrNbZRx43LNUEHklb0AjigqCVT2DwnsNOd7+8g5o1IJ7Yyy2iWC/Zf iABRrL/NDOkPSwv0hTKytN3Njex7/FWZVUZW39gOizO7+lxwjy1l/wQB02Oa1Ui408+6 rElDTvRRcjYY3vEYZtPlV05rDgwMv23We9ybdY7Ii4eKthu5f5CeGrND+DCtwjsxYzzW 8HdNcKS3SzlgC5RIKW1GTY4LWA/++8RUurR8zNjQE/asL+4EE33eeVKGNQ1LVO+ycVck +7hmn0kM8IKKmfp9SBi8qW2pQJaM0XLmn8/mbHSecg9LX/C+XMxctdxJhKsJgbpfLUtq xtaw== X-Gm-Message-State: AOAM5302hDgHeUh9w63RUB7jSvN6Ixbm0cQCpaM9AyoMNocKenBDgAZP pdOU2txSYhc9cBzzxlDyOjs= X-Google-Smtp-Source: ABdhPJwzrJh8StunMpQ1GvycDhtu+wkcSpS1ivCr2z0tEccGE0oiuOpn6/dMDUC/19y7M9+cmDrg0Q== X-Received: by 2002:adf:e4c2:0:b0:204:6d8:ce9a with SMTP id v2-20020adfe4c2000000b0020406d8ce9amr8714240wrm.189.1647906328047; Mon, 21 Mar 2022 16:45:28 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:27 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v6 15/18] dt-bindings: clock: Add L2 clocks to qcom,krait-cc Documentation Date: Tue, 22 Mar 2022 00:15:45 +0100 Message-Id: <20220321231548.14276-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Krait-cc qcom driver provide also L2 clocks and require the acpu_l2_aux and the hfpll_l2 clock to be provided. Add these missing clocks to the Documentation. The driver keep support for both old (it did already used these clocks and we keep the same naming scheme) and this new implementation and should prevent any regression by this fixup. Signed-off-by: Ansuel Smith Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/qcom,krait-cc.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml index e879bfbe67ac..de4320a85764 100644 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -26,6 +26,8 @@ properties: - description: phandle to CPU0 aux clock - description: phandle to CPU1 aux clock - description: phandle to QSB fixed clk + - description: phandle to hfpll for L2 mux + - description: phandle to L2 aux clock clock-names: items: @@ -34,6 +36,8 @@ properties: - const: acpu0_aux - const: acpu1_aux - const: qsb + - const: hfpll_l2 + - const: acpu_l2_aux '#clock-cells': const: 1 @@ -51,9 +55,11 @@ examples: clock-controller { compatible = "qcom,krait-cc-v1"; clocks = <&hfpll0>, <&hfpll1>, - <&acpu0_aux>, <&acpu1_aux>, <&qsb>; + <&acpu0_aux>, <&acpu1_aux>, <&qsb>, + <&hfpll_l2>, <&acpu_l2_aux>; clock-names = "hfpll0", "hfpll1", - "acpu0_aux", "acpu1_aux", "qsb"; + "acpu0_aux", "acpu1_aux", "qsb", + "hfpll_l2", "acpu_l2_aux"; #clock-cells = <1>; }; ... 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:28 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 16/18] dt-bindings: arm: msm: Convert kpss-acc driver Documentation to yaml Date: Tue, 22 Mar 2022 00:15:46 +0100 Message-Id: <20220321231548.14276-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, limit all the additional bindings (clocks, clock-names, clock-output-names and #clock-cells) to v1 and also flag that these bindings should NOT be used for v2. Signed-off-by: Ansuel Smith Reviewed-by: Krzysztof Kozlowski --- .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ---------- .../bindings/arm/msm/qcom,kpss-acc.yaml | 94 +++++++++++++++++++ 2 files changed, 94 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 7f696362a4a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: optional - Value type: - Definition: Name of the output clock. Typically acpuX_aux where X is a - CPU number starting at 0. - -Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml new file mode 100644 index 000000000000..707a81a6c30e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-acc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +maintainers: + - Ansuel Smith + +description: | + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. + +properties: + compatible: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,kpss-acc-v1 + then: + required: + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + else: + properties: + clocks: false + clock-names: false + clock-output-names: false + '#clock-cells': false + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + - | + clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; +... 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:29 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 17/18] dt-bindings: arm: msm: Convert kpss-gcc driver Documentation to yaml Date: Tue, 22 Mar 2022 00:15:47 +0100 Message-Id: <20220321231548.14276-18-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert kpss-gcc driver Documentation to yaml. Since kpss-gcc expose a clock add the required '#clock-cells' binding while converting it. Signed-off-by: Ansuel Smith --- .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 ------------ .../bindings/arm/msm/qcom,kpss-gcc.yaml | 69 +++++++++++++++++++ 2 files changed, 69 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..7eb852be02c1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Ansuel Smith + +description: | + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation). + +properties: + compatible: + items: + - enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 + - const: qcom,kpss-gcc + - const: syscon + + reg: + maxItems: 1 + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + const: acpu_l2_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; + }; +... + From patchwork Mon Mar 21 23:15:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12787930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 394DEC4332F for ; Mon, 21 Mar 2022 23:45:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233389AbiCUXrD (ORCPT ); Mon, 21 Mar 2022 19:47:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233364AbiCUXrB (ORCPT ); Mon, 21 Mar 2022 19:47:01 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2C05E543B; Mon, 21 Mar 2022 16:45:32 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id t11so22784200wrm.5; Mon, 21 Mar 2022 16:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KntnxEIslcAH3B4iwp3a7mNe3NHTLtligyxMWAIcv1w=; b=IatH+BimJzIeGHXk5nktn42eXk06Zme6ZQ8njFt25twK2Gg1kwx1lAhHdNM3LQH7dz mQFZo0e2p8BOB18UR7308LKprm543sjagjbNfVa7xolh6snNUJS7NY//vJx717tmKcAO VX1AGQLLa5srzJzP1XHx6DSjsWD+wQgpIE2iX5MedLCfH9UIPb4OIpH/PLDjct87tJNi o2zMbGQ6yNMMu7NHcxeAZZw7uxBp8rov8RDEIAzgsufcDCL/Vl/3M/Wpml5nkbc4D8UH NJTdg9nopJj7yFAZQM/XJHrnGno4rxyv8e89hbblshqp4ETX1p7Fs8BeFV1LfMEliGEe c13A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KntnxEIslcAH3B4iwp3a7mNe3NHTLtligyxMWAIcv1w=; b=qO1XKX3YsMU8G/m8SLjxv2kPcZsPl4c3cZ6yZP+Q2lWj0bxxuEr89Wpu0EOCgKx1R8 QgHDBNe+CnYbmmllBVaO2RUY0ta0DEDxUp0eA7Y84eEY2ehaCldKJa+wgGlJIJJHbFL3 0rbp4FcYN4FBpl+0DPLx5SRGLJHuvN3hnw2SLcVBaw3hYlCkZgHyE/h+RQIwv26YrhMW RemD3WG9Inot7tTepTMN9nEa5ygQME48FxwIapqqNp/ucpOJT5Z2s64IhXBn4Cp2JV8a tjOpIkG8Imn+tTi8Ttw/eJnYLkKXx+XtSQZebwEAO7203POf7V2sgSTDSR1DiUmt1573 gRRw== X-Gm-Message-State: AOAM530ob38ojaywrxDW1Kuu0SaDvzOwFfpNy/O++yc4/fRRikWV4YWu Ag5uCGAeDqgeQ62B42cY9X4= X-Google-Smtp-Source: ABdhPJzh7ultj61Cwbg82x0fZ0oejvG8K5EIEbFWAc88D2M17FPNoKw/alaKDcOEFmy0+XhslbGySg== X-Received: by 2002:a05:6000:1883:b0:1f0:44f6:4bc0 with SMTP id a3-20020a056000188300b001f044f64bc0mr20515015wri.659.1647906331098; Mon, 21 Mar 2022 16:45:31 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id n10-20020a5d588a000000b002052e4aaf89sm105497wrf.80.2022.03.21.16.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 16:45:30 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 18/18] ARM: dts: qcom: qcom-ipq8064: add missing krait-cc compatible and clocks Date: Tue, 22 Mar 2022 00:15:48 +0100 Message-Id: <20220321231548.14276-19-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321231548.14276-1-ansuelsmth@gmail.com> References: <20220321231548.14276-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing krait-cc clock-controller and define missing aux clock for CPUs. Also change phandle for l2cc node to point to pxo_board instead of gcc PXO_SRC. This should align ipq8064 dtsi to the new changes in the Documentation. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..cebb5561f5d1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -468,11 +468,19 @@ IRQ_TYPE_EDGE_RISING)>, acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; adm_dma: dma-controller@18300000 { @@ -780,11 +788,23 @@ tcsr: syscon@1a400000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; + }; + + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, <&gcc PLL10>, + <&acc0>, <&acc1>, <&qsb>, + <&gcc PLL12>, <&l2cc>; + clock-names = "hfpll0", "hfpll1", + "acpu0_aux", "acpu1_aux", "qsb", + "hfpll_l2", "acpu_l2_aux"; + #clock-cells = <1>; }; lcc: clock-controller@28000000 {