From patchwork Tue Mar 22 03:27:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 12788068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A14EC433F5 for ; Tue, 22 Mar 2022 03:27:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236043AbiCVD27 (ORCPT ); Mon, 21 Mar 2022 23:28:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235946AbiCVD26 (ORCPT ); Mon, 21 Mar 2022 23:28:58 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18500E8864; Mon, 21 Mar 2022 20:27:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647919650; x=1679455650; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=5oVRZuucaffVlCcq38pjgMlQwwxBCMH83akkiqAngfI=; b=gBB8+0x+xqlrSGo/gDZ0zWYXwlfcNWDoDFg92KOIJQXkcJ8DJFbI9Lcm LvMiGkAveMw6oVqPHB2CEOSHF6a9eJ7r9UyWE38xiads2w4S2urK7Pqk3 8A49IHQ/7u5lfjuLmPpBKQQmeaOwXPX0v9P1Cm4izcyo1eyDWDYC/K+lw k=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 21 Mar 2022 20:27:30 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 21 Mar 2022 20:27:28 -0700 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 22 Mar 2022 08:57:13 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id 2E7BD34EC; Tue, 22 Mar 2022 08:57:13 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dmitry.baryshkov@linaro.org, dianders@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v7 1/5] drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe Date: Tue, 22 Mar 2022 08:57:07 +0530 Message-Id: <1647919631-14447-2-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> References: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Set mdp clock to max clock rate during probe/bind sequence from the opp table so that rails are not at undetermined state. Since we do not know what will be the rate set in boot loader, it would be ideal to vote at max frequency. There could be a firmware display programmed in bootloader and we want to transition it to kernel without underflowing. The clock will be scaled down later when framework sends an update. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Vinod Polimera Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e29796c..9c346ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1202,7 +1202,9 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) struct platform_device *pdev = to_platform_device(dev); struct drm_device *ddev = priv->dev; struct dpu_kms *dpu_kms; + struct dev_pm_opp *opp; int ret = 0; + unsigned long max_freq = ULONG_MAX; dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); if (!dpu_kms) @@ -1225,6 +1227,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) } dpu_kms->num_clocks = ret; + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + + dev_pm_opp_set_rate(dev, max_freq); + platform_set_drvdata(pdev, dpu_kms); ret = msm_kms_init(&dpu_kms->base, &kms_funcs); From patchwork Tue Mar 22 03:27:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 12788071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E38EC433EF for ; Tue, 22 Mar 2022 03:27:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236061AbiCVD3D (ORCPT ); Mon, 21 Mar 2022 23:29:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235974AbiCVD26 (ORCPT ); Mon, 21 Mar 2022 23:28:58 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8ABCE6160; Mon, 21 Mar 2022 20:27:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647919652; x=1679455652; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=GBCchohdMxPmdCyHwZJ3vkgN2swoKj239vTmkcRZUrE=; b=l0zmM5YzDKztZSnXKjyiK4WCjAKU1qR3HJjrpFRPi+y/areLZRvu/a8f 5/Z9sADnVO49GqGdsyDv0Yh5OmrGApeoV/o3QoAezq79/ruWOCYGvZyeN xtceGoYIdC2DNpql/nAMFAe0eyDvU6D92jAXbZoA2D8ozom8c3mYF7POU 4=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 21 Mar 2022 20:27:31 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 21 Mar 2022 20:27:30 -0700 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 22 Mar 2022 08:57:13 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id 38BD85422; Tue, 22 Mar 2022 08:57:13 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dmitry.baryshkov@linaro.org, dianders@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v7 2/5] arm64: dts: qcom: sm7280: remove assigned-clock-rate property for mdp clk Date: Tue, 22 Mar 2022 08:57:08 +0530 Message-Id: <1647919631-14447-3-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> References: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1]. [1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/ Signed-off-by: Vinod Polimera Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index c07765d..a3c768c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3086,9 +3086,6 @@ "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -3122,11 +3119,9 @@ "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; From patchwork Tue Mar 22 03:27:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 12788073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62B4BC4321E for ; Tue, 22 Mar 2022 03:27:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235946AbiCVD3F (ORCPT ); Mon, 21 Mar 2022 23:29:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236049AbiCVD3A (ORCPT ); Mon, 21 Mar 2022 23:29:00 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 227A3E9CB5; Mon, 21 Mar 2022 20:27:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647919654; x=1679455654; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=NeQgRFIMFaBb8gkIXKoWb96J7lg5ULFzPB022MVbE2c=; b=U6XExGjIsHZlS066TSSmvIdxLvai95gIMwR/c37QCmmrYe5CxL5zi4kg Ld39VL703WxBvQt/UvVF4I0584Spi4jPxgRS0PfBXWCWVyPyfB0z4N+Hl JpidBfu/QepymKf0X9Uw1XF49Lm8JDEP8LGnFd5ZO8No0virRnNSneQQD o=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 21 Mar 2022 20:27:33 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 21 Mar 2022 20:27:31 -0700 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 22 Mar 2022 08:57:14 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id 5B74B542F; Tue, 22 Mar 2022 08:57:13 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dmitry.baryshkov@linaro.org, dianders@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v7 3/5] arm64: dts: qcom: sm7180: remove assigned-clock-rate property for mdp clk Date: Tue, 22 Mar 2022 08:57:09 +0530 Message-Id: <1647919631-14447-4-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> References: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1]. [1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/ Signed-off-by: Vinod Polimera Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e1c46b8..eaab746 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2900,9 +2900,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -2932,12 +2929,10 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; From patchwork Tue Mar 22 03:27:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 12788069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D1B9C4332F for ; Tue, 22 Mar 2022 03:27:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236065AbiCVD3B (ORCPT ); Mon, 21 Mar 2022 23:29:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235973AbiCVD26 (ORCPT ); Mon, 21 Mar 2022 23:28:58 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9718E6C70; Mon, 21 Mar 2022 20:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647919650; x=1679455650; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=JV56kTBjpmX1hZeTeSDVs4LHeu3Gqjm9WADnC4VbGtA=; b=GVgqWAxavAe+p8h8lnlk7V3D+0iNKajS34rRznziq3+1+B06OUFjQOSn 4yD7WsbEd7bVm1SioeLbmPuE/FmXA2A1bkLMqh9JQ6v4JdhMkN0U1VffO rNTxduG8oc4bhswRHu6EZtvzqCLJ+Gr50uTfC9ItnbZNxbcaaIHHaZCwR U=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 21 Mar 2022 20:27:28 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 21 Mar 2022 20:27:26 -0700 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 22 Mar 2022 08:57:14 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id 4761C5427; Tue, 22 Mar 2022 08:57:13 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dmitry.baryshkov@linaro.org, dianders@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v7 4/5] arm64: dts: qcom: sdm845: remove assigned-clock-rate property for mdp clk Date: Tue, 22 Mar 2022 08:57:10 +0530 Message-Id: <1647919631-14447-5-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> References: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1]. [1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/ Signed-off-by: Vinod Polimera Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 41f4e46..c0771d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4240,9 +4240,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -4273,10 +4270,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>; From patchwork Tue Mar 22 03:27:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 12788070 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DFFFC433F5 for ; Tue, 22 Mar 2022 03:27:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236048AbiCVD3C (ORCPT ); Mon, 21 Mar 2022 23:29:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236026AbiCVD26 (ORCPT ); Mon, 21 Mar 2022 23:28:58 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7D90E6C54; Mon, 21 Mar 2022 20:27:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647919653; x=1679455653; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=AQe3coGLYhfRueJtuJRs2iZrecXBTSwzh0qH7e4AO/E=; b=DaETbHzuhWXwwN7kb/8keHiuuRcadcKIVUuM0vDwoh/xVRteQPpbZcpu Bnw4OYnIVwb4NlyTS85Eom9OaiT8H2dvsgcCTLdZI2ZUZr60zGDasYbpW sHfvFDbYK04fX8A8yf0KH5uVN2uX9Oc+apu48SvfzcoWkJ6hF5Qju1xeh E=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 21 Mar 2022 20:27:32 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 21 Mar 2022 20:27:30 -0700 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg02-blr.qualcomm.com with ESMTP; 22 Mar 2022 08:57:15 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id 65A6B5429; Tue, 22 Mar 2022 08:57:13 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dmitry.baryshkov@linaro.org, dianders@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v7 5/5] arm64: dts: qcom: sm8250: remove assigned-clock-rate property for mdp clk Date: Tue, 22 Mar 2022 08:57:11 +0530 Message-Id: <1647919631-14447-6-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> References: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe") [1]. [1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/ Signed-off-by: Vinod Polimera Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index fdaf303..2105eb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3164,9 +3164,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "bus", "nrt_bus", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <460000000>; - interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -3191,10 +3188,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>;