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Thu, 24 Mar 2022 05:31:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT044.mail.protection.outlook.com (10.13.177.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5102.17 via Frontend Transport; Thu, 24 Mar 2022 05:31:34 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 24 Mar 2022 00:31:32 -0500 From: Manali Shukla To: , CC: Subject: [kvm-unit-tests PATCH v2 1/4] x86: nSVM: Move common functionality of the main() to helper run_svm_tests Date: Thu, 24 Mar 2022 05:30:43 +0000 Message-ID: <20220324053046.200556-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220324053046.200556-1-manali.shukla@amd.com> References: <20220324053046.200556-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98f95066-4945-47b1-9f4f-08da0d578f3a X-MS-TrafficTypeDiagnostic: DS7PR12MB6008:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2022 05:31:34.2021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98f95066-4945-47b1-9f4f-08da0d578f3a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6008 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org nSVM tests are "incompatible" with usermode due to __setup_vm() call in main function. If __setup_vm() is replaced with setup_vm() in main function, KUT will build the test with PT_USER_MASK set on all PTEs. nNPT tests will be moved to their own file so that the tests don't need to fiddle with page tables midway through. The quick and dirty approach would be to turn the current main() into a small helper, minus its call to __setup_vm() and call the helper function run_svm_tests() from main() function. No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Manali Shukla --- x86/svm.c | 14 +++++++++----- x86/svm.h | 1 + 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/x86/svm.c b/x86/svm.c index 3f94b2a..e93e780 100644 --- a/x86/svm.c +++ b/x86/svm.c @@ -406,17 +406,13 @@ test_wanted(const char *name, char *filters[], int filter_count) } } -int main(int ac, char **av) +int run_svm_tests(int ac, char **av) { - /* Omit PT_USER_MASK to allow tested host.CR4.SMEP=1. */ - pteval_t opt_mask = 0; int i = 0; ac--; av++; - __setup_vm(&opt_mask); - if (!this_cpu_has(X86_FEATURE_SVM)) { printf("SVM not availble\n"); return report_summary(); @@ -453,3 +449,11 @@ int main(int ac, char **av) return report_summary(); } + +int main(int ac, char **av) +{ + pteval_t opt_mask = 0; + + __setup_vm(&opt_mask); + return run_svm_tests(ac, av); +} diff --git a/x86/svm.h b/x86/svm.h index f74b13a..9ab3aa5 100644 --- a/x86/svm.h +++ b/x86/svm.h @@ -398,6 +398,7 @@ struct regs { typedef void (*test_guest_func)(struct svm_test *); +int run_svm_tests(int ac, char **av); u64 *npt_get_pte(u64 address); u64 *npt_get_pde(u64 address); u64 *npt_get_pdpe(void); From patchwork Thu Mar 24 05:30:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 12790371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 516EDC433F5 for ; Thu, 24 Mar 2022 05:32:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347707AbiCXFdi (ORCPT ); Thu, 24 Mar 2022 01:33:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347549AbiCXFdg (ORCPT ); Thu, 24 Mar 2022 01:33:36 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2072.outbound.protection.outlook.com [40.107.92.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A65896828 for ; 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Date: Thu, 24 Mar 2022 05:30:44 +0000 Message-ID: <20220324053046.200556-3-manali.shukla@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220324053046.200556-1-manali.shukla@amd.com> References: <20220324053046.200556-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: de5bf6fd-a988-46fd-5f03-08da0d579bce X-MS-TrafficTypeDiagnostic: BN8PR12MB3202:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7T3AstMHaeVq7aCQNijEVs0WFTZbkEYy3Jy/cGbJhtd3m/ZxnohdQekgwWKDu1rfbNR38bZBvXt2Iy5OW3EHN+XOQLLk8bm7XQH0mYjiyvFrL/RF+EkYokkh94pEUaTo4nldXwq0dnxKkBb7avk0Ji8XhLqx3XoBmG20Dk6aX5NIvA6Y9rmLjdOUiG9uPREiyVohyjlyoFJKRs5zQk6JDBJ7Mh1jGC9RqIMj64pLGNmUCMyBBfY/ltI8+h3dS3tXpIs9oDc2hc66zkIQNuTpJOFYNBNQXOoLeTOZ7nR1NHyMQs5Wsl9ZYYLHL1LBqG+p/U9ByO3JPoJVU02ShWMPp/BIi2BhCYCVIkRktE47EPjS5GnE4bdw4BuI0RiW1J/7lgdutmi3eCrXJPbrzdIeY5T+qDUoro7ZyR0RIOQLfeax0NNt1LzAq9DkQ26itzJgvejbDNYYk5ZB29pAW5poOOJOEE/xcha7GvW2L+cIYeTp2iZm7W+EgTITeppdtl61S32vukMUj8VbyrE4dJuS8BveeO/xErsutAyo1mbTLm5NK2pYmFPKxKwVID2Ni9gtI0icFQhCKPenqSG324lJDVwGpaFipi115mo2DksZULtCTXCmNv5PLrKcm0rx27UtTK/GeluxGf9YT77rFzi2IyaAJy6qKOyO8L3uw8wN+1c0St+aJUAB8cd1sHeETIP9jtwFLFgUvKME6c0Ehv7zqg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(8936002)(44832011)(30864003)(82310400004)(5660300002)(81166007)(356005)(1076003)(186003)(16526019)(26005)(2616005)(40460700003)(336012)(426003)(316002)(110136005)(508600001)(6666004)(7696005)(36860700001)(4326008)(47076005)(83380400001)(8676002)(70586007)(70206006)(36756003)(2906002)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2022 05:31:55.3030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de5bf6fd-a988-46fd-5f03-08da0d579bce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3202 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org nNPT test cases are moved to a separate file svm_npt.c so that they can be run independently with PTE_USER_MASK disabled. Rest of the test cases can be run with PTE_USER_MASK enabled. No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Manali Shukla --- x86/Makefile.common | 2 + x86/Makefile.x86_64 | 2 + x86/svm.c | 8 - x86/svm_npt.c | 386 ++++++++++++++++++++++++++++++++++++++++++++ x86/svm_tests.c | 372 ++---------------------------------------- x86/unittests.cfg | 6 + 6 files changed, 405 insertions(+), 371 deletions(-) create mode 100644 x86/svm_npt.c diff --git a/x86/Makefile.common b/x86/Makefile.common index b903988..5590afe 100644 --- a/x86/Makefile.common +++ b/x86/Makefile.common @@ -107,6 +107,8 @@ $(TEST_DIR)/access_test.$(bin): $(TEST_DIR)/access.o $(TEST_DIR)/vmx.$(bin): $(TEST_DIR)/access.o +$(TEST_DIR)/svm_npt.$(bin): $(TEST_DIR)/svm.o + $(TEST_DIR)/kvmclock_test.$(bin): $(TEST_DIR)/kvmclock.o $(TEST_DIR)/hyperv_synic.$(bin): $(TEST_DIR)/hyperv.o diff --git a/x86/Makefile.x86_64 b/x86/Makefile.x86_64 index f18c1e2..dbe5967 100644 --- a/x86/Makefile.x86_64 +++ b/x86/Makefile.x86_64 @@ -42,6 +42,7 @@ endif ifneq ($(CONFIG_EFI),y) tests += $(TEST_DIR)/access_test.$(exe) tests += $(TEST_DIR)/svm.$(exe) +tests += $(TEST_DIR)/svm_npt.$(exe) tests += $(TEST_DIR)/vmx.$(exe) endif @@ -55,3 +56,4 @@ $(TEST_DIR)/hyperv_clock.$(bin): $(TEST_DIR)/hyperv_clock.o $(TEST_DIR)/vmx.$(bin): $(TEST_DIR)/vmx_tests.o $(TEST_DIR)/svm.$(bin): $(TEST_DIR)/svm_tests.o +$(TEST_DIR)/svm_npt.$(bin): $(TEST_DIR)/svm_npt.o diff --git a/x86/svm.c b/x86/svm.c index e93e780..d0d523a 100644 --- a/x86/svm.c +++ b/x86/svm.c @@ -449,11 +449,3 @@ int run_svm_tests(int ac, char **av) return report_summary(); } - -int main(int ac, char **av) -{ - pteval_t opt_mask = 0; - - __setup_vm(&opt_mask); - return run_svm_tests(ac, av); -} diff --git a/x86/svm_npt.c b/x86/svm_npt.c new file mode 100644 index 0000000..4f80d9a --- /dev/null +++ b/x86/svm_npt.c @@ -0,0 +1,386 @@ +#include "svm.h" +#include "vm.h" +#include "alloc_page.h" +#include "vmalloc.h" + +static void *scratch_page; + +static void null_test(struct svm_test *test) +{ +} + +static void npt_np_prepare(struct svm_test *test) +{ + u64 *pte; + + scratch_page = alloc_page(); + pte = npt_get_pte((u64)scratch_page); + + *pte &= ~1ULL; +} + +static void npt_np_test(struct svm_test *test) +{ + (void) *(volatile u64 *)scratch_page; +} + +static bool npt_np_check(struct svm_test *test) +{ + u64 *pte = npt_get_pte((u64)scratch_page); + + *pte |= 1ULL; + + return (vmcb->control.exit_code == SVM_EXIT_NPF) + && (vmcb->control.exit_info_1 == 0x100000004ULL); +} + +static void npt_nx_prepare(struct svm_test *test) +{ + u64 *pte; + + test->scratch = rdmsr(MSR_EFER); + wrmsr(MSR_EFER, test->scratch | EFER_NX); + + /* Clear the guest's EFER.NX, it should not affect NPT behavior. */ + vmcb->save.efer &= ~EFER_NX; + + pte = npt_get_pte((u64)null_test); + + *pte |= PT64_NX_MASK; +} + +static bool npt_nx_check(struct svm_test *test) +{ + u64 *pte = npt_get_pte((u64)null_test); + + wrmsr(MSR_EFER, test->scratch); + + *pte &= ~PT64_NX_MASK; + + return (vmcb->control.exit_code == SVM_EXIT_NPF) + && (vmcb->control.exit_info_1 == 0x100000015ULL); +} + +static void npt_us_prepare(struct svm_test *test) +{ + u64 *pte; + + scratch_page = alloc_page(); + pte = npt_get_pte((u64)scratch_page); + + *pte &= ~(1ULL << 2); +} + +static void npt_us_test(struct svm_test *test) +{ + (void) *(volatile u64 *)scratch_page; +} + +static bool npt_us_check(struct svm_test *test) +{ + u64 *pte = npt_get_pte((u64)scratch_page); + + *pte |= (1ULL << 2); + + return (vmcb->control.exit_code == SVM_EXIT_NPF) + && (vmcb->control.exit_info_1 == 0x100000005ULL); +} + +static void npt_rw_prepare(struct svm_test *test) +{ + + u64 *pte; + + pte = npt_get_pte(0x80000); + + *pte &= ~(1ULL << 1); +} + +static void npt_rw_test(struct svm_test *test) +{ + u64 *data = (void*)(0x80000); + + *data = 0; +} + +static bool npt_rw_check(struct svm_test *test) +{ + u64 *pte = npt_get_pte(0x80000); + + *pte |= (1ULL << 1); + + return (vmcb->control.exit_code == SVM_EXIT_NPF) + && (vmcb->control.exit_info_1 == 0x100000007ULL); +} + +static void npt_rw_pfwalk_prepare(struct svm_test *test) +{ + + u64 *pte; + + pte = npt_get_pte(read_cr3()); + + *pte &= ~(1ULL << 1); +} + +static bool npt_rw_pfwalk_check(struct svm_test *test) +{ + u64 *pte = npt_get_pte(read_cr3()); + + *pte |= (1ULL << 1); + + return (vmcb->control.exit_code == SVM_EXIT_NPF) + && (vmcb->control.exit_info_1 == 0x200000007ULL) + && (vmcb->control.exit_info_2 == read_cr3()); +} + +static void npt_l1mmio_prepare(struct svm_test *test) +{ +} + +u32 nested_apic_version1; +u32 nested_apic_version2; + +static void npt_l1mmio_test(struct svm_test *test) +{ + volatile u32 *data = (volatile void*)(0xfee00030UL); + + nested_apic_version1 = *data; + nested_apic_version2 = *data; +} + +static bool npt_l1mmio_check(struct svm_test *test) +{ + volatile u32 *data = (volatile void*)(0xfee00030); + u32 lvr = *data; + + return nested_apic_version1 == lvr && nested_apic_version2 == lvr; +} + +static void npt_rw_l1mmio_prepare(struct svm_test *test) +{ + + u64 *pte; + + pte = npt_get_pte(0xfee00080); + + *pte &= ~(1ULL << 1); +} + +static void npt_rw_l1mmio_test(struct svm_test *test) +{ + volatile u32 *data = (volatile void*)(0xfee00080); + + *data = *data; +} + +static bool npt_rw_l1mmio_check(struct svm_test *test) +{ + u64 *pte = npt_get_pte(0xfee00080); + + *pte |= (1ULL << 1); + + return (vmcb->control.exit_code == SVM_EXIT_NPF) + && (vmcb->control.exit_info_1 == 0x100000007ULL); +} + +static void basic_guest_main(struct svm_test *test) +{ +} + +static void __svm_npt_rsvd_bits_test(u64 *pxe, u64 rsvd_bits, u64 efer, + ulong cr4, u64 guest_efer, ulong guest_cr4) +{ + u64 pxe_orig = *pxe; + int exit_reason; + u64 pfec; + + wrmsr(MSR_EFER, efer); + write_cr4(cr4); + + vmcb->save.efer = guest_efer; + vmcb->save.cr4 = guest_cr4; + + *pxe |= rsvd_bits; + + exit_reason = svm_vmrun(); + + report(exit_reason == SVM_EXIT_NPF, + "Wanted #NPF on rsvd bits = 0x%lx, got exit = 0x%x", rsvd_bits, exit_reason); + + if (pxe == npt_get_pdpe() || pxe == npt_get_pml4e()) { + /* + * The guest's page tables will blow up on a bad PDPE/PML4E, + * before starting the final walk of the guest page. + */ + pfec = 0x20000000full; + } else { + /* RSVD #NPF on final walk of guest page. */ + pfec = 0x10000000dULL; + + /* PFEC.FETCH=1 if NX=1 *or* SMEP=1. */ + if ((cr4 & X86_CR4_SMEP) || (efer & EFER_NX)) + pfec |= 0x10; + + } + + report(vmcb->control.exit_info_1 == pfec, + "Wanted PFEC = 0x%lx, got PFEC = %lx, PxE = 0x%lx. " + "host.NX = %u, host.SMEP = %u, guest.NX = %u, guest.SMEP = %u", + pfec, vmcb->control.exit_info_1, *pxe, + !!(efer & EFER_NX), !!(cr4 & X86_CR4_SMEP), + !!(guest_efer & EFER_NX), !!(guest_cr4 & X86_CR4_SMEP)); + + *pxe = pxe_orig; +} + +static void _svm_npt_rsvd_bits_test(u64 *pxe, u64 pxe_rsvd_bits, u64 efer, + ulong cr4, u64 guest_efer, ulong guest_cr4) +{ + u64 rsvd_bits; + int i; + + /* + * RDTSC or RDRAND can sometimes fail to generate a valid reserved bits + */ + if (!pxe_rsvd_bits) { + report_skip("svm_npt_rsvd_bits_test: Reserved bits are not valid"); + return; + } + + /* + * Test all combinations of guest/host EFER.NX and CR4.SMEP. If host + * EFER.NX=0, use NX as the reserved bit, otherwise use the passed in + * @pxe_rsvd_bits. + */ + for (i = 0; i < 16; i++) { + if (i & 1) { + rsvd_bits = pxe_rsvd_bits; + efer |= EFER_NX; + } else { + rsvd_bits = PT64_NX_MASK; + efer &= ~EFER_NX; + } + if (i & 2) + cr4 |= X86_CR4_SMEP; + else + cr4 &= ~X86_CR4_SMEP; + if (i & 4) + guest_efer |= EFER_NX; + else + guest_efer &= ~EFER_NX; + if (i & 8) + guest_cr4 |= X86_CR4_SMEP; + else + guest_cr4 &= ~X86_CR4_SMEP; + + __svm_npt_rsvd_bits_test(pxe, rsvd_bits, efer, cr4, + guest_efer, guest_cr4); + } +} + +static u64 get_random_bits(u64 hi, u64 low) +{ + unsigned retry = 5; + u64 rsvd_bits = 0; + + if (this_cpu_has(X86_FEATURE_RDRAND)) { + do { + rsvd_bits = (rdrand() << low) & GENMASK_ULL(hi, low); + retry--; + } while (!rsvd_bits && retry); + } + + if (!rsvd_bits) { + retry = 5; + do { + rsvd_bits = (rdtsc() << low) & GENMASK_ULL(hi, low); + retry--; + } while (!rsvd_bits && retry); + } + + return rsvd_bits; +} + +static void svm_npt_rsvd_bits_test(void) +{ + u64 saved_efer, host_efer, sg_efer, guest_efer; + ulong saved_cr4, host_cr4, sg_cr4, guest_cr4; + + if (!npt_supported()) { + report_skip("NPT not supported"); + return; + } + + saved_efer = host_efer = rdmsr(MSR_EFER); + saved_cr4 = host_cr4 = read_cr4(); + sg_efer = guest_efer = vmcb->save.efer; + sg_cr4 = guest_cr4 = vmcb->save.cr4; + + test_set_guest(basic_guest_main); + + /* + * 4k PTEs don't have reserved bits if MAXPHYADDR >= 52, just skip the + * sub-test. The NX test is still valid, but the extra bit of coverage + * isn't worth the extra complexity. + */ + if (cpuid_maxphyaddr() >= 52) + goto skip_pte_test; + + _svm_npt_rsvd_bits_test(npt_get_pte((u64)basic_guest_main), + get_random_bits(51, cpuid_maxphyaddr()), + host_efer, host_cr4, guest_efer, guest_cr4); + +skip_pte_test: + _svm_npt_rsvd_bits_test(npt_get_pde((u64)basic_guest_main), + get_random_bits(20, 13) | PT_PAGE_SIZE_MASK, + host_efer, host_cr4, guest_efer, guest_cr4); + + _svm_npt_rsvd_bits_test(npt_get_pdpe(), + PT_PAGE_SIZE_MASK | + (this_cpu_has(X86_FEATURE_GBPAGES) ? get_random_bits(29, 13) : 0), + host_efer, host_cr4, guest_efer, guest_cr4); + + _svm_npt_rsvd_bits_test(npt_get_pml4e(), BIT_ULL(8), + host_efer, host_cr4, guest_efer, guest_cr4); + + wrmsr(MSR_EFER, saved_efer); + write_cr4(saved_cr4); + vmcb->save.efer = sg_efer; + vmcb->save.cr4 = sg_cr4; +} + +int main(int ac, char **av) +{ + pteval_t opt_mask = 0; + + __setup_vm(&opt_mask); + return run_svm_tests(ac, av); +} + +#define TEST(name) { #name, .v2 = name } + +struct svm_test svm_tests[] = { + { "npt_nx", npt_supported, npt_nx_prepare, + default_prepare_gif_clear, null_test, + default_finished, npt_nx_check }, + { "npt_np", npt_supported, npt_np_prepare, + default_prepare_gif_clear, npt_np_test, + default_finished, npt_np_check }, + { "npt_us", npt_supported, npt_us_prepare, + default_prepare_gif_clear, npt_us_test, + default_finished, npt_us_check }, + { "npt_rw", npt_supported, npt_rw_prepare, + default_prepare_gif_clear, npt_rw_test, + default_finished, npt_rw_check }, + { "npt_rw_pfwalk", npt_supported, npt_rw_pfwalk_prepare, + default_prepare_gif_clear, null_test, + default_finished, npt_rw_pfwalk_check }, + { "npt_l1mmio", npt_supported, npt_l1mmio_prepare, + default_prepare_gif_clear, npt_l1mmio_test, + default_finished, npt_l1mmio_check }, + { "npt_rw_l1mmio", npt_supported, npt_rw_l1mmio_prepare, + default_prepare_gif_clear, npt_rw_l1mmio_test, + default_finished, npt_rw_l1mmio_check }, + TEST(svm_npt_rsvd_bits_test) +}; diff --git a/x86/svm_tests.c b/x86/svm_tests.c index 0707786..41980d9 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -10,11 +10,10 @@ #include "isr.h" #include "apic.h" #include "delay.h" +#include "vmalloc.h" #define SVM_EXIT_MAX_DR_INTERCEPT 0x3f -static void *scratch_page; - #define LATENCY_RUNS 1000000 extern u16 cpu_online_count; @@ -698,181 +697,6 @@ static bool sel_cr0_bug_check(struct svm_test *test) return vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE; } -static void npt_nx_prepare(struct svm_test *test) -{ - u64 *pte; - - test->scratch = rdmsr(MSR_EFER); - wrmsr(MSR_EFER, test->scratch | EFER_NX); - - /* Clear the guest's EFER.NX, it should not affect NPT behavior. */ - vmcb->save.efer &= ~EFER_NX; - - pte = npt_get_pte((u64)null_test); - - *pte |= PT64_NX_MASK; -} - -static bool npt_nx_check(struct svm_test *test) -{ - u64 *pte = npt_get_pte((u64)null_test); - - wrmsr(MSR_EFER, test->scratch); - - *pte &= ~PT64_NX_MASK; - - return (vmcb->control.exit_code == SVM_EXIT_NPF) - && (vmcb->control.exit_info_1 == 0x100000015ULL); -} - -static void npt_np_prepare(struct svm_test *test) -{ - u64 *pte; - - scratch_page = alloc_page(); - pte = npt_get_pte((u64)scratch_page); - - *pte &= ~1ULL; -} - -static void npt_np_test(struct svm_test *test) -{ - (void) *(volatile u64 *)scratch_page; -} - -static bool npt_np_check(struct svm_test *test) -{ - u64 *pte = npt_get_pte((u64)scratch_page); - - *pte |= 1ULL; - - return (vmcb->control.exit_code == SVM_EXIT_NPF) - && (vmcb->control.exit_info_1 == 0x100000004ULL); -} - -static void npt_us_prepare(struct svm_test *test) -{ - u64 *pte; - - scratch_page = alloc_page(); - pte = npt_get_pte((u64)scratch_page); - - *pte &= ~(1ULL << 2); -} - -static void npt_us_test(struct svm_test *test) -{ - (void) *(volatile u64 *)scratch_page; -} - -static bool npt_us_check(struct svm_test *test) -{ - u64 *pte = npt_get_pte((u64)scratch_page); - - *pte |= (1ULL << 2); - - return (vmcb->control.exit_code == SVM_EXIT_NPF) - && (vmcb->control.exit_info_1 == 0x100000005ULL); -} - -static void npt_rw_prepare(struct svm_test *test) -{ - - u64 *pte; - - pte = npt_get_pte(0x80000); - - *pte &= ~(1ULL << 1); -} - -static void npt_rw_test(struct svm_test *test) -{ - u64 *data = (void*)(0x80000); - - *data = 0; -} - -static bool npt_rw_check(struct svm_test *test) -{ - u64 *pte = npt_get_pte(0x80000); - - *pte |= (1ULL << 1); - - return (vmcb->control.exit_code == SVM_EXIT_NPF) - && (vmcb->control.exit_info_1 == 0x100000007ULL); -} - -static void npt_rw_pfwalk_prepare(struct svm_test *test) -{ - - u64 *pte; - - pte = npt_get_pte(read_cr3()); - - *pte &= ~(1ULL << 1); -} - -static bool npt_rw_pfwalk_check(struct svm_test *test) -{ - u64 *pte = npt_get_pte(read_cr3()); - - *pte |= (1ULL << 1); - - return (vmcb->control.exit_code == SVM_EXIT_NPF) - && (vmcb->control.exit_info_1 == 0x200000007ULL) - && (vmcb->control.exit_info_2 == read_cr3()); -} - -static void npt_l1mmio_prepare(struct svm_test *test) -{ -} - -u32 nested_apic_version1; -u32 nested_apic_version2; - -static void npt_l1mmio_test(struct svm_test *test) -{ - volatile u32 *data = (volatile void*)(0xfee00030UL); - - nested_apic_version1 = *data; - nested_apic_version2 = *data; -} - -static bool npt_l1mmio_check(struct svm_test *test) -{ - volatile u32 *data = (volatile void*)(0xfee00030); - u32 lvr = *data; - - return nested_apic_version1 == lvr && nested_apic_version2 == lvr; -} - -static void npt_rw_l1mmio_prepare(struct svm_test *test) -{ - - u64 *pte; - - pte = npt_get_pte(0xfee00080); - - *pte &= ~(1ULL << 1); -} - -static void npt_rw_l1mmio_test(struct svm_test *test) -{ - volatile u32 *data = (volatile void*)(0xfee00080); - - *data = *data; -} - -static bool npt_rw_l1mmio_check(struct svm_test *test) -{ - u64 *pte = npt_get_pte(0xfee00080); - - *pte |= (1ULL << 1); - - return (vmcb->control.exit_code == SVM_EXIT_NPF) - && (vmcb->control.exit_info_1 == 0x100000007ULL); -} - #define TSC_ADJUST_VALUE (1ll << 32) #define TSC_OFFSET_VALUE (~0ull << 48) static bool ok; @@ -2604,173 +2428,9 @@ static void svm_test_singlestep(void) vmcb->save.rip == (u64)&guest_end, "Test EFLAGS.TF on VMRUN: guest execution completion"); } -static void __svm_npt_rsvd_bits_test(u64 *pxe, u64 rsvd_bits, u64 efer, - ulong cr4, u64 guest_efer, ulong guest_cr4) -{ - u64 pxe_orig = *pxe; - int exit_reason; - u64 pfec; - - wrmsr(MSR_EFER, efer); - write_cr4(cr4); - - vmcb->save.efer = guest_efer; - vmcb->save.cr4 = guest_cr4; - - *pxe |= rsvd_bits; - - exit_reason = svm_vmrun(); - - report(exit_reason == SVM_EXIT_NPF, - "Wanted #NPF on rsvd bits = 0x%lx, got exit = 0x%x", rsvd_bits, exit_reason); - - if (pxe == npt_get_pdpe() || pxe == npt_get_pml4e()) { - /* - * The guest's page tables will blow up on a bad PDPE/PML4E, - * before starting the final walk of the guest page. - */ - pfec = 0x20000000full; - } else { - /* RSVD #NPF on final walk of guest page. */ - pfec = 0x10000000dULL; - - /* PFEC.FETCH=1 if NX=1 *or* SMEP=1. */ - if ((cr4 & X86_CR4_SMEP) || (efer & EFER_NX)) - pfec |= 0x10; - - } - - report(vmcb->control.exit_info_1 == pfec, - "Wanted PFEC = 0x%lx, got PFEC = %lx, PxE = 0x%lx. " - "host.NX = %u, host.SMEP = %u, guest.NX = %u, guest.SMEP = %u", - pfec, vmcb->control.exit_info_1, *pxe, - !!(efer & EFER_NX), !!(cr4 & X86_CR4_SMEP), - !!(guest_efer & EFER_NX), !!(guest_cr4 & X86_CR4_SMEP)); - - *pxe = pxe_orig; -} - -static void _svm_npt_rsvd_bits_test(u64 *pxe, u64 pxe_rsvd_bits, u64 efer, - ulong cr4, u64 guest_efer, ulong guest_cr4) -{ - u64 rsvd_bits; - int i; - - /* - * RDTSC or RDRAND can sometimes fail to generate a valid reserved bits - */ - if (!pxe_rsvd_bits) { - report_skip("svm_npt_rsvd_bits_test: Reserved bits are not valid"); - return; - } - - /* - * Test all combinations of guest/host EFER.NX and CR4.SMEP. If host - * EFER.NX=0, use NX as the reserved bit, otherwise use the passed in - * @pxe_rsvd_bits. - */ - for (i = 0; i < 16; i++) { - if (i & 1) { - rsvd_bits = pxe_rsvd_bits; - efer |= EFER_NX; - } else { - rsvd_bits = PT64_NX_MASK; - efer &= ~EFER_NX; - } - if (i & 2) - cr4 |= X86_CR4_SMEP; - else - cr4 &= ~X86_CR4_SMEP; - if (i & 4) - guest_efer |= EFER_NX; - else - guest_efer &= ~EFER_NX; - if (i & 8) - guest_cr4 |= X86_CR4_SMEP; - else - guest_cr4 &= ~X86_CR4_SMEP; - - __svm_npt_rsvd_bits_test(pxe, rsvd_bits, efer, cr4, - guest_efer, guest_cr4); - } -} - -static u64 get_random_bits(u64 hi, u64 low) -{ - unsigned retry = 5; - u64 rsvd_bits = 0; - - if (this_cpu_has(X86_FEATURE_RDRAND)) { - do { - rsvd_bits = (rdrand() << low) & GENMASK_ULL(hi, low); - retry--; - } while (!rsvd_bits && retry); - } - - if (!rsvd_bits) { - retry = 5; - do { - rsvd_bits = (rdtsc() << low) & GENMASK_ULL(hi, low); - retry--; - } while (!rsvd_bits && retry); - } - - return rsvd_bits; -} - - -static void svm_npt_rsvd_bits_test(void) -{ - u64 saved_efer, host_efer, sg_efer, guest_efer; - ulong saved_cr4, host_cr4, sg_cr4, guest_cr4; - - if (!npt_supported()) { - report_skip("NPT not supported"); - return; - } - - saved_efer = host_efer = rdmsr(MSR_EFER); - saved_cr4 = host_cr4 = read_cr4(); - sg_efer = guest_efer = vmcb->save.efer; - sg_cr4 = guest_cr4 = vmcb->save.cr4; - - test_set_guest(basic_guest_main); - - /* - * 4k PTEs don't have reserved bits if MAXPHYADDR >= 52, just skip the - * sub-test. The NX test is still valid, but the extra bit of coverage - * isn't worth the extra complexity. - */ - if (cpuid_maxphyaddr() >= 52) - goto skip_pte_test; - - _svm_npt_rsvd_bits_test(npt_get_pte((u64)basic_guest_main), - get_random_bits(51, cpuid_maxphyaddr()), - host_efer, host_cr4, guest_efer, guest_cr4); - -skip_pte_test: - _svm_npt_rsvd_bits_test(npt_get_pde((u64)basic_guest_main), - get_random_bits(20, 13) | PT_PAGE_SIZE_MASK, - host_efer, host_cr4, guest_efer, guest_cr4); - - _svm_npt_rsvd_bits_test(npt_get_pdpe(), - PT_PAGE_SIZE_MASK | - (this_cpu_has(X86_FEATURE_GBPAGES) ? get_random_bits(29, 13) : 0), - host_efer, host_cr4, guest_efer, guest_cr4); - - _svm_npt_rsvd_bits_test(npt_get_pml4e(), BIT_ULL(8), - host_efer, host_cr4, guest_efer, guest_cr4); - - wrmsr(MSR_EFER, saved_efer); - write_cr4(saved_cr4); - vmcb->save.efer = sg_efer; - vmcb->save.cr4 = sg_cr4; -} - static bool volatile svm_errata_reproduced = false; static unsigned long volatile physical = 0; - /* * * Test the following errata: @@ -3074,6 +2734,14 @@ static void svm_nm_test(void) "fnop with CR0.TS and CR0.EM unset no #NM excpetion"); } +int main(int ac, char **av) +{ + pteval_t opt_mask = 0; + + __setup_vm(&opt_mask); + return run_svm_tests(ac, av); +} + struct svm_test svm_tests[] = { { "null", default_supported, default_prepare, default_prepare_gif_clear, null_test, @@ -3117,27 +2785,6 @@ struct svm_test svm_tests[] = { { "sel_cr0_bug", default_supported, sel_cr0_bug_prepare, default_prepare_gif_clear, sel_cr0_bug_test, sel_cr0_bug_finished, sel_cr0_bug_check }, - { "npt_nx", npt_supported, npt_nx_prepare, - default_prepare_gif_clear, null_test, - default_finished, npt_nx_check }, - { "npt_np", npt_supported, npt_np_prepare, - default_prepare_gif_clear, npt_np_test, - default_finished, npt_np_check }, - { "npt_us", npt_supported, npt_us_prepare, - default_prepare_gif_clear, npt_us_test, - default_finished, npt_us_check }, - { "npt_rw", npt_supported, npt_rw_prepare, - default_prepare_gif_clear, npt_rw_test, - default_finished, npt_rw_check }, - { "npt_rw_pfwalk", npt_supported, npt_rw_pfwalk_prepare, - default_prepare_gif_clear, null_test, - default_finished, npt_rw_pfwalk_check }, - { "npt_l1mmio", npt_supported, npt_l1mmio_prepare, - default_prepare_gif_clear, npt_l1mmio_test, - default_finished, npt_l1mmio_check }, - { "npt_rw_l1mmio", npt_supported, npt_rw_l1mmio_prepare, - default_prepare_gif_clear, npt_rw_l1mmio_test, - default_finished, npt_rw_l1mmio_check }, { "tsc_adjust", tsc_adjust_supported, tsc_adjust_prepare, default_prepare_gif_clear, tsc_adjust_test, default_finished, tsc_adjust_check }, @@ -3189,7 +2836,6 @@ struct svm_test svm_tests[] = { vgif_check }, TEST(svm_cr4_osxsave_test), TEST(svm_guest_state_test), - TEST(svm_npt_rsvd_bits_test), TEST(svm_vmrun_errata_test), TEST(svm_vmload_vmsave), TEST(svm_test_singlestep), diff --git a/x86/unittests.cfg b/x86/unittests.cfg index 9a70ba3..0d14721 100644 --- a/x86/unittests.cfg +++ b/x86/unittests.cfg @@ -240,6 +240,12 @@ smp = 2 extra_params = -cpu max,+svm -m 4g arch = x86_64 +[svm_npt] +file = svm_npt.flat +smp = 2 +extra_params = -cpu max,+svm -m 4g +arch = x86_64 + [taskswitch] file = taskswitch.flat arch = i386 From patchwork Thu Mar 24 05:30:45 2022 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2022 05:32:18.6525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 650f4c31-f334-40d9-9aac-08da0d57a9bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2970 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Commit 916635a813e975600335c6c47250881b7a328971 (nSVM: Add test for NPT reserved bit and #NPF error code behavior) clears PT_USER_MASK for all svm testcases. Any tests that requires usermode access will fail after this commit. Above mentioned commit did changes in main() due to which other nSVM tests became "incompatible" with usermode Solution to this problem would be to set PT_USER_MASK on all PTEs. So that KUT will build other tests with PT_USER_MASK set on all PTEs. Suggested-by: Sean Christopherson Signed-off-by: Manali Shukla --- x86/svm_tests.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/x86/svm_tests.c b/x86/svm_tests.c index 41980d9..fce466e 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -10,7 +10,6 @@ #include "isr.h" #include "apic.h" #include "delay.h" -#include "vmalloc.h" #define SVM_EXIT_MAX_DR_INTERCEPT 0x3f @@ -2736,9 +2735,7 @@ static void svm_nm_test(void) int main(int ac, char **av) { - pteval_t opt_mask = 0; - - __setup_vm(&opt_mask); + setup_vm(); return run_svm_tests(ac, av); } From patchwork Thu Mar 24 05:30:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 12790373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A633C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT058.mail.protection.outlook.com (10.13.174.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5102.17 via Frontend Transport; Thu, 24 Mar 2022 05:32:40 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 24 Mar 2022 00:32:37 -0500 From: Manali Shukla To: , CC: Subject: [kvm-unit-tests PATCH v2 4/4] x86: nSVM: Build up the nested page table dynamically Date: Thu, 24 Mar 2022 05:30:46 +0000 Message-ID: <20220324053046.200556-5-manali.shukla@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220324053046.200556-1-manali.shukla@amd.com> References: <20220324053046.200556-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7ac110ee-f8fa-4f6c-bc34-08da0d57b6dc X-MS-TrafficTypeDiagnostic: BL0PR12MB4722:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2022 05:32:40.5550 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ac110ee-f8fa-4f6c-bc34-08da0d57b6dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4722 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Current implementation of nested page table does the page table build up statistically with 2048 PTEs and one pml4 entry. That is why current implementation is not extensible. New implementation does page table build up dynamically based on the RAM size of the VM which enables us to have separate memory range to test various npt test cases. Signed-off-by: Manali Shukla --- x86/svm.c | 163 ++++++++++++++++++++++++++++++++++---------------- x86/svm.h | 17 +++++- x86/svm_npt.c | 4 +- 3 files changed, 130 insertions(+), 54 deletions(-) diff --git a/x86/svm.c b/x86/svm.c index d0d523a..67dbe31 100644 --- a/x86/svm.c +++ b/x86/svm.c @@ -8,6 +8,7 @@ #include "desc.h" #include "msr.h" #include "vm.h" +#include "fwcfg.h" #include "smp.h" #include "types.h" #include "alloc_page.h" @@ -16,38 +17,67 @@ #include "vmalloc.h" /* for the nested page table*/ -u64 *pte[2048]; -u64 *pde[4]; -u64 *pdpe; u64 *pml4e; struct vmcb *vmcb; -u64 *npt_get_pte(u64 address) +u64* get_npt_pte(u64 *pml4, u64 guest_addr, int level) { - int i1, i2; + int l; + u64 *pt = pml4, iter_pte; + unsigned offset; + + assert(level >= 1 && level <= 4); + + for(l = NPT_PAGE_LEVEL; ; --l) { + offset = (guest_addr >> (((l - 1) * NPT_PGDIR_WIDTH) + 12)) + & NPT_PGDIR_MASK; + iter_pte = pt[offset]; + if (l == level) + break; + if (!(iter_pte & NPT_PRESENT)) + return false; + pt = (u64*)(iter_pte & PT_ADDR_MASK); + } + offset = (guest_addr >> (((l - 1) * NPT_PGDIR_WIDTH) + 12)) + & NPT_PGDIR_MASK; + return &pt[offset]; +} - address >>= 12; - i1 = (address >> 9) & 0x7ff; - i2 = address & 0x1ff; +void set_npt_pte(u64 *pml4, u64 guest_addr, + int level, u64 pte_val) +{ + int l; + unsigned long *pt = pml4; + unsigned offset; + + for (l = NPT_PAGE_LEVEL; ; --l) { + offset = (guest_addr >> (((l - 1) * NPT_PGDIR_WIDTH) + 12)) + & NPT_PGDIR_MASK; + if (l == level) + break; + if (!(pt[offset] & NPT_PRESENT)) + return; + pt = (u64*)(pt[offset] & PT_ADDR_MASK); + } + offset = (guest_addr >> (((l - 1) * NPT_PGDIR_WIDTH) + 12)) + & NPT_PGDIR_MASK; + pt[offset] = pte_val; +} - return &pte[i1][i2]; +u64 *npt_get_pte(u64 address) +{ + return get_npt_pte(npt_get_pml4e(), address, 1); } u64 *npt_get_pde(u64 address) { - int i1, i2; - - address >>= 21; - i1 = (address >> 9) & 0x3; - i2 = address & 0x1ff; - - return &pde[i1][i2]; + return get_npt_pte(npt_get_pml4e(), address, 2); } -u64 *npt_get_pdpe(void) +u64 *npt_get_pdpe(u64 address) { - return pdpe; + return get_npt_pte(npt_get_pml4e(), address, 3); } u64 *npt_get_pml4e(void) @@ -309,11 +339,72 @@ static void set_additional_vcpu_msr(void *msr_efer) wrmsr(MSR_EFER, (ulong)msr_efer | EFER_SVME); } +static void install_npt_entry(u64 *pml4, + int pte_level, + u64 guest_addr, + u64 pte, + u64 *pt_page) +{ + int level; + unsigned long *pt = pml4; + unsigned offset; + + for (level = NPT_PAGE_LEVEL; level > pte_level; --level) { + offset = (guest_addr >> (((level - 1) * NPT_PGDIR_WIDTH) + 12)) + & NPT_PGDIR_MASK; + if (!(pt[offset] & PT_PRESENT_MASK)) { + unsigned long *new_pt = pt_page; + if (!new_pt) { + new_pt = alloc_page(); + } else + pt_page = 0; + memset(new_pt, 0, PAGE_SIZE); + + pt[offset] = virt_to_phys(new_pt) | NPT_USER_ACCESS | + NPT_ACCESS_BIT | NPT_PRESENT | NPT_RW_ACCESS; + } + pt = phys_to_virt(pt[offset] & PT_ADDR_MASK); + } + offset = (guest_addr >> (((level - 1) * NPT_PGDIR_WIDTH) + 12)) + & NPT_PGDIR_MASK; + pt[offset] = pte | NPT_USER_ACCESS | NPT_ACCESS_BIT | NPT_DIRTY_BIT; +} + +void install_npt(u64 *pml4, u64 phys, u64 guest_addr, + u64 perm) +{ + install_npt_entry(pml4, 1, guest_addr, + (phys & PAGE_MASK) | perm, 0); +} + +static void setup_npt_range(u64 *pml4, u64 start, + u64 len, u64 perm) +{ + u64 phys = start; + u64 max = (u64)len + (u64)start; + + while (phys + PAGE_SIZE <= max) { + install_npt(pml4, phys, phys, perm); + phys += PAGE_SIZE; + } +} + +void setup_npt(void) { + u64 end_of_memory; + pml4e = alloc_page(); + + end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); + if (end_of_memory < (1ul << 32)) + end_of_memory = (1ul << 32); + + setup_npt_range(pml4e, 0, end_of_memory, + NPT_PRESENT | NPT_RW_ACCESS); +} + static void setup_svm(void) { void *hsave = alloc_page(); - u64 *page, address; - int i,j; + int i; wrmsr(MSR_VM_HSAVE_PA, virt_to_phys(hsave)); wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_SVME); @@ -335,37 +426,7 @@ static void setup_svm(void) * Build the page-table bottom-up and map everything with 4k * pages to get enough granularity for the NPT unit-tests. */ - - address = 0; - - /* PTE level */ - for (i = 0; i < 2048; ++i) { - page = alloc_page(); - - for (j = 0; j < 512; ++j, address += 4096) - page[j] = address | 0x067ULL; - - pte[i] = page; - } - - /* PDE level */ - for (i = 0; i < 4; ++i) { - page = alloc_page(); - - for (j = 0; j < 512; ++j) - page[j] = (u64)pte[(i * 512) + j] | 0x027ULL; - - pde[i] = page; - } - - /* PDPe level */ - pdpe = alloc_page(); - for (i = 0; i < 4; ++i) - pdpe[i] = ((u64)(pde[i])) | 0x27; - - /* PML4e level */ - pml4e = alloc_page(); - pml4e[0] = ((u64)pdpe) | 0x27; + setup_npt(); } int matched; diff --git a/x86/svm.h b/x86/svm.h index 9ab3aa5..7815f56 100644 --- a/x86/svm.h +++ b/x86/svm.h @@ -147,6 +147,17 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL +#define NPT_PAGE_LEVEL 4 +#define NPT_PGDIR_WIDTH 9 +#define NPT_PGDIR_MASK 511 + +#define NPT_PRESENT (1ul << 0) +#define NPT_RW_ACCESS (1ul << 1) +#define NPT_USER_ACCESS (1ul << 2) +#define NPT_ACCESS_BIT (1ul << 5) +#define NPT_DIRTY_BIT (1ul << 6) +#define NPT_NX_ACCESS (1ul << 63) + struct __attribute__ ((__packed__)) vmcb_seg { u16 selector; u16 attrib; @@ -401,7 +412,7 @@ typedef void (*test_guest_func)(struct svm_test *); int run_svm_tests(int ac, char **av); u64 *npt_get_pte(u64 address); u64 *npt_get_pde(u64 address); -u64 *npt_get_pdpe(void); +u64 *npt_get_pdpe(u64 address); u64 *npt_get_pml4e(void); bool smp_supported(void); bool default_supported(void); @@ -418,7 +429,11 @@ struct regs get_regs(void); void vmmcall(void); int __svm_vmrun(u64 rip); int svm_vmrun(void); +void setup_npt(void); void test_set_guest(test_guest_func func); +void install_npt(u64 *pml4, u64 phys, u64 guest_addr, u64 perm); +u64* get_npt_pte(u64 *pml4, u64 guest_addr, int level); +void set_npt_pte(u64 *pml4, u64 guest_addr, int level, u64 pte_val); extern struct vmcb *vmcb; extern struct svm_test svm_tests[]; diff --git a/x86/svm_npt.c b/x86/svm_npt.c index 4f80d9a..4f95ae0 100644 --- a/x86/svm_npt.c +++ b/x86/svm_npt.c @@ -208,7 +208,7 @@ static void __svm_npt_rsvd_bits_test(u64 *pxe, u64 rsvd_bits, u64 efer, report(exit_reason == SVM_EXIT_NPF, "Wanted #NPF on rsvd bits = 0x%lx, got exit = 0x%x", rsvd_bits, exit_reason); - if (pxe == npt_get_pdpe() || pxe == npt_get_pml4e()) { + if (pxe == npt_get_pdpe((u64)basic_guest_main) || pxe == npt_get_pml4e()) { /* * The guest's page tables will blow up on a bad PDPE/PML4E, * before starting the final walk of the guest page. @@ -336,7 +336,7 @@ skip_pte_test: get_random_bits(20, 13) | PT_PAGE_SIZE_MASK, host_efer, host_cr4, guest_efer, guest_cr4); - _svm_npt_rsvd_bits_test(npt_get_pdpe(), + _svm_npt_rsvd_bits_test(npt_get_pdpe((u64)basic_guest_main), PT_PAGE_SIZE_MASK | (this_cpu_has(X86_FEATURE_GBPAGES) ? get_random_bits(29, 13) : 0), host_efer, host_cr4, guest_efer, guest_cr4);