From patchwork Sat Mar 26 06:08:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 12792224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7A02C4332F for ; Sat, 26 Mar 2022 06:08:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231433AbiCZGKI (ORCPT ); Sat, 26 Mar 2022 02:10:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229708AbiCZGKH (ORCPT ); Sat, 26 Mar 2022 02:10:07 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98F3647AF6 for ; Fri, 25 Mar 2022 23:08:29 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id gb19so9402608pjb.1 for ; Fri, 25 Mar 2022 23:08:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=29ohcmk+WpMbeDVWQK/EG8Sg/hmSlIvrDXmbJsgg1AI=; b=B+UqxkOxdFdPEBgdSSeGzgmvxO5mOP0JYIY1EfcNmFxdiTbrcCrRmKngasA+1VSoyE Kgx+LAgfiouyQ3Fsfy7e0jg8WZZxut0cPwHw9wrTk00oMo4BDl+DuTIyjls4yHtyPO+L eWSq18/GShcaMHycr+HmzObBCcgs65+/GoqZC4/G6XYjO4uiPHZCZ5TndFjE85Eo+Tc8 UkWM5q9psyXrmBpTJah+G2+bdPgoO5k7ICiMXz3Lj735+JNkm/ZHyPZVLZdXh1cqME3q 3/Oo5eqrZjsOd9KWo4g+ym9D36iYzpSURkNunrLcosRu3Iybu7oIqH6OjRXxtvf1n7fd M/9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=29ohcmk+WpMbeDVWQK/EG8Sg/hmSlIvrDXmbJsgg1AI=; b=dh46fpMxsnU9P6fSNMPjT4lshmdEjqOrV3/QA5mKALawivn+0zv84X1O9aKztdCKSY wlUCnWpT0UoDITBL4wtbW5WZO2fwloOAQFjGk4CgBT86stf8NEhJpQkhZJcaL1tSv7yg 7L03wDM2PxcMfBlN9jG2O7EHVYWIsRzW5qldaYCJ7Erwm6R0wV0tg/Ax1jJcoHpqNCbc 8Lx9BhNpaz7uNd6PtRoHREZDXTumVMUDnNlMQ3PKfKvjh2NETZsqelKcoM92kO97UpOD 2jPPtIBvbPCEbdoVToKVhLPUBsYMDpVtbUlW22/7KoAmiE9a/md8XQZ3WZB+IfKziZSC 0uaA== X-Gm-Message-State: AOAM530tnTVNc/OGsX4GKgIMvBg9SGL27uneORmDmDrZiurw1CiZeblY qSnKKqmhhnB/j+4j1Ywm9Fy2mQ== X-Google-Smtp-Source: ABdhPJxkIIUxA6/qud0HKlVxagcAACOtgkeJL53JKLutEFJD+2R88ZNw46KOjL1emWIlfEGBIjvowg== X-Received: by 2002:a17:902:ce05:b0:14f:8cfa:1ace with SMTP id k5-20020a170902ce0500b0014f8cfa1acemr14974539plg.149.1648274908805; Fri, 25 Mar 2022 23:08:28 -0700 (PDT) Received: from localhost.localdomain ([223.233.78.42]) by smtp.gmail.com with ESMTPSA id p26-20020a63951a000000b003826aff3e41sm6944959pgd.33.2022.03.25.23.08.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 23:08:28 -0700 (PDT) From: Bhupesh Sharma To: linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Rob Herring Subject: [PATCH v4 1/2] dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC Date: Sat, 26 Mar 2022 11:38:09 +0530 Message-Id: <20220326060810.1797516-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220326060810.1797516-1-bhupesh.sharma@linaro.org> References: <20220326060810.1797516-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the PCIe DT bindings for SM8150 SoC. The PCIe IP is similar to the one used on SM8250. Cc: Lorenzo Pieralisi Cc: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 0adb56d5645e..fd8b6d1912e7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -14,6 +14,7 @@ - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8150" for sm8150 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 @@ -159,7 +160,7 @@ - "pipe" PIPE clock - clock-names: - Usage: required for sc8180x and sm8250 + Usage: required for sc8180x, sm8150 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -266,7 +267,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sc8180x, sdm845, sm8250 and sm8450 + Usage: required for sc8180x, sdm845, sm8150, sm8250 and sm8450 Value type: Definition: Should contain the following entries - "pci" PCIe core reset From patchwork Sat Mar 26 06:08:10 2022 Content-Type: text/plain; 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Fri, 25 Mar 2022 23:08:34 -0700 (PDT) Received: from localhost.localdomain ([223.233.78.42]) by smtp.gmail.com with ESMTPSA id p26-20020a63951a000000b003826aff3e41sm6944959pgd.33.2022.03.25.23.08.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 23:08:33 -0700 (PDT) From: Bhupesh Sharma To: linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Vinod Koul , Dmitry Baryshkov , Rob Herring Subject: [PATCH v4 2/2] PCI: qcom: Add SM8150 SoC support Date: Sat, 26 Mar 2022 11:38:10 +0530 Message-Id: <20220326060810.1797516-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220326060810.1797516-1-bhupesh.sharma@linaro.org> References: <20220326060810.1797516-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on SM8250. Hence the support is added reusing the members of ops_1_9_0. Cc: Vinod Koul Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring Signed-off-by: Bhupesh Sharma --- drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6ab90891801d..375f27ab9403 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1523,6 +1523,13 @@ static const struct qcom_pcie_cfg sdm845_cfg = { .has_tbu_clk = true, }; +static const struct qcom_pcie_cfg sm8150_cfg = { + /* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as + * 1.9.0, so reuse the same. + */ + .ops = &ops_1_9_0, +}; + static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, @@ -1655,6 +1662,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg }, { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, + { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },